WO2016019566A1

WO2016019566A1 - Memory management method, device and system and network-on-chip

Info

Publication number: WO2016019566A1
Application number: PCT/CN2014/083966
Authority: WO
Inventors: 蔡卫光; 程德华; 吴祖光
Original assignee: 华为技术有限公司
Priority date: 2014-08-08
Filing date: 2014-08-08
Publication date: 2016-02-11
Also published as: CN105518631A; CN105518631B

Abstract

Provided are a memory management method, device and system and a network-on-chip. The memory management method comprises: determining first physical pages allocated for a process from idle physical pages; sending an adjustment instruction to a memory manager, wherein the adjustment instruction is used for instructing the memory manager to exchange at least one pair of second physical pages in a physical memory, and each pair of second physical pages comprises one of the first physical pages with physical page numbers being non-consecutive and one non-idle physical page, so that the first physical page obtained after exchange and at least another first physical page are consecutive; and adding a table entry in a TLB page table of the process, wherein a mapping relationship between at least two consecutive first physical pages after being combined into a large physical page and virtual pages of the process is recorded in the table entry, and the large physical page comprises the first physical page obtained after exchange. The present invention can reduce the loss of performance caused by a TLB page fault in the application of a large memory.

Description

Memory management methods, devices and systems, and on-chip networks

Technical field

The present invention relates to the field of computer technologies, and in particular, to a memory management method, apparatus and system, and an on-chip network. Background technique

Page-based virtual memory technology is a core part of memory management in current computing systems. In this technique, the operating system divides the address space of physical memory into multiple consecutive physical pages, and divides the address space of the virtual memory that the program will use into multiple consecutive virtual pages. During the running of the program, the memory management unit converts the virtual address that the program needs to access to a physical address, and then accesses the physical memory according to the physical address.

The process of address translation is usually implemented using TLB (Translation Look-aside Buffer). Specifically, after obtaining the virtual address, the CPU determines the virtual page number according to the virtual address, and then searches for the virtual page number in the TLB entry of the process (the mapping relationship between the virtual page number and the physical page number is saved), if the TLB is in the TLB. If the virtual page number is found in the entry, it is called TLB hit (that is, TLB Hit), and the physical page number corresponding to the virtual page number is output, and the physical address is determined according to the physical page number; if the virtual address is not found, The page number indicates that the TLB Missing page (TLB Miss) has occurred. At this time, it is necessary to find the mapping information corresponding to the virtual page number (including the mapping relationship between the virtual page number and the physical page number) from the memory, and find the memory. The mapping information of the virtual page number is reloaded into the TLB for next use.

In the process of implementing the present invention, the inventors have found that the prior art has at least the following problems: The physical memory of the device configuration is getting larger and larger (for example, one server can integrate tens of GB or even TB of physical memory), while the TLB The resources are limited, and the number of TLB entries that can be saved is limited. Therefore, in large memory applications, the situation of TLB missing pages is very serious, resulting in a large system overhead. In the prior art, large page technology is usually used to reduce the system overhead caused by TLB page faults. The so-called large page technology, that is, increasing the page size, increasing the page size is equivalent to increasing the address space that each entry in the TLB can map. For the program, it is equivalent to reducing the number of pages used by the program. Large page technology can reduce the page fault overhead to a certain extent. However, experiments have shown that when the page size increases to a certain limit, the page fault overhead will not change, that is, the use of large page technology to reduce page fault overhead. Limited effect. Summary of the invention

In order to solve the problem that the TLB page fault is expensive in the large memory application in the prior art, the embodiment of the present invention provides a memory management method, device and system, and an on-chip network. The technical solution is as follows: In a first aspect, an embodiment of the present invention provides a memory management method, where the method includes: when a physical memory needs to be allocated for a process, determining, from an idle physical page, a number allocated to the process a physical page;

When the determined first physical page is at least two, and the determined first physical page has a physical page number discontinuous first physical page, sending an adjustment instruction to the memory manager, the adjusting The instruction is configured to instruct the memory manager to perform an exchange process on at least one pair of second physical pages in the physical memory, where each pair of the second physical page includes the first physical page in which the physical page number is discontinuous One and one non-idle physical page such that the first physical page obtained after the exchange is continuous with at least one other of the first physical pages;

Adding an entry in the address translation buffer TLB page table of the process, where the entry records that at least two consecutive first physical pages are merged into one large physical page and virtualized with the process A mapping relationship of pages, the large physical page including the first physical page obtained after the exchange.

In a first possible implementation manner of the first aspect, the memory manager is configured with a mapping table of a physical page number and an internal page number, where the adjustment instruction carries a first physical page number and a second physical page number. The storage instruction is configured to instruct the memory manager to exchange an internal page number corresponding to the first physical page number and the second physical page number, where the memory manager is configured to access the physical according to the internal page number RAM.

Further, in the first possible implementation manner, the method may further include: sending a reset instruction to the memory manager, where the reset instruction is used to instruct the memory manager to create the physical page number and A mapping table of internal page numbers.

In a second possible implementation manner of the first aspect, the adjustment instruction carries a first physical page number and a second physical page number, where the adjustment instruction is used to instruct the memory manager to exchange the first physical page The data in the physical page corresponding to the number and the data in the physical page corresponding to the second physical page number. In a second aspect, an embodiment of the present invention provides a memory management method, where the method includes: a memory manager receiving an adjustment instruction, where the adjustment instruction is used to instruct the memory manager to At least one pair of second physical pages in the physical memory is exchanged, and each pair of the second physical pages includes one of the first physical pages whose physical page numbers are discontinuous and one non-idle physical page, the A physical page is an idle physical page to be assigned to a process;

The physical page in the physical memory is exchanged according to the adjustment instruction, so that the first physical page obtained after the exchange is continuous with at least another of the first physical pages.

In a first possible implementation manner of the second aspect, the memory manager is configured with a mapping table of a physical page number and an internal page number, where the adjustment instruction carries the first physical page number and the second physical page number. The storage instruction is configured to instruct the memory manager to exchange an internal page number corresponding to the first physical page number and the second physical page number, where the memory manager is configured to access the physical according to the internal page number RAM.

Further, in the first possible implementation manner, the method may further include: receiving a reset instruction, where the reset instruction is used to instruct the memory manager to create a mapping table of the physical page number and the internal page number. ;

A mapping table of the physical page number and the internal page number is created according to the reset instruction.

Further, the method may further include:

Receiving a memory access instruction, where the memory access instruction includes a starting physical address and length information;

Converting a starting physical address in the memory access instruction to an internal address according to a mapping table of the physical page number and an internal page number;

The physical memory is accessed according to the internal address.

In a second possible implementation manner of the second aspect, the adjustment instruction carries a first physical page number and a second physical page number, where the adjustment instruction is used to instruct the memory manager to exchange the first physical page The data in the physical page corresponding to the number and the data in the physical page corresponding to the second physical page number. In a third aspect, an embodiment of the present invention provides a memory management apparatus, where the apparatus includes: a memory allocation module, configured to determine, when an physical memory needs to be allocated for a process, an idle physical page to allocate to the process a physical page;

a sending module, configured to: when the first physical page determined by the memory allocation module is at least two, and the first physical page that is determined to have a discontinuous physical page number in the first physical page, The memory manager sends an adjustment instruction, where the adjustment instruction is used to instruct the memory manager to perform an exchange process on at least one pair of second physical pages in the physical memory, where each pair of the second physical page includes the physical page One of the first physical pages that are not consecutive and one non-idle physical page, so that after the exchange The first physical page is continuous with at least one other of the first physical pages;

An entry processing module, configured to add an entry in the address translation buffer TLB page table of the process, where the entry records that at least two consecutive first physical pages are merged into one large physical page And a mapping relationship with the virtual page of the process, where the large physical page includes the first physical page obtained after the exchange.

In a first possible implementation manner of the third aspect, the memory manager is configured with a mapping table of a physical page number and an internal page number, where the adjustment instruction carries the first physical page number and the second physical page number. The storage instruction is configured to instruct the memory manager to exchange an internal page number corresponding to the first physical page number and the second physical page number, where the memory manager is configured to access the physical according to the internal page number RAM.

Further, in the first possible implementation, the sending module is further configured to send a reset instruction to the memory manager, where the reset instruction is used to instruct the memory manager to create the physical page A mapping table of numbers and internal page numbers.

In a second possible implementation manner of the third aspect, the adjustment instruction carries a first physical page number and a second physical page number, where the adjustment instruction is used to instruct the memory manager to exchange the first physical page The data in the physical page corresponding to the number and the data in the physical page corresponding to the second physical page number. In a fourth aspect, an embodiment of the present invention provides a memory management apparatus, where the apparatus includes: a receiving module, configured to receive an adjustment instruction, where the adjustment instruction is used to instruct the memory manager to at least the physical memory A pair of second physical pages are exchanged, each pair of the second physical pages including one of the first physical pages whose physical page numbers are discontinuous and one non-idle physical page, the first physical page being An empty physical page assigned to the process;

An execution module, configured to exchange physical pages in the physical memory according to the adjustment instruction received by the receiving module, so that the first physical page obtained after the exchange is continuous with at least another of the first physical pages of.

In a first possible implementation manner of the fourth aspect, the memory manager is configured with a mapping table of a physical page number and an internal page number, where the adjustment instruction carries a first physical page number and a second physical page number. The storage instruction is configured to instruct the memory manager to exchange an internal page number corresponding to the first physical page number and the second physical page number, where the memory manager is configured to access the physical according to the internal page number RAM.

Further, in the first possible implementation manner, the receiving module is further configured to receive a complex a bit instruction, the reset instruction is used to instruct the memory manager to create a mapping table of the physical page number and an internal page number; the execution module is further configured to: create the physical page number and an internal page number according to the reset instruction Mapping table.

Further, the receiving module is further configured to receive a memory access instruction, where the memory access instruction includes a starting physical address and length information;

Correspondingly, the device further includes:

An address conversion module, configured to convert a starting physical address in the memory access instruction into an internal address according to a mapping table of the physical page number and an internal page number;

And a memory access module, configured to access the physical memory according to the internal address obtained by the address translation module.

In a second possible implementation manner of the fourth aspect, the adjustment instruction carries a first physical page number and a second physical page number, where the adjustment instruction is used to instruct the memory manager to exchange the first physical page The data in the physical page corresponding to the number and the data in the physical page corresponding to the second physical page number. In a fifth aspect, an embodiment of the present invention provides a memory management apparatus, where the apparatus includes: a processor, a memory, a bus, and a communication interface; the memory is configured to store a computer to execute an instruction, and the processor and the memory pass The bus connection, when the computer is running, the processor executes the computer-executed instructions stored by the memory to cause the computer to perform the method of the first aspect. According to a sixth aspect, an embodiment of the present invention provides a memory management apparatus, where the apparatus includes: the apparatus includes: a processor, a memory, a bus, and a communication interface; the memory is configured to store a computer execution instruction, The processor is coupled to the memory via the bus, and when the computer is running, the processor executes the computer-executed instructions stored by the memory to cause the computer to perform the method as described in the second aspect method. According to a seventh aspect, an embodiment of the present invention provides a memory management system, where the system includes a central processor and a memory controller;

The central processing unit includes the memory management device of the third aspect or the fifth aspect; the memory controller includes the memory management device of the fourth aspect or the sixth aspect. In an eighth aspect, an embodiment of the present invention provides an on-chip network, where the on-chip network includes: multiple processors, multiple routers, and multiple memory controllers, and the processor passes the router and the memory controller connection;

The processor includes the memory management device according to the third aspect or the fifth aspect;

The router includes the memory management device according to the fourth aspect or the sixth aspect.

The technical solution provided by the embodiment of the present invention has the beneficial effects of: first determining the first physical page allocated to the process, and then performing an exchange process on the first physical page whose physical page number is discontinuous, thereby enabling the first physical body obtained after the exchange. The page is contiguous with another physical page, so that at least two consecutive first physical pages can be merged into one large physical page, which is added as an entry to the process's TLB page table, thereby reducing the process at the address. The number of TLB entries used during mapping, which in turn reduces TLB page fault overhead. DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described. It is obvious that the drawings in the following description are only some embodiments of the present invention. Other drawings may also be obtained from those of ordinary skill in the art in view of the drawings.

1 is a schematic structural diagram of a memory management system in a computer system;

2 is a flowchart of a memory management method according to Embodiment 1 of the present invention;

3 is a flowchart of a memory management method according to Embodiment 2 of the present invention;

4 is a flowchart of a memory management method according to Embodiment 3 of the present invention;

FIG. 5 is a flowchart of a memory management method according to Embodiment 4 of the present invention; FIG.

6 is a structural block diagram of a memory management apparatus according to Embodiment 5 of the present invention;

7 is a structural block diagram of a memory management apparatus according to Embodiment 6 of the present invention;

8 is a structural block diagram of a memory management apparatus according to Embodiment 7 of the present invention;

9 is a structural block diagram of a memory management apparatus according to Embodiment 8 of the present invention;

FIG. 10 is a structural block diagram of a memory management apparatus according to Embodiment 9 of the present invention; FIG.

11 is a structural block diagram of a memory management apparatus according to Embodiment 10 of the present invention;

FIG. 12 is a structural block diagram of a memory management system according to Embodiment 11 of the present invention; FIG.

FIG. 13 is a structural block diagram of an on-chip network according to Embodiment 12 of the present invention. detailed description

The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

Embodiments of the present invention provide a memory management method, apparatus, and system, which are applicable to a memory management system in a computer system. The structure of the memory management system will be described below in conjunction with FIG.

Referring to FIG. 1 , the memory management system 100 includes a central processing unit 110 (CPU), a memory controller 120, and a physical memory 130 (also referred to as a main memory, such as a dynamic random access memory). Memory, referred to as DRAM)). The CPU 110 is provided with an address generation unit 111 (AGU) and a memory management unit (MMU). The core part of the MMU 112 is a translation look-aside buffer (Translation Look-aside Buffer). , referred to as TLB).

The physical memory 130 stores a page table of each process, and the page table of the process is used to record the physical page number of the physical page that is arranged in the main memory when the virtual page of the process is loaded into the main memory. Typically, each process corresponds to a page table, the complete page table of the process is stored in a specific area of the main memory, and the most active part of the page table is stored in the TLB (ie, the TLB page table).

When the CPU executes the instruction, the virtual address to be accessed is calculated by the AGU 111, and the virtual address is sent into the TLB to query the corresponding physical address. If the physical address is queried in the TLB, the memory access request is generated according to the physical address. A memory access request is issued to the MMU 112. If the corresponding physical address is not found in the TLB, the CPU 110 needs to find the physical address corresponding to the virtual address in the physical memory 130, and add the found mapping relationship to the TLB page table. Embodiment 1

The embodiment of the invention provides a memory management method, which is applicable to the memory management system shown in FIG. 1, and the method can be executed by a CPU. As shown in Figure 2, the method includes:

Step 101: When physical memory needs to be allocated for the process, the first physical page allocated to the process is determined from the free physical page.

In the implementation, when the process starts, the operating system needs to allocate physical memory for the process; or, after the process starts, the process requests physical memory from the operating system as needed. At this time, the operating system also needs to allocate physical memory for the process.

Step 102: When the determined first physical page is at least two, and the first physical page having the physical page number discontinuous exists in the determined first physical page, the adjustment instruction is sent to the memory manager. The adjustment instruction is used to instruct the memory manager to exchange at least one pair of second physical pages in the physical memory, each pair of second physical pages including one of the first physical pages whose physical page numbers are discontinuous and one non-idle The physical page is such that the first physical page obtained after the exchange is continuous with at least one other first physical page.

The memory manager may be the memory controller in FIG. 1 or a router in an on-chip network.

Step 103: Add an entry in the TLB page table of the process, where the entry records the mapping relationship between the at least two consecutive first physical pages and the virtual page of the process after being merged into one large physical page.

The large physical page includes the first physical page obtained after the exchange.

Understandably, the page table of the process in the physical memory is updated before an entry is added to the TLB page table of the process.

In the embodiment of the present invention, the first physical page allocated to the process is first determined, and then the first physical page whose physical page number is discontinuous is exchanged, so that the first physical page obtained after the exchange is continuous with another physical page. In this way, at least two consecutive first physical pages can be merged into one large physical page, and added as an entry to the TLB page table of the process, thereby reducing the TLB entry used by the process in address mapping. The number, in turn, reduces the TLB page fault overhead. In addition, the embodiment of the present invention has few changes to the operating system and is easy to popularize and apply. Embodiment 2

The embodiment of the invention provides a memory management method, which is applicable to the memory management system shown in FIG. This method can be performed by a memory controller. As shown in Figure 3, the method includes:

Step 201: Receive an adjustment instruction.

The adjustment instruction is used to instruct the memory manager to exchange at least one pair of second physical pages in the physical memory, each pair of second physical pages including one of the first physical pages whose physical page numbers are discontinuous and one non-idle physical Page, the first physical page is the free physical page to be assigned to the process.

Step 202: Exchange physical pages in the physical memory according to the adjustment instruction, so that the first physical page obtained after the exchange is continuous with at least another first physical page.

In the embodiment of the present invention, the first physical page allocated to the process is first determined, and then the first physical page whose physical page number is discontinuous is exchanged, so that the first physical page obtained after the exchange is continuous with another physical page. In this way, at least two consecutive first physical pages can be merged into one large physical page, and added as an entry to the TLB page table of the process, thereby reducing the process when the address mapping is performed. The number of TLB entries used, which in turn reduces the TLB page fault overhead. Embodiment 3

The embodiment of the invention provides a memory management method, which is applicable to the memory management system shown in FIG. In this embodiment, the memory manager is a storage controller, and the operating system divides the physical address space of the main memory into a plurality of physical pages, and assigns a physical page number to each physical page, and the storage controller is each physical page. An internal page number is allocated, and the storage controller is used to access the physical memory according to the internal page number, and the physical page number corresponds to the internal page number. Referring to Figure 4, the method includes:

Step Mount 301: When the system is initialized, the CPU divides the physical page and the virtual page.

Specifically, when the system is initialized, the operating system divides the physical address space of the entire physical memory into a plurality of consecutive physical pages, assigns a physical page number to each physical page, and divides the entire virtual address space that the program will use into Multiple consecutive virtual pages, each virtual page is assigned a virtual page number.

The physical page number is visible to the operating system, and the virtual page number is visible to the program. The physical page numbers of different physical pages vary.

Specifically, the operating system can divide the physical address space of the entire physical memory into a plurality of consecutive physical pages according to the same page size, for example, 4 KB, that is, the size of each physical page is the same, which is convenient for maintenance and management. Virtual pages are divided by the same page size as physical pages. As can be appreciated, the size of the physical page can also be different.

During the operation of the operating system, the physical page number of each physical page is fixed.

Step 302: The CPU sends a reset instruction to the storage controller, where the reset command is used to instruct the storage controller to establish a mapping relationship between the physical page number and the internal page number.

For example, the reset instruction may be a page_reset instruction, and when the memory controller receives the instruction, a mapping relationship between the physical page number and the internal page number is established.

An internal page number can be assigned to each physical page by step 302, and the internal page number is visible to the storage controller. The internal page numbers of different physical pages vary. At this point, each physical page has a physical page number and an internal page number.

Step 303: When it is necessary to allocate physical memory for the process, the CPU determines the size of the physical memory to be allocated to the process.

Generally, when the process starts, the operating system determines the size of the physical memory required by the process according to the information in the process's mirror (binary file); or the process requests the virtual memory space from the operating system during the process running. The system will determine the size of the virtual memory space requested by the process. The size of the physical memory that needs to be allocated to the process.

Step 304: The CPU scans the free physical page.

A free physical page is an unallocated physical page. In the CPU, a physical page table is usually saved to record the allocation of physical pages in physical memory. When implemented, the free physical page can be determined.

Step 305: The CPU determines, according to the determined size of the physical memory, the first physical page to be allocated to the process from the free physical page.

Through steps 302~305, when the physical memory needs to be allocated for the process, the first physical page allocated to the process is determined from the free physical page.

Step 306: When the first physical page is determined to be at least two, and the first physical page whose physical page number is discontinuous exists in the determined first physical page, the CPU sends an adjustment instruction to the storage controller.

The adjustment instruction is used to instruct the storage controller to perform at least one pair of second physical pages in the physical memory, and each pair of second physical pages includes one of the first physical pages whose physical page numbers are discontinuous and one non-idle physical The page is such that the first physical page obtained after the exchange is continuous with at least the other first physical page.

In this embodiment, the adjustment instruction carries a first physical page number and a second physical page number, where the storage instruction is used to instruct the storage controller to exchange the internal page number corresponding to the first physical page number and the second physical page number. Internal page number.

Specifically, the adjustment instruction may be a page_swap ( fnl , pfn2 ) instruction, where pfn1 is used to indicate a first physical page number (for example, may be a physical page number of a first physical page in the second physical page), and pfn2 is used to indicate The second physical page number (eg, may be the physical page number of a non-idle physical page in the second physical page).

When implemented, each adjustment instruction may include one or more pairs of physical page numbers of the second physical page (ie, including a plurality of first physical page numbers and a plurality of second physical page numbers), when an adjustment instruction includes multiple For the physical page number of the second physical page, for example, the physical page number of the plurality of pairs of the second physical page may be separated by a semicolon.

The first physical page whose physical page number is not continuous may be discontinuous with the physical page number of the first physical page that is smaller than the physical page number of the current first physical page, or may be compared with the current physical page number of the first physical page. The physical page number of the physical page number of the first physical page is not continuous, and may be a physical medium that is larger than the physical page number of the first physical page and smaller than the physical page number of the current first physical page. The page numbers are not continuous. Specifically, which first physical pages are adjusted, the adjustment strategy can be configured according to actual needs. There is no limit to the comparison.

Step 307: The storage controller executes an adjustment instruction.

In this embodiment, as described above, the storage controller is provided with a mapping table of physical page numbers and internal page numbers. When the storage controller receives the page_swap (pfnl, pfn2) instruction, it is about to be in the mapping table. The internal page number corresponding to the physical page number is modified to the internal page number corresponding to the second physical page number, and the internal page number corresponding to the second physical page number is modified to the internal page number corresponding to the first physical page number. After modification, The physical page corresponding to the first physical page number becomes a non-idle physical page, and the physical page corresponding to the second physical page number is the first physical page obtained after the exchange.

After performing this step 307, the effect seen by the operating system is to exchange data of two physical pages.

Optionally, when the storage controller executes the adjustment instruction, the storage controller may further send a response message to the CPU, where the response message is used to indicate whether the adjustment instruction is successfully executed.

Step 308: The CPU adds an entry in the TLB page table of the process, and the added entry records the mapping of at least two consecutive first physical pages into a large physical page and the virtual page of the process. relationship.

It will be readily appreciated that prior to step 308, the method further includes updating the page table of the process in the main memory. Each virtual page of the corresponding process in the page table of the process has an entry, and the content of the entry includes the address (physical page number) of the main memory page where the virtual page is located, and the effective indication of whether the virtual page is loaded into the main memory. Bit. In this embodiment, the entry may also include the size of the page.

It should be noted that, in practical applications, for a plurality of consecutive first physical pages, the CPU may add it as an entry to the TLB page table, or may divide the consecutive multiple first physical pages into multiple The entry is added to the TLB page table of the process. For example, for 10 consecutive first physical pages, the CPU can splicing 10 first physical pages into one large physical page, and then adding it as an entry to the TLB. In the page table, it is also possible to splicing 10 first physical pages into two large physical pages (for example, two large physical pages include five physical pages, or two large physical pages, one including four physical pages, One includes 6 physical pages). That is to say, the number of the large physical pages can be set according to actual needs, and the present invention is not limited thereto as long as the condition including at least two consecutive first physical pages is satisfied.

The foregoing steps 305-308 are exemplified below. The physical page numbers of the three physical pages are Page_A, Page_B, and Page_C, respectively, and their corresponding internal page numbers are Page_0, Page_l, and Page_2, respectively, Page_A, Page_B, and Page_C. After scanning the free physical page, the physical page corresponding to Page_A and Page_C is obtained as a free physical page, and the physical page corresponding to Page_B is occupied by other processes. At this time, it is determined that the physical page corresponding to Page_A and Page_C is assigned to the process. (ie as the first physical page).

According to the existing memory allocation method, the physical pages corresponding to Page_A and Page_C need to be mapped separately by using two TLB entries, and in this embodiment, the physical page numbers of the two first physical pages (Page_A and Page_C) Is not continuous, in this case, the CPU sends a page_swap (Page_B, Page_C) instruction to the storage controller. After receiving the instruction, the storage controller modifies the corresponding table of the physical page number and the internal page number stored therein. Page_B is modified to correspond to Page2, and Page_C '爹 is changed to correspond to pagel. Since the physical page number corresponding to the physical page is fixed, the operation is actually equivalent to two physical pages (the physical corresponding to Page_B and Page_C). The corresponding internal page number of the page has been changed, so that the physical page numbers corresponding to the two first physical pages become continuous. The two physical pages consecutive to the two physical page numbers are merged into one large physical page and added to the TLB entry. That is to say, the situation that the two TLB entries need to be mapped is implemented by using only one TLB entry, and the large physical page includes the physical page corresponding to Page_A and the physical corresponding to Page_B obtained after the exchange. The page, that is, the large physical page corresponds to the two virtual pages of the process.

Step 309: The CPU sends a memory access request to the storage controller, where the memory access request includes a process number, a starting physical address, and a length information.

It is easy to know that the fetch request usually also includes the type of operation, such as read operation, write operation.

In the implementation, when the process needs to access the virtual memory, the CPU generates the virtual address to be accessed, the high address of the virtual address is the logical page number, and the low bit is the offset within the page; then, the CPU converts the virtual address into a physical address, and converts The process is as follows: First, according to the page table, the physical page number corresponding to the logical page number is found, and the physical page number is used as the high field of the physical address, and the offset is integrated with the page of the virtual address to form a complete physical address. After the CPU obtains the complete physical address, it generates a memory access request based on the physical address, and sends the generated memory access request to the storage controller.

Step 310: The storage controller converts the starting physical address in the fetch request into an internal address. As described above, the upper bits of the physical address are physical page numbers, and the lower bits are offsets within the page; specifically, the step 310 may include:

The storage controller determines the physical page number according to the starting physical address;

Then, the internal page number corresponding to the starting physical page number is determined according to the mapping table of the physical page number and the internal page number;

The internal page number is spliced with the offset within the page to obtain the internal address corresponding to the starting physical address. In implementation, the step 310 can be completed when the memory access request is in the queue of the storage controller, and therefore, the access efficiency of the physical memory is not affected.

Step 311: The storage controller accesses the physical memory according to the obtained internal address.

After the storage controller accesses the physical memory, the data corresponding to the internal address is transferred into the cache (Cache).

It should be noted that, in this embodiment, the mapping table of the physical page number and the internal page number is stored in the storage controller, and the storage controller executes the reset instruction, the adjustment instruction, and the conversion of the physical address and the internal address, in other implementations. In an example, the method of the present invention can also be applied to, for example, a network-on-chip (NoC). In NoC, a mapping table of physical page numbers and internal page numbers can be stored in an on-chip router. The router performs a reset instruction, an adjustment instruction, and a conversion of a physical address and an internal address.

In the embodiment of the present invention, the first physical page allocated to the process is first determined, and then the first physical page whose physical page number is discontinuous is exchanged, so that the first physical page obtained after the exchange is continuous with another physical page. In this way, at least two consecutive first physical pages can be merged into one large physical page, and added as an entry to the TLB page table of the process. Since the page size corresponding to the entry becomes larger, the process can be reduced. The number of TLB entries used in the address mapping reduces the TLB page fault overhead. The page size corresponding to the TLB entry is adjusted in real time according to the actual situation. Compared with the existing large page technology, Reduce page fault overhead more effectively. In addition, in the embodiment of the present invention, by configuring a physical page number and an internal page number for a physical page, and setting a mapping table of a physical page number and a physical page number in the storage controller, the first physical page that is not continuous with the physical page number is performed. When adjusting, it is only necessary to modify the mapping relationship in the mapping table, and there is no need to perform data transmission inside the storage controller, so the system delay is small. In addition, the embodiment of the present invention has few changes to the operating system, and is easy to popularize and apply. Embodiment 4

The embodiment of the invention provides a memory management method, which is applicable to the memory management system shown in FIG. In this embodiment, the memory manager is a storage controller, and the operating system divides the physical address space of the main memory into a plurality of physical pages, and allocates a physical page number for each physical page, and the storage controller is based on the physical page number. Access physical memory. Referring to Figure 5, the method includes:

Step Mount 401: When the system is initialized, the CPU divides the physical page and the virtual page.

This step 401 is the same as the aforementioned step 301, and a detailed description is omitted here.

Step 402: When it is necessary to allocate physical memory for the process, the CPU determines the score from the free physical page. The first physical page of the provisioning process.

The implementation process of the step 402 is the same as the foregoing steps 302-305, and details are not described herein again.

Step 403: When the first physical page is determined to be at least two, and the first physical page whose physical page number is discontinuous exists in the determined first physical page, the CPU sends an adjustment instruction to the storage controller.

The adjustment instruction is used to instruct the storage controller to perform at least one pair of second physical pages in the physical memory, and each pair of second physical pages includes one of the first physical pages whose physical page numbers are discontinuous and one non-idle The physical page is such that the first physical page obtained after the exchange is continuous with at least the other first physical page.

In this embodiment, the adjustment instruction carries a first physical page number and a second physical page number, where the storage instruction is used to instruct the storage controller to exchange data and a second physical page in a physical page corresponding to the first physical page number. The data in the physical page corresponding to the number.

Step 404: The storage controller executes an adjustment instruction.

Specifically, in implementation, the physical page corresponding to the first physical page number is the first physical page, and the physical page of the second physical page number is the non-idle physical page, because the first physical page is a free physical page. Therefore, the storage controller can complete the adjustment instruction by transmitting the data of the physical page corresponding to the second physical page number to the physical page corresponding to the first physical page number. After the exchange, the physical page corresponding to the first physical page number becomes a non-idle physical page, and the physical page corresponding to the second physical page number is an idle physical page, that is, the first physical page obtained after the exchange.

Step 405: The CPU adds an entry in the TLB page table of the process, where the added entry records the mapping of at least two consecutive first physical pages into a large physical page and the virtual page of the process. relationship.

It will be readily appreciated that prior to step 405, the method further includes updating the page table of the process in the main memory. Step 406: The CPU sends a memory access request to the storage controller, where the memory access request includes a process number, a starting physical address, and a length information.

This step 406 is the same as the foregoing step 309, and details are not described herein again.

Step 407: The storage controller accesses the physical memory according to the starting physical address and length information in the memory access request.

In the embodiment of the present invention, the first physical page allocated to the process is first determined, and then the first physical page whose physical page number is discontinuous is exchanged, so that the first physical page obtained after the exchange is combined with another object. The page is continuous, so that at least two consecutive first physical pages can be merged into one large physical page, which is added as an entry to the TLB page table of the process, because the page size corresponding to the entry becomes larger, so The number of TLB entries used by the process in the address mapping can be reduced, and the page loss overhead of the TLB entry is reduced. The page size corresponding to the TLB entry is adjusted in real time according to the actual situation, and the existing large page technology. In comparison, it is therefore possible to reduce page fault overhead more effectively. In addition, the embodiment of the present invention has few changes to the operating system, and is easy to popularize and apply. Embodiment 5

The embodiment of the present invention provides a memory management apparatus, which can be used to implement the method provided in Embodiment 1. As shown in FIG. 6, the apparatus includes: a memory allocation module 501, a sending module 502, and an entry processing module 503.

The memory allocation module 501 is configured to determine, when the physical memory needs to be allocated for the process, the first physical page allocated to the process from the free physical page.

The sending module 502 is configured to: when the first physical page determined by the memory allocating module 501 is at least two, and the first physical page that is determined to have a discontinuous physical page number in the first physical page, send to the memory manager And an adjustment instruction, the adjustment instruction is used to instruct the memory manager to exchange at least one pair of second physical pages in the physical memory, where each pair of second physical pages includes one and one of the first physical pages whose physical page numbers are discontinuous a non-idle physical page such that the first physical page obtained after the exchange is contiguous with at least one other of the first physical pages;

The entry processing module 503 is configured to add an entry in the TLB page table of the process, where the entry records the mapping relationship between the at least two consecutive first physical pages and the virtual page of the process after being merged into one large physical page. The large physical page includes the first physical page obtained after the exchange.

In the embodiment of the present invention, the first physical page allocated to the process is first determined, and then the first physical page whose physical page number is discontinuous is exchanged, so that the first physical page obtained after the exchange is continuous with another physical page. In this way, at least two consecutive first physical pages can be merged into one large physical page, and added as an entry to the TLB page table of the process, thereby reducing the TLB entry used by the process in address mapping. The number, in turn, reduces the TLB page fault overhead. In addition, the embodiment of the present invention has few changes to the operating system and is easy to popularize and apply. Embodiment 6

The embodiment of the invention provides a memory management device, which can be used to implement the third or fourth embodiment. The steps performed by the CPU. As shown in Figure 7, the device includes:

The memory allocation module 601, the sending module 602, and the entry processing module 603.

The memory allocation module 601 is configured to determine, when the physical memory needs to be allocated for the process, the first physical page allocated to the process from the free physical page.

The sending module 602 is configured to send, when the first physical page determined by the memory allocation module 601 is at least two, and the first physical page in the first physical page that is determined to be discontinuous, to the memory manager And an adjustment instruction, the adjustment instruction is used to instruct the memory manager to exchange at least one pair of second physical pages in the physical memory, where each pair of second physical pages includes one and one of the first physical pages whose physical page numbers are discontinuous a non-idle physical page such that the first physical page obtained after the exchange is contiguous with at least one other of the first physical pages;

The entry processing module 603 is configured to add an entry in the TLB page table of the process, where the entry records the mapping relationship between the at least two consecutive first physical pages and the virtual page of the process after being merged into one large physical page. The large physical page includes the first physical page obtained after the exchange.

In a first implementation manner of the embodiment of the present invention, the memory manager is provided with a mapping table of a physical page number and an internal page number, where the adjustment instruction carries the first physical page number and the second physical page number, and the storage instruction is used to indicate The memory manager exchanges the internal page number corresponding to the first physical page number and the second physical page number. The memory manager is configured to access the physical memory according to the internal page number. For the implementation, refer to the second embodiment, and detailed description is omitted here.

In the first implementation, the sending module 602 is further configured to send a reset instruction to the memory manager, the reset instruction is used to instruct the memory manager to create a mapping table of the physical page number and the internal page number.

In this first implementation, the memory manager can be a memory controller or a router for an on-chip network.

In a second implementation manner of the embodiment of the present invention, the adjustment instruction carries a first physical page number and a second physical page number, where the adjustment instruction is used to instruct the memory manager to exchange data in the physical page corresponding to the first physical page number and The data in the physical page corresponding to the second physical page number (for the implementation, refer to the third embodiment, and the detailed description is omitted here).

In this second implementation, the memory manager can be a memory controller.

In the embodiment of the present invention, the first physical page allocated to the process is first determined, and then the first physical page whose physical page number is discontinuous is exchanged, so that the first physical page obtained after the exchange is continuous with another physical page. In this way, at least two consecutive first physical pages can be merged into one large physical page, and added as an entry to the TLB page table of the process, thereby reducing the process when the address mapping is performed. The number of TLB entries used, which in turn reduces the TLB page fault overhead. In addition, the embodiment of the present invention has few changes to the operating system, and is easy to popularize and apply. Example 7

The embodiment of the present invention provides a memory management apparatus, which can be used to implement the method provided in Embodiment 2. As shown in FIG. 8, the apparatus includes: a receiving module 701 and an executing module 702.

The receiving module 701 is configured to receive an adjustment instruction, where the adjustment instruction is used to instruct the memory manager to perform exchange processing on at least one pair of second physical pages in the physical memory, where each pair of second physical pages includes a physical page number discontinuous One of the first physical pages and one non-idle physical page, the first physical page being the free physical page to be assigned to the process.

The executing module 702 is configured to exchange physical pages in the physical memory according to the adjustment instruction received by the receiving module 701, so that the first physical page obtained after the exchange is continuous with at least another first physical page.

In the embodiment of the present invention, the first physical page allocated to the process is first determined, and then the first physical page whose physical page number is discontinuous is exchanged, so that the first physical page obtained after the exchange is continuous with another physical page. In this way, at least two consecutive first physical pages can be merged into one large physical page, and added as an entry to the TLB page table of the process, thereby reducing the TLB entry used by the process in address mapping. The number, in turn, reduces the TLB page fault overhead. In addition, the embodiment of the present invention has few changes to the operating system and is easy to popularize and apply. Example eight

The embodiment of the invention provides a memory management device, which can be used to implement the steps performed by the memory controller in the third or fourth embodiment. Referring to Figure 9, the apparatus includes: a receiving module 801 and an executing module 802.

The receiving module 801 is configured to receive an adjustment instruction, where the adjustment instruction is used to instruct the memory manager to perform exchange processing on at least one pair of second physical pages in the physical memory, where each pair of second physical pages includes a physical page number discontinuous One of the first physical pages and one non-idle physical page, the first physical page being the free physical page to be assigned to the process.

The executing module 802 is configured to exchange physical pages in the physical memory according to the adjustment instruction received by the receiving module 801, so that the first physical page obtained after the exchange is continuous with at least another first physical page.

In a first implementation manner of the embodiment of the present invention, a physical page number and an internal part are provided in the memory manager. a mapping table of the page number, the adjustment instruction carries a first physical page number and a second physical page number, the adjustment instruction is used to instruct the memory manager to exchange the first physical page number and the internal page number corresponding to the second physical page number The memory manager is used to access physical memory based on the internal page number.

In the first implementation, the receiving module 801 is further configured to receive a reset instruction, where the reset instruction is used to instruct the memory manager to create a mapping table of the physical page number and an internal page number; It can also be used to create a mapping table of physical page numbers and internal page numbers according to the reset instruction.

In this first implementation, the memory manager may be a memory controller or a router of an on-chip network (for the implementation, refer to Embodiment 4, and detailed description is omitted here).

Further, in the first implementation manner, the apparatus may further include: an address conversion module 803 and a memory access module 804.

At this time, the receiving module 801 is further configured to receive a memory access instruction, where the memory access instruction includes a starting physical address and length information. The address conversion module 803 is configured to convert the starting physical address in the fetch instruction into an internal address according to the mapping table of the physical page number and the internal page number. The memory access module 804 is configured to access the physical memory according to the internal address obtained by the address translation module 803.

In a second implementation manner of the embodiment of the present invention, the adjustment instruction carries a first physical page number and a second physical page number, where the adjustment instruction is used to instruct the memory manager to exchange data in the physical page corresponding to the first physical page number and The data in the physical page corresponding to the second physical page number (for the implementation, refer to Embodiment 4, and detailed description is omitted here).

In this second implementation, the memory manager can be a memory controller.

In the embodiment of the present invention, the first physical page allocated to the process is first determined, and then the first physical page whose physical page number is discontinuous is exchanged, so that the first physical page obtained after the exchange is continuous with another physical page. In this way, at least two consecutive first physical pages can be merged into one large physical page, and added as an entry to the TLB page table of the process, thereby reducing the TLB entry used by the process in address mapping. The number, in turn, reduces the TLB page fault overhead. In addition, the embodiment of the present invention has few changes to the operating system and is easy to popularize and apply. Example nine

An embodiment of the present invention provides a memory management apparatus. Referring to FIG. 10, the apparatus includes a processor 1001, a memory 1002, a bus 1003, and a communication interface 1004. The memory 1002 is configured to store computer execution instructions, and the processor 1001 is connected to the memory 1002 via the bus 1003. When the computer is running, the processor 1001 executes the computer-executed instructions stored in the memory 1002 to cause the computer to execute the method executed by the CPU in the first embodiment or the third embodiment or the fourth embodiment.

In the embodiment of the present invention, the first physical page allocated to the process is first determined, and then the first physical page whose physical page number is discontinuous is exchanged, so that the first physical page obtained after the exchange is continuous with another physical page. In this way, at least two consecutive first physical pages can be merged into one large physical page, and added as an entry to the TLB page table of the process, thereby reducing the TLB entry used by the process in address mapping. The number, in turn, reduces the TLB page fault overhead. In addition, the embodiment of the present invention has few changes to the operating system and is easy to popularize and apply. Example ten

The embodiment of the present invention provides a memory management apparatus. Referring to FIG. 11, the apparatus includes a processor 1101, a memory 1102, a bus 1103, and a communication interface 1104. The memory 1102 is used to store computer execution instructions, and the processor 1101 is connected to the memory 1102 via a bus 1103. When the computer is running, the processor 1101 executes the computer execution instructions stored in the memory 1102 to cause the computer to execute the implementation. The method performed by the memory controller in the second embodiment or the third embodiment or the fourth embodiment.

In the embodiment of the present invention, the first physical page allocated to the process is first determined, and then the first physical page whose physical page number is discontinuous is exchanged, so that the first physical page obtained after the exchange is continuous with another physical page. In this way, at least two consecutive first physical pages can be merged into one large physical page, and added as an entry to the TLB page table of the process, thereby reducing the TLB entry used by the process in address mapping. The number, in turn, reduces the TLB page fault overhead. In addition, the embodiment of the present invention has few changes to the operating system and is easy to popularize and apply. Embodiment 11

The embodiment of the present invention provides a memory management system. Referring to FIG. 12, the system includes: a CPU 1201 and a memory controller 1202;

The CPU 1201 includes the memory management device provided in Embodiment 5, 6 or 9;

The memory controller 1202 includes the memory management device provided in the seventh, eighth or tenth embodiment.

In the embodiment of the present invention, the first physical page allocated to the process is first determined, and then the first physical page whose physical page number is discontinuous is exchanged, so that the first physical page obtained after the exchange is continuous with another physical page. In this way, at least two consecutive first physical pages can be merged into one large physical page. As an entry, it is added to the TLB page table of the process, which can reduce the number of TLB entries used by the process in address mapping, and thus reduce the TLB page fault overhead. In addition, the embodiment of the present invention has few changes to the operating system, and is easy to popularize and apply. Example twelve

The embodiment of the present invention provides an on-chip network. Referring to FIG. 13, the on-chip network includes: a plurality of processors 1301, a plurality of routers 1302, and a plurality of memory controllers 1303. The processor 1301 is connected to the memory controller 1303 through the router 1302. ;

The processor 1301 includes the memory management device provided in Embodiment 5, 6 or 9. The router 1302 includes the memory management device provided in Embodiment 7, 8, or 10.

In the embodiment of the present invention, the first physical page allocated to the process is first determined, and then the first physical page whose physical page number is discontinuous is exchanged, so that the first physical page obtained after the exchange is continuous with another physical page. In this way, at least two consecutive first physical pages can be merged into one large physical page, and added as an entry to the TLB page table of the process, thereby reducing the TLB entry used by the process in address mapping. The number, in turn, reduces the TLB page fault overhead. In addition, the embodiment of the present invention has few changes to the operating system and is easy to popularize and apply. It should be noted that, when the memory management device provided by the foregoing embodiment performs memory management, only the division of each functional module described above is used as an example. In actual applications, the function distribution may be completed by different functional modules as needed. The internal structure of the device is divided into different functional modules to perform all or part of the functions described above. In addition, the memory management device and the memory management method embodiment provided in the foregoing embodiments are in the same concept, and the specific implementation process is described in detail in the method embodiment, and details are not described herein again. The serial numbers of the embodiments of the present invention are merely for the description, and do not represent the advantages and disadvantages of the embodiments.

A person skilled in the art may understand that all or part of the steps of implementing the above embodiments may be completed by hardware, or may be instructed by a program to execute related hardware, and the program may be stored in a computer readable storage medium. The storage medium mentioned may be a read only memory, a magnetic disk or an optical disk or the like.

The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., which are included in the spirit and scope of the present invention, should be included in the present invention. Within the scope of protection.

Claims

Claim

A memory allocation method, the method comprising:

When physical memory needs to be allocated for a process, the first physical page allocated to the process is determined from the free physical page;

Sending an adjustment instruction to the memory manager when the first physical page is determined to be at least two, and the first physical page whose physical page number is discontinuous exists in the determined at least two first physical pages, The adjustment instruction is configured to instruct the memory manager to perform an exchange process on at least one pair of second physical pages in the physical memory, where each pair of the second physical pages includes the first physical body whose physical page number is discontinuous One of the pages and one non-idle physical page, such that the first physical page obtained after the exchange is continuous with at least one of the other first physical pages;

The method according to claim 1, wherein the memory manager is provided with a mapping table of physical page numbers and internal page numbers, and the adjustment instruction carries a first physical page number and a second physical page number. The storage instruction is configured to instruct the memory manager to exchange an internal page number corresponding to the first physical page number and the second physical page number, where the memory manager is configured to access the internal page number according to the Physical memory.

The method according to claim 2, wherein the method further comprises: sending a reset instruction to the memory manager, the reset instruction being used to instruct the memory manager to create the physical page number and A mapping table of internal page numbers.

The method according to claim 1, wherein the adjustment instruction carries a first physical page number and a second physical page number, and the adjustment instruction is used to instruct the memory manager to exchange the first physical The data in the physical page corresponding to the page number and the data in the physical page corresponding to the second physical page number.

5. A memory management method, the method comprising:

The memory manager receives an adjustment instruction, the adjustment instruction is used to instruct the memory manager to Exchanging at least one pair of second physical pages in the physical memory, each pair of the second physical pages including one of the first physical pages whose physical page numbers are discontinuous and one non-idle physical page, the A physical page is an idle physical page to be assigned to a process;

The method according to claim 5, wherein the memory manager is provided with a mapping table of a physical page number and an internal page number, and the adjustment instruction carries a first physical page number and a second physical page number. The adjustment instruction is configured to instruct the memory manager to exchange an internal page number corresponding to the first physical page number and the second physical page number, where the memory manager is configured to access the internal page number according to the Physical memory.

The method according to claim 6, wherein the method further comprises:

Receiving a reset instruction, the reset instruction is used to instruct the memory manager to create a mapping table of the physical page number and an internal page number;

The method according to claim 6, wherein the method further comprises:

The physical memory is accessed according to the internal address.

The method according to claim 5, wherein the adjustment instruction carries a first physical page number and a second physical page number, the adjustment instruction is used to instruct the memory manager to exchange the first physical The data in the physical page corresponding to the page number and the data in the physical page corresponding to the second physical page number.

10. A memory management device, the device comprising:

a memory allocation module, configured to determine, from an idle physical page, a first physical page allocated to the process when physical memory needs to be allocated for the process;

a sending module, configured to: when the first physical page determined by the memory allocation module is at least two, And determining, in the first physical page that the first physical page has a physical page number that is not continuous, sending an adjustment instruction to the memory manager, where the adjustment instruction is used to indicate that the memory manager is in the physical memory At least one pair of second physical pages are exchanged, and each pair of the second physical pages includes one of the first physical pages whose physical page numbers are discontinuous and one non-idle physical page, so that the first obtained after the exchange One physical page is continuous with at least one other of the first physical pages;

The apparatus according to claim 10, wherein the memory manager is provided with a mapping table of a physical page number and an internal page number, and the adjustment instruction carries the first physical page number and the second physical page number. The storage instruction is configured to instruct the memory manager to exchange an internal page number corresponding to the first physical page number and the second physical page number, where the memory manager is configured to access the internal page number according to the Physical memory.

The device according to claim 11, wherein the sending module is further configured to send a reset instruction to the memory manager, where the reset instruction is used to instruct the memory manager to create the physical page A mapping table of numbers and internal page numbers.

The apparatus according to claim 10, wherein the adjustment instruction carries a first physical page number and a second physical page number, the adjustment instruction is used to instruct the memory manager to exchange the first physical The data in the physical page corresponding to the page number and the data in the physical page corresponding to the second physical page number.

14. A memory management device, the device comprising:

a receiving module, configured to receive an adjustment instruction, where the adjustment instruction is used to instruct the memory manager to perform an exchange process on at least one pair of second physical pages in the physical memory, where each pair of the second physical page includes the One of the first physical pages whose physical page numbers are not consecutive and one non-idle physical page, the first physical page being an idle physical page to be allocated to the process;

An execution module, configured to exchange physical pages in the physical memory according to the adjustment instruction received by the receiving module, so that the first physical page obtained after the exchange and the at least another first Physical pages are contiguous.

The apparatus according to claim 14, wherein the memory manager is provided with a mapping table of a physical page number and an internal page number, and the adjustment instruction carries the first physical page number and the second physical page number. The adjustment instruction is configured to instruct the memory manager to exchange an internal page number corresponding to the first physical page number and the second physical page number, where the memory manager is configured to access the internal page number according to the Physical memory.

The device according to claim 15, wherein the receiving module is further configured to receive a reset instruction, where the reset instruction is used to instruct the memory manager to create the physical page number and an internal page number. Mapping table

The execution module is further configured to create a mapping table of the physical page number and the internal page number according to the reset instruction.

The device according to claim 15, wherein the receiving module is further configured to: receive a memory access instruction, where the memory access instruction includes a starting physical address and length information;

The device also includes:

The apparatus according to claim 14, wherein the adjustment instruction carries a first physical page number and a second physical page number, and the adjustment instruction is used to instruct the memory manager to exchange the first physical The data in the physical page corresponding to the page number and the data in the physical page corresponding to the second physical page number.

A memory management device, the device comprising: a processor, a memory, a bus, and a communication interface; the memory is configured to store a computer execution instruction, and the processor is connected to the memory through the bus The processor executes the computer-executed instructions stored in the memory to cause the computer to perform the method of any one of claims 1 to 4.

20. A memory management device, the device comprising: the device comprising: a processor, a memory, a bus, and a communication interface; the memory is configured to store a computer execution instruction, the processor and the memory Through the bus connection, the processor executes the computer-executed instructions stored in the memory to cause the computer to perform the method of any one of claims 5-9 when the computer is running.

21. A memory management system, the system comprising:

Central processor and memory controller;

The central processing unit includes the memory management device according to any one of claims 10-13 or claim 19;

The memory controller includes the memory management device of any one of claims 14-18 or 20.

22. An on-chip network, wherein the on-chip network includes:

a plurality of processors, a plurality of routers, and a plurality of memory controllers, wherein the processor is connected to the memory controller through the router;

The processor includes the memory management device according to any one of claims 10-13 or claim 19;

The router includes the memory management device of any one of claims 14-18 or 20.