CN102147760A - Processor co-verification platform based on network transmission and testing method of processor co-verification platform - Google Patents
Processor co-verification platform based on network transmission and testing method of processor co-verification platform Download PDFInfo
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Abstract
The invention discloses a processor co-verification platform based on network transmission and a testing method of the processor co-verification platform. The processor co-verification platform based on network transmission consists of a hardware implementation program, a software implementation program and a network communication between the hardware implementation program and the software implementation program, wherein the hardware implementation program comprises a test excitation, a hardware design model, a hardware simulation model and a work station on which a Linux operating system is installed; the software implementation program comprises a software simulator and a work station on which the Linux operating system is installed; the software simulator is used for simulating hardware and further verifies hardware design at the software level; the network communication between the hardware implementation program and the software implementation program realizes synchronism control and document transmission of the testing based on a TCP/IP (transmission control protocol/internet protocol) and is used for collaborative test on the two work stations. The processor co-verification platform can detailedly/accurately locate errors and differences and has high verification accuracy rate; and the verification is carried out in a network mode and is convenient, fast and easy.
Description
Technical field
The present invention relates to a kind of processor co-verification platform and method of testing thereof of transmission Network Based, belong to the functional verification and the evaluation and test technical field of processor.
Background technology
In the design cycle of processor, checking is very important and a take time and effort job.The checking of processor comprises two processes: functional verification and timing verification, functional verification has several methods such as simplation verification, formalization checking and FPGA prototype verification, wherein simplation verification is fundamental method, proof procedure uses the most extensive, plays important effect at the processor system Qualify Phase.In hardware RTL code compiling process, just need verify that what need system after hardware design is finished carries out correctness and the performance index thereof of functional verification with the check design to correctness and every performance index of logicality of design.
The logic function and the performance index of processor hardware design mainly depend on the code quality that the hardware design personnel utilize hardware description language to write.Follow the continuous rising of processor complexity, the complexity of processor checking work and workload present index and rise, and be also more and more higher with requirement to the dependence of checking.As the part of design process, the effect of checking play more and more key, the workload of checking also is relatively big, occupies about 70% of whole work design effort amount, the efficient of checking and reliability have often determined the success or failure of project.
Traditional function verification method is to utilize existing software simulator analog hardware design (see figure 1), the correctness of checking RTL code, promptly respectively with same test and excitation respectively in the middle operation that designs a model of software simulator and hardware (RTL level), the operation result that compares both then, and manually operation result is compared analysis by the tester, search wrong in the RTL code and make amendment, carry out simulation test after the modification more again.The thought of software emulation is, uses or the emulator that develops software when the processor design verification, and the function design of analog hardware aspect is verified and tested hardware design.Use or the emulator that develops software, the tester does not need to be concerned about the circuit design of bottom, only needs to be concerned about the correctness and the performance of the logic aspect of hardware design own, is suitable for the robotization of hardware design functional verification.
Utilize traditional function verification method, the right problem of checking personnel demand side has: (1) test and excitation is by manual compiling, and its function coverage of test and excitation of each manual compiling is not high, be difficult to satisfy the needs of functional verification, as traveling through all excitation input and possible combined situation thereof, reach and verify coverage rate completely, workload is very big, also is difficult to realize; (2) the checking flow process is to utilize software simulator operation result checking R TL code model operation result, from operation result, compare and analysis by the tester, but RTL code model operational process and software emulation process are very long, needs wait long time just can be seen the result and analyze, the wave file of RTL size of code and operation result is all bigger, obviously can not satisfy the demand of checking according to manual analysis, inspection; (3) going deep into along with test, general more common design mistake is investigated, but still have the mistake that a lot of people are difficult for discovering and fail to detect, this needs repeatedly, a large amount of test to be to traverse all situations, to guarantee that hardware design all produces reasonably output to any possible excitation input and combination thereof,, proving period is very long; (4) checking depends on software simulator, at software simulation is not to develop voluntarily or source code when open, can not extract or follow the tracks of the execution information of software simulator, be difficult to guarantee the accuracy and the correctness of software action, thereby be difficult to guarantee the correctness and the validity thereof of checking itself.In addition, also need the checking personnel, just can analyze wrong concrete reason RTL code and software emulation being familiar with very all, thereby, classic method waste time and energy and efficient not high, these all need the higher verification method of people's application efficiency.
Summary of the invention
Technical matters to be solved by this invention is: provide a kind of and can realize the robotization checking, improve the processor co-verification platform and the method for testing thereof of the transmission Network Based of testing reliability and accuracy and testing efficiency height, wide coverage.
Its technical scheme is:
A kind of processor co-verification platform of transmission Network Based is characterized in that: be made up of three parts of network service between hardware realization program, software realization program and hardware realization program and the software realization program; Hardware realization program comprises test and excitation, hardware design model, hardware simulation model and the workstation that (SuSE) Linux OS is installed; Test and excitation is combined to form according to certain constraint rule at random by assembly instruction, and the hardware design model generates with the Verilog hardware description language, and (Register Transfer Level RTL) carries out modeling in the register transfer level; The hardware simulation model carries out level verification just with C Plus Plus analog hardware design carrying out modeling to hardware design, and two models are abideed by identical design proposal, can have identical response to identical excitation; Software realization program comprises software simulator and the workstation that (SuSE) Linux OS is installed; Software is realized the parameter configuration test environment of program according to input, utilizes software simulator that hardware is simulated, in software levels hardware design is further verified; Hardware is realized the network service between program and the software realization program, adopts the synchronism control and the file transfer that realize test based on ICP/IP protocol, is used for working in coordination with test at above-mentioned two workstations.
A kind of processor co-verification platform test method of transmission Network Based, under the test environment of (SuSE) Linux OS workstation, its testing procedure is:
The first step: the test beginning, executive software realization program is imported two parameters respectively according to prompting: parameter 1 is provided with the number of rounds of tests that each test process verification platform is finished automatically, and parameter 2 is provided with the port numbers of communicating pair; And test environment is set according to parameter, set up three level files storing directory voluntarily to preserve all test file information;
Second step: carry out hardware and realize program, produce test and excitation, and generate corresponding memory mapped file (.img1).Test and excitation is formed according to certain constraint at random by assembly instruction, the constraint that reaches of assembly instruction is to extract with random fashion the constraint function storehouse by program from the instruction functions storehouse, the packing of orders form of test and excitation is made up according to constraint rule at random by instruction, and generates corresponding scale-of-two memory mapped file (.img1);
The 3rd step: software realizes that program encourages with TCP mode read test, compiling generates the excitation file (.out) that software simulator can load, and further generate memory mapped file (.img2) that hardware design/analogy model needs and compare with memory mapped file that hardware realization program generates, to guarantee that every what take turns hardware design/simulation and software emulation loading in the test is same test and excitation;
The 4th step: relatively hardware is realized the memory mapped file that program and software realization program generate respectively, all is that hardware design/simulation and software emulation load identical test and excitation to guarantee that each takes turns checking.When memory mapped file was more inconsistent, the comparative result file that journalises finished the epicycle test, and when comparative result was consistent, the operating software emulator produced simulation result;
The 5th step: hardware design/analogy model generates hardware design model result and hardware simulation model result respectively by read/load memory mapped file (.img2) in the TCP mode, and is kept under the Pretesting catalogue;
The 6th step: comparative analysis hardware design model result and hardware simulation model result, and with the analysis result file that journalises, this realizes that relatively hardware design model result and hardware simulation model verify mutually, with the correctness of checking RTL code;
The 7th step: output comparative analysis hardware design model running result and software emulation result, and with the analysis result file that journalises, this relatively realizes the correctness of software levels checking RTL code;
The 8th step: software is realized program inquiring, and each takes turns the testing differentia destination file, deposits with the textual form record
In the test file place of difference catalogue, deletion result correct catalogue and file, the statistics coverage rate, file and beginning test next time journalise the functional verification coverage rate after finishing each time.
Its technique effect: co-verification platform of the present invention and method of testing thereof, fully apply to the dsp chip BWDSP100 functional verification work of developing voluntarily, the checking result is presented at that coverage rate can reach 99.75% under the correct situation of functional verification result, can satisfy the needs of processor function verification fully.In proof procedure, do not need manual monitoring and intervention fully, reduced a large amount of proving times and checking workload, effectively improved the checking work efficiency.
1, test and excitation of the present invention is generated by program, test and excitation makes up at random according to constraint rule, test job can be finished automatically by unified co-verification platform, significantly reduced identifier person's workload, improved work efficiency, can be behind the process batch testing as far as possible near the function coverage of setting.
2, accuracy height of the present invention, the present invention verifies hardware design at hardware level and two levels of software levels respectively by hardware simulation model and software emulation, can comprehensive and accurately detect the mistake of hardware design RTL code.
3, the present invention verifies wide coverage, the test and excitation of this co-verification platform and method of testing thereof adopts random fashion to produce, support batch testing, can finish the very large test of data volume, can traverse the variety of way of the packing of orders in the hardware design, but system comprehensively realizes functional verification.
4, verification efficiency of the present invention is higher, collaborative verification platform is a complete software program, automatically carry out functional verification after the program run, the checking personnel only need check and verify program and generate the result, mistake according to the results modification hardware design, information is carried out in the inside that does not need to be concerned about hardware design/analogy model and software simulator, does not need to check the execution information of hardware operation wave file and software simulator, has reduced proving time and checking personnel's workload.
5, applied widely, the not only applicable processor function verification that is used for different demands of the present invention also is applicable to the rear end simulating, verifying, and the correctness detection of support software emulator operation result etc.
Description of drawings
Fig. 1 is traditional function verification method process flow diagram.
Fig. 2 is the structural drawing of verification platform of the present invention.
Fig. 3 is a test flow chart of the present invention.
Fig. 4 is a communication flow diagram.
The comparison of Fig. 5 test result file, analysis synoptic diagram.
Embodiment
As shown in Figure 2, a kind of processor co-verification platform of transmission Network Based is characterized in that: be made up of three parts of network service between hardware realization program, software realization program and hardware realization program and the software realization program.
Hardware realization program comprises test and excitation, hardware design model, hardware simulation model and the workstation that (SuSE) Linux OS is installed.Test and excitation is combined to form according to certain constraint rule at random by assembly instruction, the assembly instruction of processor is edited in advance in the instruction functions storehouse, constraint rule utilizes hardware description language that it is compiled the universal constraining function library, and its constraint of different hardware modules is also inequality.For example, the checking instruction type of shift unit and multiplier and array mode are promptly inequality.The method that produces excitation is, behind each test starting, hardware realization program is randomly drawed instruction and constraint from function library, and with random fashion generation test and excitation, as the test and excitation of hardware design/analogy model and software simulator, assembly instruction and array configuration thereof that each test and excitation the inside comprises all are not quite similar because of randomness.The hardware design model generates with the Verilog hardware description language, at register transfer level (Register Transfer Level, RTL) carry out modeling, Verilog is that a kind of hardware description language is similar with the C language syntax, hardware design can be described on very abstract level, this description can be converted to the circuit under any manufacturing process, for example, the designer can do the description of register transfer level (RTL) to design under the situation of not considering concrete manufacturing process; The register transfer level is to utilize a kind of abstraction hierarchy of Verilog language description hardware physical circuit.The hardware simulation model carries out modeling with the design of C Plus Plus analog hardware.Two models are abideed by identical design proposal, can have identical response to identical excitation, if response is different, then must have one to make mistakes, and carry out level verification just with this correctness to hardware design RTL code.After the assembly test excitation generates, generate the memory mapped file (.img1) of corresponding binary mode simultaneously, be transferred to the software executive routine with latticed form.Hardware design and analogy model generate the corresponding results file respectively after loading memory mapped file, realize that by software program carries out comparison first time to the destination file of two kinds of models, in the correctness of hardware level verification hardware design.
Software realization program comprises software simulator and the workstation that (SuSE) Linux OS is installed.Software is realized the parameter configuration test environment of program according to input, is to utilize software simulator that hardware is simulated, in software levels hardware design is further verified.Software simulator is implanted co-verification platform software realization program to be called after being packaged into the .so library file, and all processor instruction functions have been realized in software simulator inside, can develop or utilize existing software simulator voluntarily.After the assembly test excitation generates, software realizes program compilation calling compilation tool, and excitation compiles and links to assembly test, but compiling generation software load document (.out) and hardware model can load memory mapped file (.img2) respectively, and realize that with hardware the memory mapped file of program compares, whether identical with the test and excitation that detects in the test.After the software/hardware model loads and to generate separately destination file behind the memory mapped file respectively, realize that by software Automatic Program finishes hardware design model result file and hardware simulation model and software simulator relatively and analysis, and with the analysis result file that journalises.
Hardware is realized the network service between program and the software realization program, be file transfer and the data communication between software simulator and the hardware design/analogy model, employing is based on the Network Transmission mode of ICP/IP protocol, be used for working in coordination with test at above-mentioned two workstations, communication realizes the synchronism control and the file transfer of test based on ICP/IP protocol, realize the synchro control of test with the UDP message, realize the automatic transmission of test file and read in the TCP mode, whenever, take turns test and comprise the synchronous control signal of realizing with the UDP message for four times, and the file transfer bout of realizing in the TCP mode for three times.
Above-mentionedly realize the synchronism control and the file transfer of test, realize the synchro control of test, realize the automatic transmission of test file and read that in the TCP mode its specific implementation (see figure 4) is with the UDP message based on ICP/IP protocol:
The first step: test beginning, software realize that the program executive routine utilizes the UDP message to initiate test request, after hardware components is received the UDP message, start test (Req1/Ack1) after returning confirmation signal;
Second step: behind the test starting, hardware components produces test and excitation with random fashion, and the memory mapped file (.img1) of further generation correspondence, link (Req2/Ack2) with UDP message and the foundation of software realization program, by the TCP mode test stimulus file and memory mapped file are transferred to software realization program, and deposit under the path of program appointment;
The 3rd step: software realization program reads test stimulus file and the memory mapped file that hardware realization program generates, collect, compile and link processing, but the memory mapped file (.img2) that load document (.out) that the generation software simulator needs and hardware need, and the memory mapped file that generates with hardware realization program relatively, whether loads identical test and excitation to check hardware design/analogy model and software emulation;
The 4th step: hardware realizes that program loads the 3rd memory mapped file (.img2) that goes on foot after the unanimity relatively in the TCP mode, generates hardware design (RTL code) result and hardware simulation result respectively;
The 5th step: after hardware design model and hardware simulation model result generate, hardware program links (Req3/Ack3) for the third time by UDP message and software realization program, destination file is transferred to software in the TCP mode realizes program, and deposit under the path of program appointment;
The 6th step: after the co-verification platform relatively finishes soft, hardware result, realize producing a pair of UDP ending request, answer signal (Req4/Ack4) between program and the hardware program at software, and finish the epicycle test, start the lower whorl test.
As shown in Figure 3, the processor co-verification platform test method of transmission Network Based, under the test environment of (SuSE) Linux OS workstation, its testing procedure is:
The first step: the test beginning, executive software realization program is imported two parameters respectively according to prompting: parameter 1 is provided with the number of rounds of tests that each test process verification platform is finished automatically, and parameter 2 is provided with the port numbers of communicating pair; And test environment is set according to parameter, set up three level files storing directory voluntarily to preserve all test file information.Wherein, ' ... / test ' is the test first class catalogue, deposit all test file sub-directories, begin to create once, do not repeat to create in test, ' ... / test/time/ ' named with the current time in system, deposit sub-directory and file that once test produces, when the test beginning, create, ' ... / test/time/i/ ' is used to deposit the All Files that the test of i wheel produces, each is taken turns test and creates once, ' ... / ' current directory at expression co-verification platform program place;
Second step: carry out hardware and realize program, produce test and excitation, and generate corresponding memory mapped file (.img1).Test and excitation is formed according to certain constraint at random by assembly instruction, the constraint that reaches of assembly instruction is to extract with random fashion the constraint function storehouse by program from the instruction functions storehouse, the packing of orders form of test and excitation is made up according to constraint rule at random by instruction, and generates corresponding scale-of-two memory mapped file (.img1);
The 3rd step: software realizes that program encourages with TCP mode read test, compiling generates the excitation file (.out) that software simulator can load, and further generate memory mapped file (.img2) that hardware design/analogy model needs and compare with memory mapped file that hardware realization program generates, to guarantee that every what take turns hardware design/simulation and software emulation loading in the test is same test and excitation;
The 4th step: relatively hardware is realized the memory mapped file that program and software realization program generate respectively, all is that hardware design/simulation and software emulation load identical test and excitation to guarantee that each takes turns checking.When memory mapped file was more inconsistent, the comparative result file that journalises finished the epicycle test, and when comparative result was consistent, the operating software emulator produced simulation result;
The 5th step: hardware design/analogy model is by reading/load memory mapped file (.img2) in the TCP mode, generate hardware design model result and hardware simulation model result respectively, be kept at that the first step describes when the Pretesting catalogue ' ... under/the test/time/i/ ';
The 6th step: comparative analysis hardware design model result and hardware simulation model result, and with analysis result journalise file (... / test/time/i/log.txt), this realizes that relatively hardware design model result and hardware simulation model verify mutually, with the correctness of checking RTL code;
The 7th step: output comparative analysis hardware design model running result and software emulation be (see figure 5) as a result, and with analysis result journalise file (... / test/time/i/log.txt), this relatively realizes the correctness of software levels checking RTL code;
The 8th step: software is realized program inquiring, and each takes turns the testing differentia destination file, with textual form (... / test/time/dirlog.txt) the test file place catalogue that there are differences of record, correct catalogue and the file of deletion result, the statistics coverage rate, file and beginning test next time journalise the functional verification coverage rate after finishing each time.
Claims (3)
1. the processor co-verification platform of a transmission Network Based is characterized in that: be made up of three parts of network service between hardware realization program, software realization program and hardware realization program and the software realization program; Hardware realization program comprises test and excitation, hardware design model, hardware simulation model and the workstation that (SuSE) Linux OS is installed; Test and excitation is combined to form according to certain constraint rule at random by assembly instruction, and the hardware design model generates with the Verilog hardware description language, and (Register Transfer Level RTL) carries out modeling in the register transfer level; The hardware simulation model carries out level verification just with C Plus Plus analog hardware design carrying out modeling to hardware design, and two models are abideed by identical design proposal, can have identical response to identical excitation; Software realization program comprises software simulator and the workstation that (SuSE) Linux OS is installed; Software is realized the parameter configuration test environment of program according to input, utilizes software simulator that hardware is simulated, in software levels hardware design is further verified; Hardware is realized the network service between program and the software realization program, adopts the synchronism control and the file transfer that realize test based on ICP/IP protocol, is used for working in coordination with test at above-mentioned two workstations.
2. the processor co-verification platform of a kind of transmission Network Based according to claim 1, it is characterized in that: described synchronism control and the file transfer that realizes test based on ICP/IP protocol, it is the synchro control that realizes test with the UDP message, realize the automatic transmission of test file and read that in the TCP mode its specific implementation is:
The first step: test beginning, software realize that the program executive routine utilizes the UDP message to initiate test request, after hardware components is received the UDP message, start test (Req1/Ack1) after returning confirmation signal;
Second step: behind the test starting, hardware components produces test and excitation with random fashion, and the memory mapped file (.img1) of further generation correspondence, link (Req2/Ack2) with UDP message and the foundation of software realization program, by the TCP mode test stimulus file and memory mapped file are transferred to software realization program, and deposit under the path of program appointment;
The 3rd step: software realization program reads test stimulus file and the memory mapped file that hardware realization program generates, collect, compile and link processing, but the memory mapped file (.img2) that load document (.out) that the generation software simulator needs and hardware need, and the memory mapped file that generates with hardware realization program relatively, whether loads identical test and excitation to check hardware design/analogy model and software emulation;
The 4th step: hardware realizes that program loads the 3rd memory mapped file (.img2) that goes on foot after the unanimity relatively in the TCP mode, generates hardware design (RTL code) result and hardware simulation result respectively;
The 5th step: after hardware design model and hardware simulation model result generate, hardware program links (Req3/Ack3) for the third time by UDP message and software realization program, destination file is transferred to software in the TCP mode realizes program, and deposit under the path of program appointment;
The 6th step: after the co-verification platform relatively finishes soft, hardware result, realize producing a pair of UDP ending request, answer signal (Req4/Ack4) between program and the hardware program at software, and finish the epicycle test, start the lower whorl test.
3. the processor co-verification platform test method of a transmission Network Based, under the test environment of (SuSE) Linux OS workstation, its testing procedure is:
The first step: the test beginning, executive software realization program is imported two parameters respectively according to prompting: parameter 1 is provided with the number of rounds of tests that each test process verification platform is finished automatically, and parameter 2 is provided with the port numbers of communicating pair; And test environment is set according to parameter, set up three level files storing directory voluntarily to preserve all test file information;
Second step: carry out hardware and realize program, produce test and excitation, and generate corresponding memory mapped file (.img1),
Test and excitation is formed according to certain constraint at random by assembly instruction, the constraint that reaches of assembly instruction is to extract with random fashion the constraint function storehouse by program from the instruction functions storehouse, the packing of orders form of test and excitation is made up according to constraint rule at random by instruction, and generates corresponding scale-of-two memory mapped file (.img1);
The 3rd step: software realizes that program encourages with TCP mode read test, compiling generates the excitation file (.out) that software simulator can load, and further generate memory mapped file (.img2) that hardware design/analogy model needs and compare with memory mapped file that hardware realization program generates, to guarantee that every what take turns hardware design/simulation and software emulation loading in the test is same test and excitation;
The 4th step: relatively hardware is realized the memory mapped file that program and software realization program generate respectively, to guarantee that each takes turns checking all is that hardware design/simulation loads identical test and excitation with software emulation, when memory mapped file is more inconsistent, the comparative result file that journalises, finish the epicycle test, when comparative result was consistent, the operating software emulator produced simulation result;
The 5th step: hardware design/analogy model generates hardware design model result and hardware simulation model result respectively by read/load memory mapped file (.img2) in the TCP mode, and is kept under the Pretesting catalogue;
The 6th step: comparative analysis hardware design model result and hardware simulation model result, and with the analysis result file that journalises, this realizes that relatively hardware design model result and hardware simulation model verify mutually, with the correctness of checking RTL code;
The 7th step: output comparative analysis hardware design model running result and software emulation result, and with the analysis result file that journalises, this relatively realizes the correctness of software levels checking RTL code;
The 8th step: software is realized program inquiring, and each takes turns the testing differentia destination file, write down the test file place catalogue that there are differences with textual form, correct catalogue and the file of deletion result, the statistics coverage rate, file and beginning test next time journalise the functional verification coverage rate after finishing each time.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6223272B1 (en) * | 1998-07-15 | 2001-04-24 | Siemens Aktiengesellschaft | Test vector verification system |
| US20080167853A1 (en) * | 2007-01-09 | 2008-07-10 | Fernsler Matthew E | Method and System for Testing An Operation of Integrated Circuitry |
| CN202110531U (en) * | 2011-04-22 | 2012-01-11 | 中国电子科技集团公司第三十八研究所 | Processor collaborative verification platform based on network transmission |
-
2011
- 2011-04-22 CN CN2011101011156A patent/CN102147760A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6223272B1 (en) * | 1998-07-15 | 2001-04-24 | Siemens Aktiengesellschaft | Test vector verification system |
| US20080167853A1 (en) * | 2007-01-09 | 2008-07-10 | Fernsler Matthew E | Method and System for Testing An Operation of Integrated Circuitry |
| CN202110531U (en) * | 2011-04-22 | 2012-01-11 | 中国电子科技集团公司第三十八研究所 | Processor collaborative verification platform based on network transmission |
Non-Patent Citations (2)
| Title |
|---|
| 欧明双: "面向DSP芯片统一验证平台的研究与实现", 《中国优秀硕士学位论文全文数据库》, 12 September 2009 (2009-09-12), pages 137 - 89 * |
| 鲍华，洪一，郭二辉: "面向Soc的软硬件协同验证平台设计", 《计算机工程》, vol. 35, no. 8, 20 May 2009 (2009-05-20) * |
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