CN113283211A - Microprocessor automatic verification method and verification device based on Verilog - Google Patents
Microprocessor automatic verification method and verification device based on Verilog Download PDFInfo
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- CN113283211A CN113283211A CN202110550463.5A CN202110550463A CN113283211A CN 113283211 A CN113283211 A CN 113283211A CN 202110550463 A CN202110550463 A CN 202110550463A CN 113283211 A CN113283211 A CN 113283211A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3604—Software analysis for verifying properties of programs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3664—Environments for testing or debugging software
Abstract
The invention relates to the technical field of communication, in particular to a microprocessor automatic verification method and a verification device based on Verilog. The microprocessor automatic verification method based on Verilog comprises the following steps: establishing a mapping corresponding relation, wherein the mapping corresponding relation comprises a plurality of calling modules and a plurality of test excitation modules in one-to-one correspondence with the calling modules, and the test excitation modules are used for generating test excitation; calling a target calling module required by current verification of a circuit to be tested in a microprocessor; selecting a target test excitation module corresponding to the target calling module according to the mapping corresponding relation; and loading the target test excitation generated by the target test excitation module to the circuit to be tested so as to verify the circuit to be tested. The invention simplifies the verification process of the microprocessor, reduces the workload of testers and shortens the design period of the microprocessor.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a microprocessor automatic verification method and a verification device based on Verilog.
Background
The performance of a microprocessor, which is the most core component in a computer system, directly affects the performance of the entire computer system, and therefore, it is important to verify the function of the microprocessor and ensure the correctness of the function. With the continuous development of integrated circuit technology, the scale of microprocessor chips is increasing and the design complexity is increasing, and the verification becomes more and more difficult.
Fig. 1 is a flow chart of a chip design in the prior art. As shown in fig. 1, multiple verifications are required in the design flow of the whole chip, and the verification accounts for about 70% of the workload. In the verification process of the microprocessor, a verification platform needs to be independently established for each test, the verification process is extremely complicated, the workload of test developers is increased, and the design period of the microprocessor is prolonged.
Therefore, how to simplify the verification operation of the microprocessor, shorten the design cycle of the microprocessor, and reduce the workload of the tester is a technical problem to be solved at present.
Disclosure of Invention
The invention provides a method and a device for automatically verifying a microprocessor based on Verilog, which are used for solving the problems of complex operation and large workload in the verification process of the microprocessor in the prior art, so as to shorten the design period of the microprocessor and reduce the workload of testers.
In order to solve the above problems, the present invention provides an automatic verification method for a microprocessor based on Verilog, which comprises the following steps:
establishing a mapping corresponding relation, wherein the mapping corresponding relation comprises a plurality of calling modules and a plurality of test excitation modules in one-to-one correspondence with the calling modules, and the test excitation modules are used for generating test excitation;
calling a target calling module required by current verification of a circuit to be tested in a microprocessor;
selecting a target test excitation module corresponding to the target calling module according to the mapping corresponding relation;
and loading the target test excitation generated by the target test excitation module to the circuit to be tested so as to verify the circuit to be tested.
Optionally, the specific step of establishing the mapping correspondence includes:
building a compiling environment;
and writing a test program for generating test excitation to form the test excitation module.
Optionally, the specific step of writing a test program for generating test stimuli includes:
the test program for generating the test stimulus is written in assembly language or C language.
Optionally, the specific step of establishing the mapping correspondence further includes:
writing a plurality of calling programs to form a plurality of calling modules, wherein the calling programs have the same starting identifier and ending identifier.
Optionally, the specific step of calling a target calling module required by the current verification of the circuit to be tested in the microprocessor includes:
setting a calling identifier;
and inputting the calling identifier and the name of a target calling module, and calling the target calling module required by the current verification of the circuit to be tested in the microprocessor.
In order to solve the above problems, the present invention further provides an automated verification apparatus for a microprocessor based on Verilog, including:
the storage module is used for storing a mapping corresponding relation, the mapping corresponding relation comprises a plurality of calling modules and a plurality of test excitation modules which are in one-to-one correspondence with the calling modules, and the test excitation modules are used for generating test excitation;
the calling module is used for calling a target calling module required by the current verification of a circuit to be tested in the microprocessor;
the matching module is used for selecting a target test excitation module corresponding to the target calling module according to the mapping corresponding relation;
and the test module is used for loading the target test excitation generated by the target test excitation module to the circuit to be tested so as to verify the circuit to be tested.
Optionally, the method further includes:
the building module is used for building a compiling environment;
and the compiling module is used for compiling a test program for generating test excitation to form the test excitation module.
Optionally, the compiling module is configured to write a test program for generating a test stimulus in an assembly language or a C language.
Optionally, the compiling module is further configured to compile a plurality of calling programs to form a plurality of calling modules, where the plurality of calling programs have the same start identifier and end identifier.
Optionally, the calling module is configured to input a preset calling identifier and a name of a target calling module, and call the target calling module required by current verification of a circuit to be tested in the microprocessor.
The method and the device for automatically verifying the microprocessor based on the Verilog realize the hierarchical calling of the test excitation module by establishing the mapping corresponding relation, and have higher flexibility and easy operability. Based on the established mapping corresponding relation, the test task of the circuit to be tested is separated from the test excitation module, so that the test verification is more flexible, and when different circuits to be tested or different functions of the microprocessor are tested, only the calling module at the top layer needs to be adjusted, so that the verification process of the microprocessor is simplified, the workload of testers is reduced, and the design cycle of the microprocessor is shortened.
Drawings
FIG. 1 is a flow diagram of a prior art chip design;
FIG. 2 is a flow chart of a method for automatically verifying a microprocessor based on Verilog according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a microprocessor automatic verification process based on Verilog implementation according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating a hierarchical call relationship in the automated verification process of a microprocessor based on Verilog according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating a specific definition of a-D instruction according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating the detailed definition of an instruction for-f according to an embodiment of the present invention;
fig. 7 is a block diagram of an automated verification apparatus for a microprocessor based on Verilog according to an embodiment of the present invention.
Detailed Description
The following describes in detail specific embodiments of the method for automatically verifying a microprocessor based on Verilog and the verification apparatus thereof according to the present invention with reference to the accompanying drawings.
The present embodiment provides an automatic verification method for a microprocessor based on Verilog, fig. 2 is a flowchart of the automatic verification method for a microprocessor based on Verilog according to the present embodiment, and fig. 3 is a diagram of the automatic verification process for a microprocessor based on Verilog according to the present embodiment. As shown in fig. 2 and fig. 3, the method for automatically verifying a microprocessor based on Verilog according to this embodiment includes the following steps:
step S11, establishing a mapping corresponding relation, wherein the mapping corresponding relation comprises a plurality of calling modules and a plurality of test excitation modules corresponding to the calling modules one by one, and the test excitation modules are used for generating test excitation.
Specifically, before the verification of the microprocessor, a plurality of test excitation modules are established according to the structural or functional verification requirement of the microprocessor, each test excitation module is used for generating a test excitation, and whether the work of the circuit to be tested is normal or not is judged through the response of the circuit to be tested to the test excitation. The test excitation generated by the test excitation modules are different from each other, so that the verification of different circuit structures or functions to be tested in the microprocessor is realized. The plurality of calling modules correspond to the plurality of test excitation modules one by one, and each calling module is used for calling the corresponding test excitation module. And the test excitation module generates test excitation after being called by the calling module, transmits the generated test excitation to the circuit to be tested, and verifies the structure or function of the circuit to be tested. The plurality described in this embodiment means two or more.
Optionally, the specific step of establishing the mapping correspondence includes:
building a compiling environment;
and writing a test program for generating test excitation to form the test excitation module.
Optionally, the specific step of writing a test program for generating test stimuli includes:
the test program for generating the test stimulus is written in assembly language or C language.
Specifically, the test stimulus module generates the test stimulus by calling a test program, the test program can be compiled by assembly language or C language, and the simulation, the memory and the circuit can be expressed by Verilog hardware description language. Building a compilation environment may make compiling multiple types of test programs easier and more efficient.
The specific type of the coding environment in this embodiment may be selected by a person skilled in the art according to actual needs, and optionally, the coding environment may be riscv-none-embed-gcc joint coding. Taking the example of writing the test program in the assembly language, the makefile for compiling the assembly program is as follows:
add:DEST_NAME＝add
add:
$(AS_MIPS)-o hdr.o-march rv32im../lib/asm_hdr_gdr.s
$(AS_MIPS)-o h0.o-march rv32im../Type_V2/add.s
$(LD_MIPS)$(LDFLAGS)-Map test.map-melf32lriscv-o test.axf hdr.o h0.o
$(PROCESS_DATA_PLAIN)
in the makefile, the first line is the name of the program, and $ (AS _ MIPS) is a compilation command, and the assembly file is compiled by using elf, and then, an o file is generated after the compilation. The (LD _ MIPS) is a link command that links the compiled files. (PROCESS _ DATA _ play) is to generate various types of files and put the generated files into corresponding folders.
Optionally, the specific step of establishing the mapping correspondence further includes:
writing a plurality of calling programs to form a plurality of calling modules, wherein the calling programs have the same starting identifier and ending identifier.
For example, in fig. 3, n call modules and n test stimulus modules (i.e., test stimulus module task1, test stimulus module task2, test stimulus module task3, test stimulus modules task4, … …, and test stimulus module task) corresponding to the n call modules (i.e., call module test1, call module test2, call module test3, call modules test4, … …, and call module test) one to one are provided, where n is an integer greater than or equal to 4. The program names of the calling modules may be test _ r5_ add, test _ r5_ sub, etc., and the program of each calling module starts with a "" ifdef "" and ends with a "" end "". One of the procedures for calling the module is as follows:
each calling module sets a test time and the called test stimulus module, the program names of the test stimulus modules can be task run _ r5_ add and task run _ r5_ sub, and each test stimulus module calls an assembly language/C language test program for generating stimulus. The skilled person can also perform operations such as setting of a test environment, instantiation of an entire circuit, and the like according to actual needs. The procedure for testing the stimulus module is as follows:
and step S12, calling a target calling module required by the current verification of the circuit to be tested in the microprocessor.
And step S13, selecting a target test excitation module corresponding to the target calling module according to the mapping corresponding relation.
And step S14, loading the target test excitation generated by the target test excitation module to the circuit to be tested so as to verify the circuit to be tested.
Optionally, the specific step of calling a target calling module required by the current verification of the circuit to be tested in the microprocessor includes:
setting a calling identifier;
and inputting the calling identifier and the name of a target calling module, and calling the target calling module required by the current verification of the circuit to be tested in the microprocessor.
Specifically, after the verification content required to be performed by the circuit to be tested currently is confirmed, the name of the target calling module is input behind the calling identifier, and according to the mapping corresponding relation, the target test excitation is finally generated by the target test excitation module and input to the circuit to be tested so as to verify the circuit to be tested. For example, the call identifier may be the virilog command shown in the following procedure:
iverilog-D test_r5_add-f t_c2e_r5
"-D" is followed by the called top-level module name (i.e., the program name of the target calling module) and "-f" is followed by the name list of the netlist. FIG. 5 is a diagram illustrating a specific definition of a-D instruction according to an embodiment of the present invention. As can be seen in FIG. 5, "-D" is followed by the called top-level module name, which by definition specifies a macro that can be verified by # ifdef in the source code. FIG. 6 is a diagram illustrating the detailed definition of an instruction for-f according to an embodiment of the present invention. As can be seen in FIG. 6, these instructions specify an input file containing a list of Verilog source files, the parameters behind "-f" are a list of names for the netlist,
the microprocessor automatic verification method based on Verilog provided by the specific embodiment has higher flexibility and easy operability in the hierarchical verification process; the built compiling environment can automatically generate software in various formats; separating the tasks and stimuli makes test validation more flexible. Based on the mapping corresponding relation established in advance, if different functions are tested or different times are tested, only a few parameters need to be changed in the top module (namely, only the name of the calling module behind the calling identifier needs to be changed).
Moreover, the present embodiment further provides an automatic verification device for a microprocessor based on Verilog, and fig. 7 is a block diagram of the automatic verification device for a microprocessor based on Verilog according to the present embodiment. The automated verification apparatus for a microprocessor based on Verilog according to the present embodiment may use the automated verification method for a microprocessor based on Verilog as shown in fig. 1 to 6 to verify the microprocessor. As shown in fig. 1 to 7, the microprocessor automatic verification apparatus based on Verilog includes:
the storage module 50 is configured to store a mapping correspondence relationship, where the mapping correspondence relationship includes a plurality of calling modules and a plurality of test excitation modules corresponding to the plurality of calling modules one to one, and the test excitation modules are configured to generate test excitation;
the calling module 51 is used for calling a target calling module required by the current verification of a circuit to be tested in the microprocessor;
the matching module 52 is configured to select a target test excitation module corresponding to the target calling module according to the mapping correspondence;
and the test module 53 is configured to load the target test stimulus generated by the target test stimulus module to the circuit to be tested, so as to verify the circuit to be tested.
Optionally, the microprocessor automatic verification apparatus implemented based on Verilog further includes:
a building module 54 for building a compiling environment;
a compiling module 55 for compiling a test program for generating a test stimulus, forming the test stimulus module.
Optionally, the compiling module 55 is configured to write a test program for generating a test stimulus in an assembly language or a C language.
Optionally, the compiling module 55 is further configured to compile a plurality of calling programs to form a plurality of calling modules, where the plurality of calling programs have the same start identifier and end identifier.
Optionally, the calling module is configured to input a preset calling identifier and a name of a target calling module, and call the target calling module required by current verification of a circuit to be tested in the microprocessor.
The Verilog-based microprocessor automatic verification method and the verification device thereof provided by the specific embodiment realize hierarchical calling of the test stimulus module by establishing the mapping corresponding relation, and have higher flexibility and easy operability. Based on the established mapping corresponding relation, the test task of the circuit to be tested is separated from the test excitation module, so that the test verification is more flexible, and when different circuits to be tested or different functions of the microprocessor are tested, only the calling module at the top layer needs to be adjusted, so that the verification process of the microprocessor is simplified, the workload of testers is reduced, and the design cycle of the microprocessor is shortened.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A microprocessor automatic verification method based on Verilog is characterized by comprising the following steps:
establishing a mapping corresponding relation, wherein the mapping corresponding relation comprises a plurality of calling modules and a plurality of test excitation modules in one-to-one correspondence with the calling modules, and the test excitation modules are used for generating test excitation;
calling a target calling module required by current verification of a circuit to be tested in a microprocessor;
selecting a target test excitation module corresponding to the target calling module according to the mapping corresponding relation;
and loading the target test excitation generated by the target test excitation module to the circuit to be tested so as to verify the circuit to be tested.
2. The Verilog-based microprocessor automatic verification method according to claim 1, wherein the specific step of establishing the mapping correspondence comprises:
building a compiling environment;
and writing a test program for generating test excitation to form the test excitation module.
3. The Verilog-based microprocessor automated verification method of claim 2, wherein the specific step of writing a test program for generating test stimuli comprises:
the test program for generating the test stimulus is written in assembly language or C language.
4. The Verilog-based microprocessor automatic verification method according to claim 1, wherein the specific step of establishing the mapping correspondence further comprises:
writing a plurality of calling programs to form a plurality of calling modules, wherein the calling programs have the same starting identifier and ending identifier.
5. The Verilog-based microprocessor automatic verification method as claimed in claim 1, wherein the specific step of calling the target calling module required for the current verification of the circuit to be tested in the microprocessor comprises:
setting a calling identifier;
and inputting the calling identifier and the name of a target calling module, and calling the target calling module required by the current verification of the circuit to be tested in the microprocessor.
6. A microprocessor automatic verification device based on Verilog implementation is characterized by comprising:
the storage module is used for storing a mapping corresponding relation, the mapping corresponding relation comprises a plurality of calling modules and a plurality of test excitation modules which are in one-to-one correspondence with the calling modules, and the test excitation modules are used for generating test excitation;
the calling module is used for calling a target calling module required by the current verification of a circuit to be tested in the microprocessor;
the matching module is used for selecting a target test excitation module corresponding to the target calling module according to the mapping corresponding relation;
and the test module is used for loading the target test excitation generated by the target test excitation module to the circuit to be tested so as to verify the circuit to be tested.
7. The Verilog-based microprocessor automated validation apparatus according to claim 6, further comprising:
the building module is used for building a compiling environment;
and the compiling module is used for compiling a test program for generating test excitation to form the test excitation module.
8. The Verilog-based microprocessor automated validation apparatus according to claim 7, wherein the compiling module is configured to write a test program for generating test stimuli in assembly language or C language.
9. The Verilog-based microprocessor automated validation apparatus of claim 7, wherein the compiling module is further configured to write a plurality of calling programs, forming a plurality of calling modules, the plurality of calling programs having the same start identifier and end identifier.
10. The Verilog-based microprocessor automated verification device according to claim 6, wherein the calling module is configured to input a preset calling identifier and a name of a target calling module, and call the target calling module required for current verification of a circuit to be tested in the microprocessor.
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