CN110688821A - Test excitation generator of complex algorithm and control method thereof - Google Patents
Test excitation generator of complex algorithm and control method thereof Download PDFInfo
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Abstract
The invention relates to a test excitation generator of a complex algorithm and a control method thereof, wherein the test excitation generator comprises the following steps: the device comprises a fixed vector generation module, a random vector generation module, a special vector generation module, a time sequence monitoring module, a verification scheme input interface module, a time sequence signal input interface module and a test excitation output interface module; the fixed vector generation module generates excitation such as register reset read-write attribute and the like, and the random vector generation module generates constrained randomized excitation; the special vector generation module generates special excitation which cannot be generated by adopting SystemVerilog randomization command; the test excitation generator acquires control signals through the verification scheme input interface module, respectively controls different vector generation modules to generate corresponding test excitation, and outputs the test excitation through the test excitation output interface module; the test excitation generator acquires a control signal through the time sequence signal input interface module, and controls the loading and verification starting of the output test excitation; and the time sequence monitoring module monitors the state information of the complex algorithm verification system through the time sequence signal input interface module. The method is suitable for the test excitation generation of the complex algorithm realized by pure hardware or software and hardware in a cooperative way, and can effectively improve the quality and efficiency of the verification of the complex algorithm.
Description
Technical Field
The invention belongs to the simulation verification of a complex algorithm module in the field of integrated circuit design, and particularly relates to a test excitation generator of a complex algorithm and a control method thereof.
Background
Generally, the complexity of the algorithm determines the complexity of the RTL implementation to a great extent, and in order to ensure the functional coverage of the verification, the RTL simulation verification scheme of the complex algorithm inevitably becomes huge and cumbersome. Particularly, according to different application requirements, the same type of complex algorithm may adopt multiple implementation modes such as software and hardware cooperation or pure hardware, so as to obtain more flexible application characteristics or achieve higher data throughput rate. The high complexity and diversified implementation modes greatly increase the difficulty of RTL simulation verification of the complex algorithm.
In order to realize the complex algorithm verification (such as a deep learning algorithm, a public key algorithm and the like) realized by software and hardware cooperation or pure hardware, the invention discloses a test excitation generator of a complex algorithm and a control method thereof, which can be suitable for the test excitation generation of the complex algorithm realized by the software and hardware cooperation or the pure hardware, can be applied to a traditional simulation verification structure based on Verilog/SystemVerilog or a simulation verification structure based on UVM methodology, effectively reduces the simulation verification difficulty and improves the quality and the efficiency of the complex algorithm verification.
Disclosure of Invention
The invention provides a test stimulus generator of a complex algorithm, which can realize the test stimulus generation of the complex algorithm only by adding a test stimulus generator module on the basis of the original verification environment (based on a Verilog/SystemVerilog traditional simulation verification structure or a UVM methodology simulation verification structure); the complex algorithm test excitation generator is suitable for complex algorithm verification realized by software and hardware cooperation or pure hardware, reduces the simulation verification difficulty and improves the verification quality of the complex algorithm.
The invention provides a control method of a test excitation generator of a complex algorithm, which realizes the efficient generation and loading of test excitation and can improve the verification efficiency of the complex algorithm.
The invention provides a test excitation generator (100) of a complex algorithm, which comprises a fixed vector generation module (101), a random vector generation module (102), a special vector generation module (103), a time sequence monitoring module (104), a verification scheme input interface module (105), a time sequence signal input interface module (106) and a test excitation output interface module (107); the method comprises the steps that a test excitation generation control signal is input to a test excitation generator (100) through a verification scheme input interface module (105), the test excitation generator (100) obtains a time sequence signal from a complex algorithm verification system (108) through a time sequence signal input interface module (106), the time sequence signal is processed through a time sequence monitoring module (104) and used for controlling loading and verification starting of the test excitation, and the test excitation generator (100) generates the test excitation and outputs the test excitation to the complex algorithm verification system (108) through a test excitation output interface module (107).
In a test stimulus generator (100) of a complex algorithm, a fixed vector generation module (101) realizes test stimulus generation of a register reset value, a register read-write attribute and an RAM read-write attribute.
In a test stimulus generator (100) for a complex algorithm, a randomization mechanism of a random vector generation module (102) generates legal random data conforming to an input data format of the complex algorithm and illegal random data not conforming to the input data format of the complex algorithm using a randomization command of SystemVerilog.
In a test stimulus generator (100) of a complex algorithm, a special vector generation module (103) has a complex algorithm operation function and can generate a special stimulus conforming to a complex operation characteristic.
In a complex algorithm test stimulus generator (100), a timing monitor module (104) monitors in real time a timing signal of the complex algorithm module and controls a loading process of a test stimulus.
In a test stimulus generator (100) of a complex algorithm, a verification scheme input interface module (105) requires input of a verification scheme including at least generation control signals of a fixed vector, a random vector, and a special vector.
In a test stimulus generator (100) for a complex algorithm, a timing signal input interface module (106) is connected to a complex algorithm verification environment (108) by way of hierarchical access.
In a test stimulus generator (100) of a complex algorithm, a test stimulus output interface module (107) outputs a test stimulus in the form of a Task conforming to Verilog syntax or a Sequence conforming to UVM methodology.
According to another aspect of the invention, a control method for a test stimulus generator for a complex algorithm is shown in FIG. 3.
Step S1: analyzing the verification scheme;
step S2: generating, loading and verifying a fixed vector to start;
step S3: generating, loading and verifying a random vector to start;
step S4: judging whether the data vector is a special data vector in the special vector, if so, jumping to the step S5, otherwise, jumping to the step S6;
step S5: calling a complex algorithm to operate to generate a special data vector in the special vector;
step S6: judging whether the time sequence vector is a special time sequence vector in the special vectors, if so, jumping to the step S7, otherwise, jumping to the step S8;
step S7: initializing time sequence vector loading;
step S8: starting time sequence monitoring;
step S9: loading a special vector and starting verification;
step S10: a hybrid vector, which is a random combination of a fixed vector, a random vector, and a special vector, is loaded and authentication is initiated.
Drawings
FIG. 1 is a schematic diagram of a test stimulus generator structure for a complex algorithm.
Fig. 2 is a schematic diagram of an application example of a test stimulus generator of a complex algorithm in a UVM verification environment.
FIG. 3 is a flow chart of a test stimulus generator control method of a complex algorithm.
Detailed Description
In order to more clearly describe the technical scheme of the invention, the invention is described in detail with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, a test stimulus generator (100) of a complex algorithm is composed of a fixed vector generation module (101), a random vector generation module (102), a special vector generation module (103), a timing monitoring module (104), a verification scheme input interface module (105), a timing signal input interface module (106), and a test stimulus output interface module (107); the method comprises the steps that a test excitation generation control signal is input to a test excitation generator (100) through a verification scheme input interface module (105), the test excitation generator (100) obtains a time sequence signal from a complex algorithm verification system (108) through a time sequence signal input interface module (106), the time sequence signal is processed through a time sequence monitoring module (104) and used for controlling loading and verification starting of the test excitation, and the test excitation generator (100) generates the test excitation and outputs the test excitation to the complex algorithm verification system (108) through a test excitation output interface module (107).
A complex algorithm test stimulus generator (100) is used to generate five complex algorithm test stimuli, a fixed vector sequence, a random vector sequence, a special data vector sequence, a special timing vector sequence, and a mixed vector sequence.
As shown in fig. 2, the present invention is applied on the basis of a classical UVM verification structure, taking verification of SM2 signature verification operation implemented by software and hardware as an example, and more specifically, details of application of the complex algorithm test stimulus generator (100) are described. (the SM2 signature checking operation can be decomposed into hash operation, dot multiplication operation, and modulo addition and subtraction operation, in this embodiment, the hash operation is implemented by external software scheduling, the dot multiplication and modulo addition and subtraction operation are implemented in the SM2 algorithm implementation module (DUT), and the hash operation and the dot multiplication operation are performed in parallel).
Step S1: the test excitation generator (100) obtains a verification scheme through the verification scheme input interface module (105), and analyzes the verification scheme to obtain generation control signals of a fixed vector, a random vector, a special vector and a mixed vector.
The SM2 algorithm implements passing of timing signals of a module (DUT) through an output Interface (O-Interface) to a timing signal input Interface module (106).
Step S2: generating a control signal according to the fixed vector, calling a fixed vector generating module (101) to generate the fixed vectors of the reset value, the read-write attribute and the RAM read-write attribute of the special function register, outputting the fixed vectors to a Sequence (Sequence) through a test excitation output interface module (107), controlling the loading process of the fixed vectors according to the time Sequence signal and starting verification.
Step S3: generating a control signal according to a random vector, calling a random vector generation module (102) to generate random signature data (r, s) and a hash value e, noting that the probability of combination of the signature data (r, s) and the hash value e is an illegal value, outputting the signature data to a Sequence (Sequence) through a test excitation output interface module (107), controlling the loading process of the signature data according to a time Sequence signal and starting verification.
Steps S4, S5: and generating a control signal according to the special vector, judging whether to generate a special data vector in the special vector, if so, calling a special vector generation module (103), and obtaining a legal public and private key pair, signature data (r, S) and a hash value e combination by adopting an SM2 public and private key pair generation algorithm and an SM2 signature algorithm, otherwise, jumping to the step S6.
Steps S6, S7: and judging whether to generate a special time sequence vector in the special vectors according to the special vector generation control signal, if so, initializing the time sequence vector, and otherwise, jumping to the step S8.
Step S8: and calling a time sequence monitoring module (104) to monitor the end mark of the dot product operation in the SM2 signature checking operation process in real time so as to ensure that the hash value e is used after the dot product operation is finished and ensure the flow legality of the SM2 signature checking operation.
Step S9: special vectors are loaded and validation is initiated based on feedback from the timing monitor module (104).
Step S10: and loading a fixed vector, a random vector or a special vector according to the six combined modes of the mixed vector, starting verification, covering all possible combined use modes in the SM2 signature verification operation process, and improving the verification coverage rate.
Claims (10)
1. A test stimulus generator for complex algorithms, comprising essentially: the test excitation generator (100) is composed of a fixed vector generation module (101), a random vector generation module (102), a special vector generation module (103), a time sequence monitoring module (104), a verification scheme input interface module (105), a time sequence signal input interface module (106) and a test excitation output interface module (107); the method comprises the steps that a test excitation generation control signal is input to a test excitation generator (100) through a verification scheme input interface module (105), the test excitation generator (100) obtains a time sequence signal from a complex algorithm verification system (108) through a time sequence signal input interface module (106), the time sequence signal is processed through a time sequence monitoring module (104) and used for controlling loading and verification starting of the test excitation, and the test excitation generator (100) generates the test excitation and outputs the test excitation to the complex algorithm verification system (108) through a test excitation output interface module (107).
2. The test stimulus generator of a complex algorithm according to claim 1, characterized in that the fixed vector generation module (101) implements test stimulus generation of register reset values, register read-write properties and RAM read-write properties.
3. The test stimulus generator of a complex algorithm of claim 1, wherein the randomization mechanism of the random vector generation module (102) employs a randomization command of System Verilog to generate legal random data that conforms to the input data format of the complex algorithm and illegal random data that does not conform to the input data format of the complex algorithm.
4. The test stimulus generator of a complex algorithm according to claim 1, characterized in that the special vector generation module (103) has a complex algorithm operation function and is capable of generating special stimuli conforming to complex operation characteristics.
5. The complex algorithmic test stimulus generator of claim 1, characterized in that the timing monitoring module (104) monitors the timing signals of the complex algorithmic module in real time and controls the loading process of the test stimulus.
6. The test stimulus generator of a complex algorithm of claim 1, characterized in that the validation scheme input interface module (105) requires input of validation schemes comprising at least generation control signals of fixed vectors, random vectors and special vectors.
7. The test stimulus generator of a complex algorithm of claim 1, wherein the timing signal input interface module (106) is connected to the complex algorithm verification system (108) by way of hierarchical access.
8. The test stimulus generator of a complex algorithm of claim 1, characterized in that the test stimulus output interface module (107) outputs the test stimulus in the form of a Task according to Verilog syntax or a Sequence according to UVM methodology.
9. A control method of a test stimulus generator of a complex algorithm based on the test stimulus generator of a complex algorithm of claim 1, characterized by the main steps comprising:
step S1: analyzing the verification scheme;
step S2: generating, loading and verifying a fixed vector to start;
step S3: generating, loading and verifying a random vector to start;
step S4: judging whether the data vector is a special data vector in the special vector, if so, continuing to step S5, otherwise, jumping to step S6;
step S5: calling a complex algorithm to operate to generate a special data vector in the special vector;
step S6: judging whether the time sequence vector is a special time sequence vector in the special vectors, if so, continuing to step S7, otherwise, jumping to step S8;
step S7: initializing time sequence vector loading;
step S8: starting time sequence monitoring;
step S9: loading a special vector and starting verification;
step S10: a hybrid vector, which is a random combination of a fixed vector, a random vector, and a special vector, is loaded and authentication is initiated.
10. The control method according to claim 9, wherein the random combination of the hybrid vectors includes six of a fixed vector + a random vector, a fixed vector + a special vector, a random vector + a fixed vector, a random vector + a special vector, a special vector + a fixed vector, and a special vector + a random vector.
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| CN112198423A (en) * | 2020-09-25 | 2021-01-08 | 杭州加速科技有限公司 | Test excitation generating unit in FPGA chip |
| CN113157269A (en) * | 2021-06-10 | 2021-07-23 | 上海齐感电子信息科技有限公司 | Verification system and verification method thereof |
| CN113283211A (en) * | 2021-05-20 | 2021-08-20 | 复旦大学 | Microprocessor automatic verification method and verification device based on Verilog |
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| CN113283211A (en) * | 2021-05-20 | 2021-08-20 | 复旦大学 | Microprocessor automatic verification method and verification device based on Verilog |
| CN113157269A (en) * | 2021-06-10 | 2021-07-23 | 上海齐感电子信息科技有限公司 | Verification system and verification method thereof |
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