CN110688821B - Test excitation generator of complex algorithm and control method thereof - Google Patents
Test excitation generator of complex algorithm and control method thereof Download PDFInfo
- Publication number
- CN110688821B CN110688821B CN201910925904.8A CN201910925904A CN110688821B CN 110688821 B CN110688821 B CN 110688821B CN 201910925904 A CN201910925904 A CN 201910925904A CN 110688821 B CN110688821 B CN 110688821B
- Authority
- CN
- China
- Prior art keywords
- vector
- special
- complex algorithm
- verification
- time sequence
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The invention relates to a test excitation generator of a complex algorithm and a control method thereof, which comprises the following steps: the system comprises a fixed vector generation module, a random vector generation module, a special vector generation module, a time sequence monitoring module, a verification scheme input interface module, a time sequence signal input interface module and a test excitation output interface module; the fixed vector generation module generates excitation such as register reset read-write attribute and the like, and the random vector generation module generates constrained random excitation; the special vector generation module generates special stimulus which cannot be generated by adopting a SystemVerilog randomization command; the test excitation generator acquires control signals through the verification scheme input interface module, respectively controls different vector generation modules to generate corresponding test excitation, and outputs the test excitation through the test excitation output interface module; the test excitation generator acquires a control signal through a timing signal input interface module, and controls the loading and verification starting of the output test excitation; the time sequence monitoring module monitors the state information of the complex algorithm verification system through the time sequence signal input interface module. The method is suitable for test excitation generation of the complex algorithm realized by pure hardware or soft-hard cooperation, and can effectively improve the quality and efficiency of complex algorithm verification.
Description
Technical Field
The invention belongs to simulation verification of a complex algorithm module in the field of integrated circuit design, and particularly relates to a test excitation generator of a complex algorithm and a control method thereof.
Background
In general, the complexity of the algorithm determines the complexity of the RTL implementation to a great extent, and in order to ensure the functional coverage rate of verification, the RTL simulation verification scheme of the complex algorithm inevitably becomes huge and complicated. In particular, according to different application requirements, the same complex algorithm may adopt multiple implementation modes such as soft-hard coordination or pure hardware, so as to obtain more flexible application characteristics or achieve higher data throughput rate. The high complexity and diversified implementation modes greatly increase the difficulty of RTL simulation verification of the complex algorithm.
In order to realize complex algorithm verification (such as a deep learning algorithm, a public key algorithm and the like) of soft and hard coordination or pure hardware realization, the invention discloses a test excitation generator of a complex algorithm and a control method thereof, which can be suitable for test excitation generation of the complex algorithm of soft and hard coordination or pure hardware realization, can be applied to a traditional simulation verification structure based on Verilog/SystemVerilog or a simulation verification structure based on UVM methodology, effectively reduces simulation verification difficulty and improves quality and efficiency of complex algorithm verification.
Disclosure of Invention
The invention provides a test excitation generator of a complex algorithm, which can realize the test excitation generation of the complex algorithm by only adding one test excitation generator module on the basis of the original verification environment (a traditional simulation verification structure based on Verilog/SystemVerilog or a simulation verification structure based on UVM methodology); the complex algorithm test excitation generator is suitable for complex algorithm verification realized by soft and hard coordination or pure hardware, reduces simulation verification difficulty and improves verification quality of the complex algorithm.
The invention provides a control method of a test excitation generator of a complex algorithm, which realizes efficient generation and loading of test excitation and can improve the verification efficiency of the complex algorithm.
The invention provides a test excitation generator (100) of a complex algorithm, which consists of a fixed vector generation module (101), a random vector generation module (102), a special vector generation module (103), a time sequence monitoring module (104), a verification scheme input interface module (105), a time sequence signal input interface module (106) and a test excitation output interface module (107); the test excitation generation control signal is input to the test excitation generator (100) through the verification scheme input interface module (105), the test excitation generator (100) acquires a time sequence signal from the complex algorithm verification system (108) through the time sequence signal input interface module (106), the time sequence signal is used for controlling loading and verification starting of the test excitation after being processed by the time sequence monitoring module (104), and the test excitation generator (100) generates the test excitation and outputs the test excitation to the complex algorithm verification system (108) through the test excitation output interface module (107).
In a complex algorithm test stimulus generator (100), a fixed vector generation module (101) implements test stimulus generation of register reset values, register read-write attributes, and RAM read-write attributes.
In a complex algorithm test stimulus generator (100), a randomization mechanism of a random vector generation module (102) generates legal random data conforming to a complex algorithm input data format and illegal random data not conforming to a complex algorithm input data format by adopting a randomization command of SystemVerilog.
In a test stimulus generator (100) of a complex algorithm, a special vector generation module (103) has a complex algorithm operation function and can generate special stimulus conforming to complex operation characteristics.
In a complex algorithm test stimulus generator (100), a timing monitoring module (104) monitors timing signals of the complex algorithm module in real time and controls the loading process of the test stimulus.
In a complex algorithm test stimulus generator (100), a verification scheme input interface module (105) requires that an input verification scheme include at least a fixed vector, a random vector, and a special vector generation control signal.
In a complex algorithm test stimulus generator (100), a timing signal input interface module (106) is connected to a complex algorithm verification environment (108) by way of hierarchical access.
In a complex algorithm test stimulus generator (100), the test stimulus output interface module (107) outputs test stimulus in the form of a Task conforming to Verilog syntax or a Sequence conforming to UVM methodology.
According to another aspect of the present invention, a method of controlling a test stimulus generator of a complex algorithm is shown in FIG. 3.
Step S1: verification scheme analysis;
step S2: generating, loading and verifying a fixed vector;
step S3: random vector generation, loading and verification starting;
step S4: judging whether the data vector is a special data vector in the special vectors, if yes, jumping to the step S5, otherwise jumping to the step S6;
step S5: calling complex algorithm operation to generate a special data vector in the special vector;
step S6: judging whether the vector is a special time sequence vector in the special vectors, if yes, jumping to the step S7, otherwise jumping to the step S8;
step S7: initializing time sequence vector loading;
step S8: starting time sequence monitoring;
step S9: loading a special vector and starting verification;
step S10: the hybrid vector, which is randomly combined by the fixed vector, the random vector and the special vector, is loaded and verification is initiated.
Drawings
The test stimulus generator of the complex algorithm of fig. 1 is schematically structured.
Fig. 2 is a schematic diagram of an example application of the test stimulus generator of the complex algorithm in a UVM verification environment.
FIG. 3 is a schematic flow chart of a test stimulus generator control method of the complex algorithm.
Detailed Description
In order to more clearly describe the technical scheme of the invention, the invention is described in detail below with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, a test stimulus generator (100) of a complex algorithm is composed of a fixed vector generation module (101), a random vector generation module (102), a special vector generation module (103), a time sequence monitoring module (104), a verification scheme input interface module (105), a time sequence signal input interface module (106) and a test stimulus output interface module (107); the test excitation generation control signal is input to the test excitation generator (100) through the verification scheme input interface module (105), the test excitation generator (100) acquires a time sequence signal from the complex algorithm verification system (108) through the time sequence signal input interface module (106), the time sequence signal is used for controlling loading and verification starting of the test excitation after being processed by the time sequence monitoring module (104), and the test excitation generator (100) generates the test excitation and outputs the test excitation to the complex algorithm verification system (108) through the test excitation output interface module (107).
A complex algorithm test stimulus generator (100) is used to generate five complex algorithm test stimulus of a fixed vector sequence, a random vector sequence, a special data vector sequence, a special timing vector sequence, and a hybrid vector sequence.
As shown in fig. 2, the invention is applied on the basis of a classical UVM verification structure, and uses the verification of an SM2 signature verification operation implemented by cooperation of software and hardware as an example, and more specifically describes the application details of the complex algorithm test stimulus generator (100). (SM 2 signature verification operation can be decomposed into hash operation, dot multiplication operation and modular addition and subtraction operation, in this embodiment, the hash operation is realized by external software scheduling, dot multiplication and modular addition and subtraction operation is realized in an SM2 algorithm realization module (DUT), and the hash operation and dot multiplication operation are performed in parallel.
Step S1: the test excitation generator (100) acquires a verification scheme through the verification scheme input interface module (105), and analyzes the verification scheme to obtain generation control signals of fixed vectors, random vectors, special vectors and mixed vectors.
The timing signals of the SM2 algorithm implementation module (DUT) are transferred to the timing signal input Interface module (106) through the output Interface (O-Interface).
Step S2: and according to the fixed vector generation control signal, calling a fixed vector generation module (101) to generate a fixed vector of a reset value, a read-write attribute and a RAM read-write attribute of a special function register, outputting the fixed vector to a Sequence (Sequence) through a test excitation output interface module (107), controlling the loading process of the fixed vector according to the Sequence signal, and starting verification.
Step S3: according to the random vector generation control signal, a random vector generation module (102) is called to generate random signature data (r, s) and a hash value e, the combination probability of the signature data (r, s) and the hash value e is an illegal value, the signature data is output to a Sequence (Sequence) through a test excitation output interface module (107), and the loading process of the signature data is controlled and verification is started according to the time Sequence signal.
Step S4, S5: and (3) judging whether to generate a special data vector in the special vector according to the special vector generation control signal, if so, calling a special vector generation module (103), adopting an SM2 public-private key pair generation algorithm and an SM2 signature algorithm to obtain a legal public-private key pair, signature data (r, S) and a hash value e combination, and otherwise, jumping to a step S6.
Step S6, S7: and (3) judging whether a special time sequence vector in the special vectors is generated or not according to the special vector generation control signals, initializing the time sequence vector if the special time sequence vector is generated, and if the special time sequence vector is not generated, jumping to the step S8.
Step S8: and calling a time sequence monitoring module (104) to monitor an ending mark of the dot-multiplication operation in the SM2 signature verification operation process in real time so as to ensure that the hash value e is used after the dot-multiplication operation is ended and ensure the flow legality of the SM2 signature verification operation.
Step S9: the special vector is loaded and verification is initiated based on feedback from the timing monitor module (104).
Step S10: and loading fixed vectors, random vectors or special vectors according to the six combination modes of the mixed vectors, starting verification, covering all possible combination use modes in the SM2 signature verification operation process, and improving the verification coverage rate.
Claims (10)
1. A test stimulus generator for complex algorithms, comprising essentially: the test excitation generator (100) is composed of a fixed vector generation module (101), a random vector generation module (102), a special vector generation module (103), a time sequence monitoring module (104), a verification scheme input interface module (105), a time sequence signal input interface module (106) and a test excitation output interface module (107); the test excitation generation control signal is input to the test excitation generator (100) through the verification scheme input interface module (105), the test excitation generator (100) acquires a time sequence signal from the complex algorithm verification system (108) through the time sequence signal input interface module (106), the time sequence signal is used for controlling the loading and verification starting of the test excitation after being processed by the time sequence monitoring module (104), the test excitation generator (100) generates the test excitation and outputs the test excitation to the complex algorithm verification system (108) through the test excitation output interface module (107),
wherein, the test stimulus generator includes the following steps when in operation:
step S1: verification scheme analysis;
step S2: generating, loading and verifying a fixed vector;
step S3: random vector generation, loading and verification starting;
step S4: judging whether the data vector is a special data vector in the special vectors, if yes, continuing to step S5, otherwise, jumping to step S6;
step S5: calling complex algorithm operation to generate a special data vector in the special vector;
step S6: judging whether the vector is a special time sequence vector in the special vectors, if yes, continuing to step S7, otherwise, jumping to step S8;
step S7: initializing time sequence vector loading;
step S8: starting time sequence monitoring;
step S9: loading a special vector and starting verification;
step S10: the hybrid vector, which is randomly combined by the fixed vector, the random vector and the special vector, is loaded and verification is initiated.
2. The complex algorithm test stimulus generator of claim 1, wherein the fixed vector generation module (101) implements test stimulus generation of register reset values, register read-write attributes, and RAM read-write attributes.
3. The complex algorithm test stimulus generator of claim 1, wherein the randomization mechanism of the random vector generation module (102) employs a System Verilog randomization command to generate legal random data conforming to the complex algorithm input data format and illegal random data not conforming to the complex algorithm input data format.
4. The complex algorithm test stimulus generator of claim 1, characterized in that the special vector generation module (103) has a complex algorithm operation function, and is capable of generating special stimulus conforming to complex operation characteristics.
5. The complex algorithm test stimulus generator of claim 1, wherein the timing monitoring module (104) monitors timing signals of the complex algorithm module in real time and controls the loading process of the test stimulus.
6. A complex algorithm test stimulus generator as claimed in claim 1, characterized in that the verification scheme input interface module (105) requires that the input verification scheme comprises at least a fixed vector, a random vector and a special vector generation control signal.
7. A complex algorithm test stimulus generator as claimed in claim 1, characterized in that the timing signal input interface module (106) is connected to the complex algorithm verification system (108) by means of hierarchical access.
8. A complex algorithm test stimulus generator as claimed in claim 1, characterized in that the test stimulus output by the test stimulus output interface module (107) is in the form of a Task conforming to Verilog syntax or a Sequence conforming to UVM methodology.
9. A method for controlling a test stimulus generator of a complex algorithm, based on a test stimulus generator of a complex algorithm as claimed in claim 1, characterized in that the main steps comprise:
step S1: verification scheme analysis;
step S2: generating, loading and verifying a fixed vector;
step S3: random vector generation, loading and verification starting;
step S4: judging whether the data vector is a special data vector in the special vectors, if yes, continuing to step S5, otherwise, jumping to step S6;
step S5: calling complex algorithm operation to generate a special data vector in the special vector;
step S6: judging whether the vector is a special time sequence vector in the special vectors, if yes, continuing to step S7, otherwise, jumping to step S8;
step S7: initializing time sequence vector loading;
step S8: starting time sequence monitoring;
step S9: loading a special vector and starting verification;
step S10: the hybrid vector, which is randomly combined by the fixed vector, the random vector and the special vector, is loaded and verification is initiated.
10. The control method according to claim 9, wherein the random combination of the mixed vectors includes six kinds of fixed vector+random vector, fixed vector+special vector, random vector+fixed vector, random vector+special vector, special vector+fixed vector, special vector+random vector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910925904.8A CN110688821B (en) | 2019-09-27 | 2019-09-27 | Test excitation generator of complex algorithm and control method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910925904.8A CN110688821B (en) | 2019-09-27 | 2019-09-27 | Test excitation generator of complex algorithm and control method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110688821A CN110688821A (en) | 2020-01-14 |
| CN110688821B true CN110688821B (en) | 2023-10-13 |
Family
ID=69110697
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910925904.8A Active CN110688821B (en) | 2019-09-27 | 2019-09-27 | Test excitation generator of complex algorithm and control method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110688821B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112198423B (en) * | 2020-09-25 | 2023-04-25 | 杭州加速科技有限公司 | Test excitation generation unit in FPGA chip |
| CN113283211A (en) * | 2021-05-20 | 2021-08-20 | 复旦大学 | Microprocessor automatic verification method and verification device based on Verilog |
| CN113157269B (en) * | 2021-06-10 | 2023-11-17 | 上海齐感电子信息科技有限公司 | Verification system and verification method thereof |
Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6065106A (en) * | 1996-12-20 | 2000-05-16 | Texas Instruments Incorporated | Resuming normal execution by restoring without refetching instructions in multi-word instruction register interrupted by debug instructions loading and processing |
| AU727787B2 (en) * | 1996-11-26 | 2000-12-21 | Trw Inc. | Cochannel signal processing system |
| US6484135B1 (en) * | 1999-08-30 | 2002-11-19 | Hewlett-Packard Company | Method for adaptive test generation via feedback from dynamic emulation |
| WO2007009912A1 (en) * | 2005-07-15 | 2007-01-25 | Politecnico Di Torino | Method for testing analog-to-digital converters |
| CN101263499A (en) * | 2005-07-11 | 2008-09-10 | 布鲁克斯自动化公司 | Intelligent condition monitoring and fault diagnostic system |
| CN103700407A (en) * | 2013-12-14 | 2014-04-02 | 中国航空工业集团公司第六三一研究所 | Aviation application-based verification method for domestic storages |
| CN104486169A (en) * | 2015-01-07 | 2015-04-01 | 北京华力创通科技股份有限公司 | Reusable automatic detection and random verification system and method |
| CN104504187A (en) * | 2014-12-11 | 2015-04-08 | 安徽师范大学 | FPGA (Field Programmable Gate Array) online verification structure and method based on serial communication interface |
| CN105320583A (en) * | 2014-07-31 | 2016-02-10 | 上海华虹集成电路有限责任公司 | UVM (universal verification methodology) based write-only register verification test platform and verification method |
| CN106021037A (en) * | 2015-07-10 | 2016-10-12 | 北京中电华大电子设计有限责任公司 | Chip register automation simulation verification method based on technological manual extraction |
| CN106021044A (en) * | 2016-05-10 | 2016-10-12 | 中国电子科技集团公司第三十八研究所 | Reusable SPI (Serial Peripheral Interface) bus protocol module verification environment platform and verification method thereof |
| CN107908514A (en) * | 2017-11-15 | 2018-04-13 | 北京中电华大电子设计有限责任公司 | A kind of emulation verification method of power consumption adaptive circuit |
| CN107992675A (en) * | 2017-11-29 | 2018-05-04 | 中国电子科技集团公司第五十四研究所 | A kind of arbitration circuit test method of EDA Qualify Phases |
| CN109901999A (en) * | 2019-01-31 | 2019-06-18 | 国核自仪系统工程有限公司 | The emulation mode and system of programmable logic based on UVM |
| CN110046387A (en) * | 2019-03-14 | 2019-07-23 | 广东工业大学 | A kind of SM2 module verification platform and verification method based on UVM |
| CN110188885A (en) * | 2019-06-28 | 2019-08-30 | 合肥本源量子计算科技有限责任公司 | A kind of quantum calculation analogy method, device, storage medium and electronic device |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7164117B2 (en) * | 1992-05-05 | 2007-01-16 | Automotive Technologies International, Inc. | Vehicular restraint system control system and method using multiple optical imagers |
| US8073820B2 (en) * | 2008-04-07 | 2011-12-06 | Sonics, Inc. | Method and system for a database to monitor and analyze performance of an electronic design |
| US8584073B2 (en) * | 2008-07-21 | 2013-11-12 | Synopsys, Inc. | Test design optimizer for configurable scan architectures |
| US8104002B2 (en) * | 2009-01-28 | 2012-01-24 | Synopsys, Inc. | Performing logic optimization and state-space reduction for hybrid verification |
| WO2016106605A1 (en) * | 2014-12-30 | 2016-07-07 | 京微雅格（北京）科技有限公司 | Simulation verification method for fpga functional module and system thereof |
| US10176408B2 (en) * | 2015-08-14 | 2019-01-08 | Elucid Bioimaging Inc. | Systems and methods for analyzing pathologies utilizing quantitative imaging |
| US10007492B2 (en) * | 2015-10-21 | 2018-06-26 | Vayavya Labs Pvt. Ltd | System and method for automatically generating device drivers for run time environments |
| US20180004627A1 (en) * | 2016-06-29 | 2018-01-04 | Centipede Semi Ltd. | Sequential monitoring and management of code segments for run-time parallelization |
-
2019
- 2019-09-27 CN CN201910925904.8A patent/CN110688821B/en active Active
Patent Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU727787B2 (en) * | 1996-11-26 | 2000-12-21 | Trw Inc. | Cochannel signal processing system |
| US6065106A (en) * | 1996-12-20 | 2000-05-16 | Texas Instruments Incorporated | Resuming normal execution by restoring without refetching instructions in multi-word instruction register interrupted by debug instructions loading and processing |
| US6484135B1 (en) * | 1999-08-30 | 2002-11-19 | Hewlett-Packard Company | Method for adaptive test generation via feedback from dynamic emulation |
| CN101263499A (en) * | 2005-07-11 | 2008-09-10 | 布鲁克斯自动化公司 | Intelligent condition monitoring and fault diagnostic system |
| WO2007009912A1 (en) * | 2005-07-15 | 2007-01-25 | Politecnico Di Torino | Method for testing analog-to-digital converters |
| CN103700407A (en) * | 2013-12-14 | 2014-04-02 | 中国航空工业集团公司第六三一研究所 | Aviation application-based verification method for domestic storages |
| CN105320583A (en) * | 2014-07-31 | 2016-02-10 | 上海华虹集成电路有限责任公司 | UVM (universal verification methodology) based write-only register verification test platform and verification method |
| CN104504187A (en) * | 2014-12-11 | 2015-04-08 | 安徽师范大学 | FPGA (Field Programmable Gate Array) online verification structure and method based on serial communication interface |
| CN104486169A (en) * | 2015-01-07 | 2015-04-01 | 北京华力创通科技股份有限公司 | Reusable automatic detection and random verification system and method |
| CN106021037A (en) * | 2015-07-10 | 2016-10-12 | 北京中电华大电子设计有限责任公司 | Chip register automation simulation verification method based on technological manual extraction |
| CN106021044A (en) * | 2016-05-10 | 2016-10-12 | 中国电子科技集团公司第三十八研究所 | Reusable SPI (Serial Peripheral Interface) bus protocol module verification environment platform and verification method thereof |
| CN107908514A (en) * | 2017-11-15 | 2018-04-13 | 北京中电华大电子设计有限责任公司 | A kind of emulation verification method of power consumption adaptive circuit |
| CN107992675A (en) * | 2017-11-29 | 2018-05-04 | 中国电子科技集团公司第五十四研究所 | A kind of arbitration circuit test method of EDA Qualify Phases |
| CN109901999A (en) * | 2019-01-31 | 2019-06-18 | 国核自仪系统工程有限公司 | The emulation mode and system of programmable logic based on UVM |
| CN110046387A (en) * | 2019-03-14 | 2019-07-23 | 广东工业大学 | A kind of SM2 module verification platform and verification method based on UVM |
| CN110188885A (en) * | 2019-06-28 | 2019-08-30 | 合肥本源量子计算科技有限责任公司 | A kind of quantum calculation analogy method, device, storage medium and electronic device |
Non-Patent Citations (2)
| Title |
|---|
| 基于SV语言的802.11 MAC芯片逻辑验证方案;周卓;;现代电子技术(18);全文 * |
| 基于VMM的LDPC编译码器验证平台设计;李艳福;韩国军;方毅;穆丽伟;;通信技术(11);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110688821A (en) | 2020-01-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110688821B (en) | Test excitation generator of complex algorithm and control method thereof | |
| EP2260376B1 (en) | Digital random number generator based on digitally-controlled oscillators | |
| JP6556495B2 (en) | Secret information-based mutual authentication method and apparatus | |
| US8681976B2 (en) | System and method for device dependent and rate limited key generation | |
| US11567461B2 (en) | Method and device for controlling a technical system using a control model | |
| US20210406443A1 (en) | Verification platform for system on chip and verification method thereof | |
| CN105814833B (en) | Method and system for secure data transformation | |
| US20180097613A1 (en) | Encryption device and memory device | |
| CN200990081Y (en) | Computer hard disk data ciphering card | |
| JP2020521124A (en) | Integrated circuit test apparatus and method | |
| CN112906328A (en) | FPGA prototype verification system generation method and system and FPGA prototype verification method and system | |
| CN111814414A (en) | Coverage rate convergence method and system based on genetic algorithm | |
| US7366860B2 (en) | Storage device configured to sequentially input a command | |
| CN116193041A (en) | Image encryption method based on multistable memristor and four-dimensional chaotic neural network | |
| KR20110020153A (en) | Method and apparatus for processing f-function in seed encryption system | |
| CN110163231B (en) | Method for establishing image data identification model, computer system and recording medium | |
| CN109981251B (en) | Random number sequence compression method and device and electronic equipment | |
| CN114637704B (en) | Multi-interface excitation implementation method | |
| KR20210072711A (en) | Method and apparatus for mutual authentication between internet of things device and trusted server | |
| CN110543777A (en) | Image processing method, device, equipment and storage medium | |
| US7827417B2 (en) | Storage device | |
| CN115441984B (en) | Device, method and electronic equipment for suppressing electromagnetic radiation in signal line | |
| JPH07121357A (en) | System and device for generating parallel program system | |
| Henriksson | Implementation of a Hardware Coordinate Wise Descend Algorithm with Maximum Likelihood Estimator for Use in mMTC Activity Detection | |
| CN110889506A (en) | Method, device and system for generating quantum instruction and electronic device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |