CN112198423B - Test excitation generation unit in FPGA chip - Google Patents
Test excitation generation unit in FPGA chip Download PDFInfo
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- CN112198423B CN112198423B CN202011021891.0A CN202011021891A CN112198423B CN 112198423 B CN112198423 B CN 112198423B CN 202011021891 A CN202011021891 A CN 202011021891A CN 112198423 B CN112198423 B CN 112198423B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3177—Testing of logic operation, e.g. by logic analysers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/28—Provision in measuring instruments for reference values, e.g. standard voltage, standard waveform
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31718—Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a test excitation generating unit in an FPGA chip. The test stimulus generation unit includes: the excitation generation module is used for generating excitation signals or control signals required by the tested user logic unit; and the PCIE module is used for enabling the excitation generating module and the logic analysis module to communicate with an external computer. The test excitation generating unit can generate excitation signals or control signals required by the tested user logic unit in the FPGA chip, so that the excitation signals or control signals can be efficiently and flexibly provided for the tested user logic unit.
Description
Technical Field
The invention relates to the field of FPGA (field programmable gate array) chips, in particular to a test excitation generating unit in an FPGA chip.
Background
With the continuous development of scientific technologies such as 5G communication, internet of things, artificial intelligence, big data, cloud computing and the like, the requirements of the scientific industry on the computing capacity, the computing delay and the programmability of an integrated circuit are higher and higher. FPGAs are being widely used in various emerging technical fields due to their own high parallelism, low latency, high flexibility, high performance to power consumption ratio, and the like.
However, FPGA brings great challenges to the developer due to its technical and ecological imperfections, great difficulty in development, long development period, etc. Among these challenges, the problem of user functional logic testing links within FPGAs is particularly pronounced. Particularly in a cloud FPGA system and a remote FPGA system, the user function logic test is more difficult and heavy. One of the most difficult problems is the generation of logic test stimulus signals.
In the prior art, FPGA test stimulus signals are often provided through an external physical input interface. The signal quality and data correctness of the physical interface are limited by the external hardware environment, so that a great deal of time and effort must be expended to test whether the hardware external interface communication is correct before testing the FPGA user function logic. In addition, the input stimulus signal provided by the external interface is often limited by the external device and cannot be arbitrarily generated according to the demands of the logic function designer and the logic tester. Further, in the testing process of FPGA logic circuits, special control is often required for some special signals in order to facilitate problem localization. The traditional method can only control a small amount of signals in a VIO (virtual IO) mode, can only control the signals through external computer user software, has larger control delay, and cannot meet the control requirements of a large amount of signals or low-delay signals.
Accordingly, there is a need to provide a solution that can efficiently and flexibly provide stimulus signals for FPGA user functional logic testing.
Disclosure of Invention
In view of the above, the present invention provides a test stimulus generating unit in an FPGA chip, which can solve the above technical problems.
The technical scheme of the invention is as follows:
a test stimulus generation unit within an FPGA chip, comprising:
the excitation generation module is used for generating excitation signals or control signals required by the tested user logic unit;
and the PCIE module is used for enabling the excitation generating module to communicate with an external computer.
According to a preferred embodiment of the present invention, the stimulus generation module includes a vector buffer storing a plurality of vectors each including a period schedule address, an edge schedule address, edge data, a microinstruction, and microinstruction parameters, an edge schedule, an instruction execution unit configured to generate the stimulus signal or the control signal at the interface timing generation unit by reading and executing the vector buffer, the period schedule, and the edge schedule.
According to a preferred embodiment of the present invention, the interface timing generation unit is configured to input the stimulus signal to an input signal interface of the user logic unit under test or to input the control signal to a test signal interface of the user logic unit under test.
According to a preferred embodiment of the present invention, the PCIE module includes a PCIE IP interface, a DMA write interface, and a DMA read interface, where the PCIE IP interface is used for communicating with an external computer, the DMA write interface is used for writing vector data and configuration data to the excitation generating module, and the DMA read interface is used for reading data from the excitation generating module.
According to a preferred embodiment of the invention, the configuration data comprises cycle time data for writing to a cycle schedule and edge time data for writing to an edge schedule.
An FPGA chip includes a user logic unit under test and the test stimulus generation unit described above.
According to a preferred embodiment of the present invention, the FPGA chip further comprises a selection circuit and a configuration register, the selection circuit being configured to select, under control of the configuration register, an external physical interface or an excitation signal generated by the excitation generation module as an input to the tested user logic unit.
According to a preferred embodiment of the present invention, the PCIE module further includes a register interface configured to set the configuration register.
According to the technical scheme, the test excitation generating unit can generate excitation signals and control signals required by the tested user logic unit in the FPGA chip, so that the excitation signals or the control signals can be provided for the tested user logic unit efficiently and flexibly.
Drawings
The present disclosure will become more readily understood with reference to the accompanying drawings. It is to be understood by those skilled in the art that these drawings are for illustrative purposes only and are not intended to limit the scope of the present invention. In the figure:
FIG. 1 is a schematic diagram of the internal structure of an FPGA chip in the prior art;
FIG. 2 is a schematic diagram of the structure of the inside of a FGPA chip according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating vector data in a vector cache according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a periodic schedule according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of an edge schedule according to an embodiment of the invention;
fig. 6 is a schematic diagram of the excitation signal generation principle according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings and specific embodiments.
Fig. 1 is a schematic diagram of the internal structure of an FPGA chip in the prior art. As shown in fig. 1, the FPGA chip includes a user function logic unit therein. The user function logic unit includes an input signal interface, a test signal interface, and an output signal interface. The input signal interface and the output signal interface are respectively connected with the physical interface of the FPGA chip. The test signal interface is connected with an external computer through a JTAG interface. In the prior art, an excitation signal for testing a user function logic unit is input from the outside of the FPGA chip through a physical interface. The output signal generated by the user function logic unit is output to the external analysis equipment for analysis through the physical interface. Some control signals for simple testing may be generated by VIO (virtual pin) technology provided by EDA vendors and input to the test signal interface through the JTAG interface. As described in the background section, the prior art does not provide for efficient and flexible provision of test stimulus signals to user function logic.
Fig. 2 is a schematic diagram of the structure of the inside of a FGPA chip according to an embodiment of the present invention. As shown in FIG. 2, the FPGA chip comprises a test stimulus generation unit and a tested user logic unit. The test stimulus generation unit includes: an excitation generation module and a PCIE module. The excitation generation module is used for generating excitation signals and control signals required by the tested user logic unit. The PCIE module is used as an interface for external communication of the test excitation generating unit and is used for enabling the excitation generating module to communicate with an external computer. The tested user logic unit comprises an input signal interface, a test signal interface and an output signal interface. The FPGA chip may also include selection circuitry and configuration registers. The selection circuit is configured to select the external physical interface or the stimulus signal generated by the stimulus generation module as an input signal to the tested user logic unit under control of the configuration register.
The test excitation generating unit is positioned in the chip of the FPGA, so that excitation signals or control signals can be efficiently and flexibly provided for the tested user logic unit from the inside of the FPGA chip, and the excitation signals or control signals are not required to be introduced from the outside of the FPGA chip, thereby avoiding the problems caused by the introduction of the excitation signals or the control signals from the outside in the prior art.
According to an embodiment of the invention, the stimulus generation module comprises a vector cache, a period schedule, an edge schedule, an instruction execution unit, and an interface timing generation unit. The vector cache stores a plurality of vectors, each vector including a cycle schedule address, an edge schedule address, edge data, a microinstruction, and a microinstruction parameter. The instruction execution unit generates the excitation signal and the control signal at the interface timing generation unit by reading the vector buffer, the cycle schedule, and the edge schedule. The interface timing unit may be directly connected to the input signal interface of the tested user logic unit, or may be connected to the input signal interface of the tested user logic unit through a selection circuit, so as to provide an excitation signal for the tested user logic unit. In addition, the interface time sequence generating unit is also connected with the test signal interface of the tested user logic unit and used for providing control signals for the tested user logic unit. The output signal of the tested user logic unit can be output to external equipment or special equipment through a physical interface so as to analyze the logic correctness of the output signal. In addition, the internal signals output by the test signal interface of the tested user logic unit can be grasped by a logic analyzer tool (such as a chiprope tool of Xilinx company or a SignalTap tool of Intel company) provided by an FPGA factory for analysis.
According to the embodiment of the invention, the PCIE module comprises a PCIE IP interface, a DMA write interface and a DMA read interface. The PCIE IP interface is used for communicating with an external computer. The DMA write interface is for writing vector data and configuration data to the stimulus generation module. The DMA read interface is for reading data from the stimulus generation module. The configuration data includes cycle time data for writing to the cycle schedule and edge time data for writing to the edge schedule. The PCIE module may further include a register interface for setting configuration registers.
The structures of the FPGA chip and the test stimulus generating unit according to the embodiment of the present invention are described above. The manner in which the excitation or control signals are generated will be described in detail below in connection with fig. 3-6.
FIG. 3 is a diagram illustrating vector data in a vector cache according to an embodiment of the present invention. As shown in fig. 3, a plurality of vectors for generating the excitation signal or the control signal are stored in the vector buffer. Each vector includes a cycle schedule address, an edge schedule address, edge data, a microinstruction, and microinstruction parameters. The cycle time data may be obtained from the cycle time table by a cycle time table address. With the edge schedule address, edge time data can be obtained from the edge schedule. The microinstructions are used to control the order, number of times, cadence, conditions, etc. of vector execution. The micro instruction parameters are the execution parameters required to execute the micro instruction. The instruction execution unit may obtain cycle time data, edge data, micro instructions and micro instruction parameters by reading the vector in the vector cache, execute the micro instructions, and generate the excitation signal or the control signal at the interface timing generation unit. Some general micro instructions and corresponding instruction parameters according to embodiments of the invention are listed in table 1. The generation of the excitation signal or the control signal may be controlled by a micro instruction.
TABLE 1
Fig. 4 is a schematic diagram of a periodic schedule according to an embodiment of the present invention. As shown in fig. 4, 256 waveform periods are stored in the period schedule according to an embodiment of the present invention. One period in the period schedule may be designated as the period of the excitation signal or the control signal by the period schedule address in the vector.
Fig. 5 is a schematic diagram of an edge schedule according to an embodiment of the invention. As shown in fig. 5, 256 kinds of edge information, each including 8 pieces of edge time information, are stored in the edge schedule according to the embodiment of the present invention. One type of edge information in the edge schedule may be designated as edge information of the excitation signal or the control signal by an edge schedule address in the vector.
Fig. 6 is a schematic diagram of the excitation signal generation principle according to the present invention. As shown in fig. 6, the generated signal (i.e., the excitation signal or the control signal) is defined by a period T (32 clock cycles), 8 edge moments (3, 6, 8, 11, 17, 23, 28, and 31 clock cycles), and 8 edge data (10010110) with reference to the clock signal. The period T may be obtained from the period schedule using the period schedule address in the vector. The 8 edge times can be obtained from the edge schedule using the edge schedule addresses in the vector. 8 edge data (i.e. signal values at 8 edge instants) can be obtained from the vector. By combining the above information with the microinstruction and microinstruction parameters, an excitation signal or control signal may be generated at the interface timing generation unit.
When the excitation signal or the control signal needs to be changed, an external computer can be used for writing a new vector into the vector cache through a DMA write interface in the PCIE module, so that the excitation generation module generates a new excitation signal and/or control signal according to the new vector. In addition, the user can also write new cycle time data and/or edge time data into the cycle time table and/or the edge time table through the DMA write interface in the PCIE module by using an external computer, so that alternative cycle time and edge time are changed.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the invention.
Claims (7)
1. A test stimulus generation unit within an FPGA chip, comprising:
the excitation generation module is used for generating excitation signals or control signals required by the tested user logic units in the FPGA chip;
and a PCIE module configured to cause the excitation generation module to communicate with a computer external to the FPGA chip, wherein the excitation generation module includes a vector buffer storing a plurality of vectors each including a cycle schedule address, an edge schedule address, edge data, a microinstruction, and a microinstruction parameter, a cycle schedule, an edge schedule, an instruction execution unit configured to generate the excitation signal or the control signal at the interface timing generation unit by reading the vector buffer, the cycle schedule, and the edge schedule, and executing the microinstruction.
2. The test stimulus generation unit of claim 1, wherein the interface timing generation unit is configured to input the stimulus signal to an input signal interface of the user logic unit under test or to input the control signal to a test signal interface of the user logic unit under test.
3. The test stimulus generation unit of claim 1 or 2, wherein the PCIE module comprises a PCIE ip interface for communicating with an external computer, a DMA write interface for writing vector data and configuration data to the stimulus generation module, and a DMA read interface for reading data from the stimulus generation module.
4. A test stimulus generating unit according to claim 3, characterized in that the configuration data comprises cycle time data for writing to a cycle schedule and edge time data for writing to an edge schedule.
5. An FPGA chip, characterized in that it comprises a user logic unit under test and a test stimulus generating unit according to any of claims 1 to 4.
6. The FPGA chip of claim 5, further comprising a selection circuit and a configuration register, the selection circuit configured to select an external physical interface or an excitation signal generated by the excitation generation module as an input to the tested subscriber logic unit under control of the configuration register.
7. The FPGA chip of claim 6, wherein the PCIE module further comprises a register interface for setting the configuration registers.
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| CN113721136A (en) * | 2021-07-20 | 2021-11-30 | 天津津航计算技术研究所 | FPGA-based synchronous 422 interface test excitation implementation system and method |
| CN115078968A (en) * | 2022-06-15 | 2022-09-20 | 上海类比半导体技术有限公司 | Chip test circuit, self-test chip and chip test system |
| CN117289114A (en) * | 2023-10-10 | 2023-12-26 | 苏州异格技术有限公司 | Logic function test circuit and test method |
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