CN113721136A - FPGA-based synchronous 422 interface test excitation implementation system and method - Google Patents
FPGA-based synchronous 422 interface test excitation implementation system and method Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
Abstract
A test excitation implementation system and method based on synchronous 422 interface of FPGA, the system includes synchronous 422 interface data excitation source sending equipment and FPGA system; the FPGA system comprises a synchronous 422 interface protocol data excitation generator and an excitation source selection control module; connecting the synchronous 422 interface data excitation source sending equipment to an excitation source selection control module through a clock line and a data line through a level matching circuit; the synchronous 422 interface protocol data excitation generator is connected to the excitation source selection control module through a clock line and a data line; the invention realizes that suitable excitation sources are selected at different development stages, thereby improving the project development efficiency and also improving the development efficiency of the synchronous 422 interface receiving function module system based on the FPGA.
Description
Technical Field
The invention belongs to the field of digital chip testing. Through a test excitation implementation system, test excitation of a synchronous 422 interface developed based on an FPGA is achieved.
Background
The FPGA is a field programmable gate array, and is a product further developed on the basis of programmable devices such as PAL, GAL, CPLD and the like. The FPGA is used as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), thereby not only solving the defects of the custom circuit, but also overcoming the defect that the number of gate circuits of the original programmable device is limited. The FPGA is adopted to design a circuit, a user can obtain a shared chip without sheet production, and the FPGA is one of devices with the shortest design period, the lowest development cost and the smallest risk in an ASIC circuit.
The sync 422 standard is a modified version of RS-232, and is collectively referred to as "the electrical characteristics of the balanced voltage digital interface circuit". It uses the voltage difference between two wires to represent a logic level, commonly referred to as a twisted pair. It is a balanced transmission and any noise or interference affects each of the two twisted pairs simultaneously, but the difference between these is of little influence, a phenomenon known as common mode rejection. Therefore, synchronization 422 can transmit data at a faster speed over a longer distance, and the interference resistance is much stronger than that of unbalanced transmission modes such as RS-232 and SPI. The maximum transmission distance is about 1200m, and the maximum transmission speed can reach 10 Mb/s. Since the synchronization 422 standard only specifies the voltage standard without specific implementation details, the data transmission is usually implemented by: two signal lines, one serial clock line and one serial data line are used. The data transmitting side drives the two signals, and the data receiving side samples the data signal. The concrete implementation is as follows: the data sending party drives the clock lines, and drives the data of 1bit on the data lines to be effective and continue to the next rising edge of the clock at the rising edge of each clock; the data receiving part uses the clock line as a sampling clock synchronous sampling data line, and the data is sampled and stored at each rising edge of the clock.
When the receiving function of the synchronous 422 interface is developed by using the FPGA, the synchronous 422 data sending equipment is generally used for testing in the development stage, and whether the design function meets the expectation or not is judged according to the response of a corresponding test stimulus through the designed synchronous 422 interface receiving module, so that the iterative modification of the design function is completed. However, in the development stage, the synchronous 422 interface test stimulus is often needed to be generated quickly and conveniently, and the use of external equipment to generate the stimulus has inconvenience in the design and development stage, a synchronous 422 level matching channel circuit needs to be designed on an external circuit board of the FPGA in advance, and in the initial stage of a project, when the synchronous 422 level matching circuit is designed or has defects, the synchronous 422 interface receiving function cannot be performed effectively, so that the stage development progress of the project is influenced.
Disclosure of Invention
The technical problem solved by the invention is as follows: the system for realizing the test excitation of the synchronous 422 interface based on the FPGA overcomes the defects of the prior art, a data excitation generator with a synchronous 422 interface protocol is designed in the FPGA, and an internal channel switch is designed to select and switch an excitation source received by a synchronous 422 interface receiving function module. When the FPGA external synchronization 422 data excitation source sending related circuit or equipment is not ready, the configuration channel selection switch selects to connect the excitation signal of the FPGA internal synchronization 422 data excitation generator to the input end of the synchronization 422 interface receiving function module. When the related circuits and equipment for sending the FPGA external synchronization 422 data excitation source are ready in the later period, the configuration channel selection switch selects to connect the excitation signal of the FPGA external synchronization 422 data excitation source sending equipment to the input end of the synchronization 422 interface receiving function module. The invention realizes that suitable excitation sources are selected at different development stages, thereby improving the project development efficiency. The invention can improve the development efficiency of the synchronous 422 interface receiving function module system based on the FPGA.
The technical scheme of the invention is as follows: a test excitation implementation system of a synchronous 422 interface based on an FPGA comprises synchronous 422 interface data excitation source sending equipment and an FPGA system; the FPGA system comprises a synchronous 422 interface protocol data excitation generator and an excitation source selection control module;
connecting the synchronous 422 interface data excitation source sending equipment to an excitation source selection control module through a clock line and a data line through a level matching circuit; the synchronous 422 interface protocol data excitation generator is connected to the excitation source selection control module through a clock line and a data line;
when the synchronous 422 interface data excitation generator works, synchronous 422 interface data excitation source sending equipment or a synchronous 422 interface protocol data excitation generator is selected to be accessed through an excitation source selection control module according to actual requirements, and the synchronous 422 interface protocol data excitation generator realizes excitation of an excitation clock and a data configurable synchronous 422 interface; if the excitation source channel selects synchronous 422 interface data excitation source sending equipment, the system sends the clock and data of the synchronous 422 interface data excitation source sending equipment passing through the level matching circuit to the output end; if the excitation source channel selects the synchronous 422 interface protocol data excitation generator, the system outputs the clock and data generated by the synchronous 422 interface data excitation generator to the output port.
The synchronous 422 interface protocol data excitation generator comprises a CPU, a rate configuration module, a data sending module, a high-speed clock, a clock frequency divider and a parallel-to-serial module.
A test excitation implementation method of a synchronous 422 interface based on an FPGA comprises the following steps:
1) selecting an excitation source sending device or a synchronous 422 interface protocol data excitation generator accessed to a synchronous 422 interface data excitation source through an excitation source selection control module according to actual requirements;
2) if synchronous 422 interface data excitation source sending equipment is selected, executing steps 3) -4); if the synchronous 422 interface protocol data excitation generator is selected, executing the steps 5) -12)
3) The synchronous 422 interface data excitation source sending equipment sends a test clock and data test excitation to the level matching circuit;
4) the level matching circuit converts the clock and the test excitation signal level into a level suitable for the FPGA and sends the level to an output end;
5) writing speed information and test data of test excitation at a computer end;
6) the computer sends the rate configuration information and the test data to the CPU through the JTAG line;
7) the CPU sends the rate configuration information to the rate configuration module to complete rate configuration, and the CPU sends the test data to the data sending module;
8) the rate configuration module converts the rate information into a frequency division coefficient of the clock frequency divider and outputs the frequency division coefficient to the clock frequency divider;
9) the clock frequency divider divides the frequency of the clock generated by the high-speed clock module according to the input frequency division coefficient, one path of the clock is output, and the other path of the clock is sent to the parallel-to-serial module;
10) the data transmission module converts the received test data sent by the CPU into data with specified bit width and sends the data to the parallel-to-serial module;
11) the parallel-to-serial module converts the received test data into 1bit serial data according to the clock output by the clock frequency divider;
12) the system sends the clock and data of the synchronous 422 interface data stimulus generator to the output port.
Compared with the prior art, the invention has the advantages that:
1. and proper excitation sources are selected at different development stages, so that the development efficiency is improved. In the prior art, the existing synchronous 422 interface data stimulus source sending equipment is generally adopted, and the synchronous 422 test stimulus is realized through a level matching circuit. The invention provides two excitation sources, which can select different excitations according to requirements;
2. the synchronization 422 is flexible in rate configuration of the test stimulus. The prior art typically employs existing synchronous 422 interface data stimulus source transmission devices, which typically provide a limited range of rates. In the synchronous 422 interface protocol data excitation generator, the rate configuration is sent to the rate configuration module by the computer through the CPU, the rate which can be supported by the rate configuration module is determined by a developer, and the rate configuration is flexible;
3. the data configuration of the synchronous 422 test stimulus is flexible. The prior art typically employs existing synchronous 422 interface data stimulus source transmitting devices, which typically provide limited forms of data. The synchronous 422 interface protocol data excitation generator in the invention, data is sent to the data sending module by the computer through the CPU, the test data is decided by the developer, and the test data configuration is flexible.
4. The system of the invention designs a data excitation generator with a synchronous 422 interface protocol in the FPGA, selects and switches the excitation source received by the synchronous 422 interface receiving function module through an internal channel switch, can switch between the FPGA external synchronous 422 data excitation source sending equipment and the FPGA internal synchronous 422 data excitation generator, and selects a proper excitation source at different development stages of a project, thereby improving the project development efficiency.
Drawings
Fig. 1 is a block diagram of a test stimulus implementation system of a synchronous 422 interface before improvement.
Fig. 2 is a block diagram of a test stimulus implementation system of the improved synchronization 422 interface.
Fig. 3 is a block diagram of a synchronous 422 interface protocol data stimulus generator.
Detailed Description
Fig. 1 shows a system for implementing test stimulus for a synchronous 422 interface before improvement.
The system before improvement:
the synchronous 422 interface data excitation source sending equipment sends a test clock and data test excitation;
the level matching circuit converts the clock and the test excitation signal level into the level suitable for the FPGA to output.
Fig. 2 is a block diagram of an implementation block diagram of a synchronous 422 interface protocol data stimulus generator in a dashed box, which is a modified test stimulus implementation method for a synchronous 422 interface shown in fig. 3.
The improved system comprises:
a test excitation implementation system of a synchronous 422 interface based on an FPGA comprises synchronous 422 interface data excitation source sending equipment and an FPGA system; the FPGA system comprises a synchronous 422 interface protocol data excitation generator and an excitation source selection control module;
connecting the synchronous 422 interface data excitation source sending equipment to an excitation source selection control module through a clock line and a data line through a level matching circuit; the synchronous 422 interface protocol data excitation generator is connected to the excitation source selection control module through a clock line and a data line;
when the synchronous 422 interface data excitation generator works, synchronous 422 interface data excitation source sending equipment or a synchronous 422 interface protocol data excitation generator is selected to be accessed through an excitation source selection control module according to actual requirements, and the synchronous 422 interface protocol data excitation generator realizes excitation of an excitation clock and a data configurable synchronous 422 interface; if the excitation source channel selects synchronous 422 interface data excitation source sending equipment, the system sends the clock and data of the synchronous 422 interface data excitation source sending equipment passing through the level matching circuit to the output end; if the excitation source channel selects the synchronous 422 interface protocol data excitation generator, the system outputs the clock and data generated by the synchronous 422 interface data excitation generator to the output port.
The improved method comprises the following steps:
1) selecting an excitation source sending device or a synchronous 422 interface protocol data excitation generator accessed to a synchronous 422 interface data excitation source through an excitation source selection control module according to actual requirements;
2) if synchronous 422 interface data excitation source sending equipment is selected, executing steps 3) -4); if the synchronous 422 interface protocol data excitation generator is selected, executing the steps 5) -12)
3) The synchronous 422 interface data excitation source sending equipment sends a test clock and data test excitation to the level matching circuit;
4) the level matching circuit converts the clock and the test excitation signal level into a level suitable for the FPGA and sends the level to an output port;
5) writing speed information and test data of test excitation at a computer end;
6) the computer sends the rate configuration information and the test data to the CPU through the JTAG line;
7) the CPU sends the rate configuration information to the rate configuration module to complete rate configuration, and the CPU sends the test data to the data sending module;
8) the rate configuration module converts the rate information into a frequency division coefficient of the clock frequency divider and outputs the frequency division coefficient to the clock frequency divider;
9) the clock frequency divider divides the frequency of the clock generated by the high-speed clock module according to the input frequency division coefficient, one path of the clock is output, and the other path of the clock is sent to the parallel-to-serial module;
10) the data transmission module converts the received test data sent by the CPU into data with specified bit width and sends the data to the parallel-to-serial module;
11) the parallel-to-serial module converts the received test data into 1bit serial data according to the clock output by the clock frequency divider;
12) the system sends the clock and data of the synchronous 422 interface data stimulus generator to the output port.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make modifications and variations of the present invention without departing from the spirit and scope of the present invention.
Claims (5)
1. The utility model provides a test excitation implementation system of synchronous 422 interface based on FPGA which characterized in that: the method comprises synchronous 422 interface data excitation source sending equipment and an FPGA system; the FPGA system comprises a synchronous 422 interface protocol data excitation generator and an excitation source selection control module;
connecting the synchronous 422 interface data excitation source sending equipment to an excitation source selection control module through a clock line and a data line through a level matching circuit; the synchronous 422 interface protocol data excitation generator is connected to the excitation source selection control module through a clock line and a data line;
when the synchronous 422 interface data excitation generator works, synchronous 422 interface data excitation source sending equipment or a synchronous 422 interface protocol data excitation generator is selected to be accessed through an excitation source selection control module according to actual requirements, and the synchronous 422 interface protocol data excitation generator realizes excitation of an excitation clock and a data configurable synchronous 422 interface; if the excitation source channel selects synchronous 422 interface data excitation source sending equipment, the system sends the clock and data of the synchronous 422 interface data excitation source sending equipment passing through the level matching circuit to the output end; if the excitation source channel selects the synchronous 422 interface protocol data excitation generator, the system outputs the clock and data generated by the synchronous 422 interface data excitation generator to the output port.
2. The system according to claim 1, wherein the system comprises: the synchronous 422 interface protocol data excitation generator comprises a CPU, a rate configuration module, a data transmission module and a high-speed clock.
3. The system according to claim 2, wherein the system comprises: the synchronous 422 interface protocol data stimulus generator also includes a clock divider and a parallel to serial module.
4. A test excitation implementation method of a synchronous 422 interface based on an FPGA is characterized by comprising the following steps:
1) selecting an excitation source sending device or a synchronous 422 interface protocol data excitation generator accessed to a synchronous 422 interface data excitation source through an excitation source selection control module according to actual requirements;
2) if synchronous 422 interface data excitation source sending equipment is selected, executing step 3); if the synchronous 422 interface protocol data excitation generator is selected, executing the step 5);
3) the synchronous 422 interface data excitation source sending equipment sends a test clock and data test excitation to the level matching circuit;
4) the level matching circuit converts the clock and the test excitation signal level into a level suitable for the FPGA and sends the level to an output end;
5) writing speed information and test data of test excitation at a computer end;
6) the computer sends the rate configuration information and the test data to the CPU through the JTAG line;
7) the CPU sends the rate configuration information to the rate configuration module to complete rate configuration, and the CPU sends the test data to the data sending module;
8) the rate configuration module converts the rate information into a frequency division coefficient of the clock frequency divider and outputs the frequency division coefficient to the clock frequency divider;
9) the clock frequency divider divides the frequency of the clock generated by the high-speed clock module according to the input frequency division coefficient, one path of the clock is output, and the other path of the clock is sent to the parallel-to-serial module;
10) the data transmission module converts the received test data sent by the CPU into data with specified bit width and sends the data to the parallel-to-serial module;
11) the parallel-to-serial module converts the received test data into 1bit serial data according to the clock output by the clock frequency divider;
12) the system sends the clock and data of the synchronous 422 interface data stimulus generator to the output port.
5. A storage medium, characterized by: used for storing the test stimulus implementation program; the test stimulus implementation procedure is the steps recited in steps 1) -12) of claim 4.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105337914A (en) * | 2015-09-30 | 2016-02-17 | 许继集团有限公司 | Asynchronous serial communication receiving method based on 1B4B coding and protection device |
| CN106713280A (en) * | 2016-11-30 | 2017-05-24 | 北京得瑞领新科技有限公司 | Excitation signal processing method and device, and module verification system |
| CN206348634U (en) * | 2016-12-30 | 2017-07-21 | 甘肃交通职业技术学院 | A kind of Multipath digital quantity acquisition process board based on FPGA |
| CN111277248A (en) * | 2020-04-03 | 2020-06-12 | 中国科学院近代物理研究所 | Multi-working-mode synchronous pulse generating device and working method thereof |
| CN112198423A (en) * | 2020-09-25 | 2021-01-08 | 杭州加速科技有限公司 | Test excitation generating unit in FPGA chip |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105337914A (en) * | 2015-09-30 | 2016-02-17 | 许继集团有限公司 | Asynchronous serial communication receiving method based on 1B4B coding and protection device |
| CN106713280A (en) * | 2016-11-30 | 2017-05-24 | 北京得瑞领新科技有限公司 | Excitation signal processing method and device, and module verification system |
| CN206348634U (en) * | 2016-12-30 | 2017-07-21 | 甘肃交通职业技术学院 | A kind of Multipath digital quantity acquisition process board based on FPGA |
| CN111277248A (en) * | 2020-04-03 | 2020-06-12 | 中国科学院近代物理研究所 | Multi-working-mode synchronous pulse generating device and working method thereof |
| CN112198423A (en) * | 2020-09-25 | 2021-01-08 | 杭州加速科技有限公司 | Test excitation generating unit in FPGA chip |
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