CN216622463U - Test fixture for PCIe signal consistency test - Google Patents
Test fixture for PCIe signal consistency test Download PDFInfo
- Publication number
- CN216622463U CN216622463U CN202123239401.7U CN202123239401U CN216622463U CN 216622463 U CN216622463 U CN 216622463U CN 202123239401 U CN202123239401 U CN 202123239401U CN 216622463 U CN216622463 U CN 216622463U
- Authority
- CN
- China
- Prior art keywords
- pcie
- signal
- signals
- impedance matching
- multiplexer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The utility model provides a test fixture for PCIe signal conformance test, comprising: the signal connector is used for inputting N paths of PCIe signals to be tested, and the N paths of PCIe signals are transmitted to the specification test points of the N paths of PCIe signals; the signal selection circuit is used for selecting one PCIe signal from the N PCIe signals and outputting the PCIe signal to the SMP differential interface; the 2N impedance matching circuits are connected with the DP signals and the DN signals to which the N paths of PCIe signals belong in a one-to-one correspondence mode and are used for realizing impedance matching of the DP signals and the DN signals to which the N paths of PCIe signals belong; and the control circuit is used for sending control signals to the signal selection circuit and the 2N impedance matching circuits so as to enable the signal selection circuit to select one path of PCIe signals and enable the impedance matching circuits connected with other paths of PCIe signals except the path of PCIe signals.
Description
Technical Field
The utility model relates to the technical field of PCIe testing, in particular to a test fixture for PCIe signal consistency testing.
Background
With the rapid development of the information age, people have higher and higher requirements on the information processing speed, and the speed of signal transmission between chips is higher and higher, so that the correctness of signal transmission is very important, and meanwhile, because the demand of the chips is higher and higher, the number of signals to be tested is larger, and the high efficiency and the practicability of the test are more and more emphasized on the premise of ensuring the correctness. Currently, a consistency test (Compliance test) for PCIe (peripheral component interconnect express) signals is performed by using a test fixture provided by the PCIe association. When the test of the next link is performed after one link is tested by using the existing test fixture, the connecting wire needs to be pulled out from the SMP interface (totally called SMP series radio frequency coaxial interface) of the previous link, the impedance matching terminal needs to be pulled out from the SMP interface to be tested at the same time, and then the connecting wire and the impedance matching terminal are connected in an exchange manner. That is to say, to complete the test of one link, the connection line and the impedance matching terminal need to be plugged and unplugged twice respectively, taking the test of PCIe X8 signal as an example, since PCIe is a differential signal, and there are two connection lines in each link, it is necessary to plug and unplugg the connection line and the impedance matching terminal 32 times to complete one X8 test, and power-off operation is required during plugging and unplugging, the time consumed for restarting the chip system is serious, plugging and unplugging are frequent, and the connector joint is very easily damaged.
SUMMERY OF THE UTILITY MODEL
In order to solve the problems, the utility model provides a test fixture for testing the consistency of PCIe signals, which can realize the automatic test of the PCIe signals, improve the test efficiency and protect the connector joint.
The utility model provides a test fixture for PCIe signal consistency test, comprising:
the signal connector is used for inputting N paths of PCIe signals to be tested, N is more than or equal to 2, each path of PCIe signal is a differential signal comprising a DP signal and a DN signal, and the N paths of PCIe signals are transmitted to respective specification test points of the N paths of PCIe signals;
the input end of the signal selection circuit is connected to the specification test point of the N paths of PCIe signals, and the output end of the signal selection circuit is connected to the SMP differential interface and is used for selecting one path of PCIe signal from the N paths of PCIe signals and outputting the PCIe signal to the SMP differential interface;
2N impedance matching circuits which are connected with the DP signals and the DN signals to which the N PCIe signals belong in a one-to-one correspondence manner, wherein every two impedance matching circuits form a group, and any one group of impedance matching circuits is used for realizing impedance matching of the DP signals and the DN signals to which the one PCIe signal belongs;
and the control circuit is used for sending control signals to the signal selection circuit and the 2N impedance matching circuits so that the signal selection circuit selects one path of PCIe signals and enables the impedance matching circuits connected with other paths of PCIe signals except the path of PCIe signals.
Optionally, the specification test point satisfies a condition: the insertion loss of the link with the signal connector is 8 dB.
Optionally, the signal selection circuit comprises:
and the PCIe signal multiplexers are connected in series and used for selecting one path of PCIe signals from the multiple paths of input PCIe signals to output according to the channel selection signals sent by the control circuit.
Optionally, if 16 PCIe signals are inputted, the signal selection circuit comprises a first PCIe signal multiplexer, a second PCIe signal multiplexer, a third PCIe signal multiplexer, a fourth PCIe signal multiplexer and a fifth PCIe signal multiplexer,
the first PCIe signal multiplexer is used for receiving 8 PCIe signals of the 16 PCIe signals and selectively outputting 4 PCIe signals;
the second PCIe signal multiplexer is used for receiving the other 8 PCIe signals of the 16 PCIe signals and selectively outputting 4 PCIe signals;
the third PCIe signal multiplexer is used for receiving 8 routes of PCIe signals selectively output by the first PCIe signal multiplexer and the second PCIe signal multiplexer and further selectively outputting 4 routes of PCIe signals;
the fourth PCIe signal multiplexer is used for receiving the 4 paths of PCIe signals selectively output by the third PCIe signal multiplexer and further selectively outputting 2 paths of PCIe signals;
and the fifth PCIe signal multiplexer is used for receiving the 2-path PCIe signal selectively output by the fourth PCIe signal multiplexer and further selectively outputting the 1-path PCIe signal.
Optionally, the first PCIe signal multiplexer, the second PCIe signal multiplexer, and the third PCIe signal multiplexer are 8-to-4-way PCIe signal multiplexers.
Optionally, the fourth PCIe signal multiplexer and the fifth PCIe signal multiplexer are 4-to-2-way PCIe signal multiplexers.
Optionally, the impedance matching circuit is a 50 ohm impedance matching circuit.
Optionally, the 50 ohm impedance matching circuit includes an MOS transistor and a ground resistor, a signal of a DP signal or a DN signal to which a PCIe signal belongs after a specification test point is input to a drain of the MOS transistor, a source of the MOS transistor is grounded through the ground resistor, and a link gating signal of the PCIe signal is input to a gate of the MOS transistor.
Optionally, the control circuit comprises an FPGA.
The test fixture for the PCIe signal consistency test provided by the utility model realizes convenient and efficient PCIe test under the condition of ensuring the accuracy, the test line is not required to be repeatedly plugged after being connected, and meanwhile, the control circuit is matched to control the connection of the link, so that the PCIe test can realize automatic test, the test efficiency is improved, and the connector joint is protected.
Drawings
FIG. 1 is a schematic structural diagram of a test fixture for PCIe signal conformance testing in accordance with an embodiment of the present invention;
FIG. 2 is a schematic diagram of a signal selection circuit in the configuration shown in FIG. 1;
FIG. 3 is a schematic diagram of a 50 ohm impedance matching circuit in the configuration of FIG. 1;
fig. 4 is a schematic diagram of control signals of the control circuit.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Some embodiments of the utility model are described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
An embodiment of the present invention provides a test fixture for PCIe signal conformance testing, as shown in fig. 1, the test fixture includes: a signal connector 101, a signal selection circuit 102, an impedance matching circuit 103, and a control circuit 104.
The signal connector 101 is used for inputting N PCIe signals to be tested, N is greater than or equal to 2, and the input PCIe signals may be signals of X1, or signals of X2, X4, X8, X16, and X32. FIG. 1 is an example of an implementation of X16, including 16 PCIe signals. Each PCIe signal is a differential signal including a DP signal and a DN signal, and the 16 PCIe signals are transmitted to respective canonical sites of the 16 PCIe signals (TP 0, TP1 … … TP15 in fig. 1 represent canonical sites), and these canonical sites satisfy the condition: the insertion loss of the link with the signal connector 101 is 8dB for test accuracy.
The input ends of the signal selection circuit 102 are connected to the specification test points TP0 and TP1 … … TP15 of the 16 PCIe signals, the output ends of the signal selection circuit are connected to the SMP differential interface (SMP DP and SMP DN in fig. 1 indicate SMP differential interface), and the signal selection circuit 102 is configured to select one PCIe signal from the 16 PCIe signals to output to the SMP differential interface. The SMP differential interface is connected with testing instruments such as an oscilloscope and the like through a special connecting wire.
The impedance matching circuit 103 is typically a 50-ohm impedance matching circuit, and when there are N PCIe signals, there are 2N differential signals in total, so 2N 50-ohm impedance matching circuits 103 are required. And every two 50-ohm impedance matching circuits are in a group and connected to a signal path of the DP signal and the DN signal which belong to one PCIe signal after the specification test point, and are used for realizing 50-ohm impedance matching of the DP signal and the DN signal which belong to one PCIe signal.
And the control circuit 104 is configured to send a control signal to the signal selection circuit 102 and the 2N 50-ohm impedance matching circuits 103, so that the signal selection circuit 102 selects one PCIe signal path and enables the 50-ohm impedance matching circuits 103 connected to other PCIe signal paths except the PCIe signal path. That is, which PCIe signal is selected to be output, the 50 ohm impedance matching circuit connected to the selected PCIe signal is disabled, and the 50 ohm impedance matching circuit connected to each PCIe signal other than the selected PCIe signal needs to be enabled. Specifically, what type of control signal the control circuit 104 transmits depends on the specific circuit configuration of the signal selection circuit 102 and the 2N 50-ohm impedance matching circuits 103.
As a specific implementation manner, the signal selection circuit 102 may include a plurality of PCIe signal multiplexers connected in series in front and at the back, and is configured to select one PCIe signal from the input multiple PCIe signals according to the channel selection signal sent by the control circuit 104 for output. Specifically, fig. 2 shows a circuit configuration of the signal selection circuit 102. Referring to fig. 2, the input terminal of the signal selection circuit 102 is connected to 16 PCIe signals, and correspondingly, the signal selection circuit 102 may be implemented based on 5 PCIe signal multiplexers. I.e., includes a first PCIe signal multiplexer 1021, a second PCIe signal multiplexer 1022, a third PCIe signal multiplexer 1023, a fourth PCIe signal multiplexer 1024, and a fifth PCIe signal multiplexer 1025, wherein,
the first PCIe signal multiplexer 1021 is used for receiving 8 PCIe signals of the 16 PCIe signals, such as PCIe TX0 DP/DN-PCIe TX7 DP/DN, each PCIe TX signal DP/DN represents a differential signal, and 4 PCIe signals are selected and output;
the second PCIe signal multiplexer 1022 is used for receiving other 8 PCIe signals of the 16 PCIe signals, such as PCIe TX8 DP/DN-PCIe TX15 DP/DN, and selectively outputting 4 PCIe signals;
a third PCIe signal multiplexer 1023, configured to receive the 8 PCIe signals selectively output by the first PCIe signal multiplexer 1021 and the second PCIe signal multiplexer 1022, and further selectively output 4 PCIe signals;
the fourth PCIe signal multiplexer 1024 is configured to receive the 4-way PCIe signal selectively output by the third PCIe signal multiplexer 1023, and further selectively output the 2-way PCIe signal;
and the fifth PCIe signal multiplexer 1025 is configured to receive the 2-way PCIe signal selectively output by the fourth PCIe signal multiplexer 1024, and further selectively output the 1-way PCIe signal.
And finally outputting one path of PCIe signal from the 16 paths of PCIe signals through a channel selection function of the 5 PCIe signal multiplexers. SEL1, SEL2, SEL3, SEL4, SEL5 represent the channel select signals for first PCIe signal multiplexer 1021, second PCIe signal multiplexer 1022, third PCIe signal multiplexer 1023, fourth PCIe signal multiplexer 1024, and fifth PCIe signal multiplexer 1025, respectively, all from control circuit 104.
Further, the first PCIe signal multiplexer 1021, the second PCIe signal multiplexer 1022, and the third PCIe signal multiplexer 1023 are 8-to-4-way PCIe signal multiplexers (PCIe muxes), and the model of the optional device is PI3DBS16412, or other devices having the same function. Taking the first PCIe signal multiplexer 1021 as an example, when SEL1 inputs level L (low level), B [0-3] is connected to A [0-3 ]; when SEL1 inputs a level H (high level), C [0-3] is connected to A [0-3 ]. The second PCIe signal multiplexer 1022 and the third PCIe signal multiplexer 1023 work on the same principle.
The fourth PCIe signal multiplexer 1024 and the fifth PCIe signal multiplexer 1025 are 4-to-2-way PCIe signal multiplexers, and the model of the optional device is PI3DBS16212, or other devices with the same function. Taking the fourth PCIe signal multiplexer 1024 as an example, when SEL4 inputs a level L, E [0-1] is connected to D [0-1 ]; when SEL4 inputs level H, F [0-1] is connected to D [0-1 ]. The fifth PCIe signal multiplexer 1025 operates in the same principle.
Further, fig. 3 shows a schematic diagram of a 50 ohm impedance matching circuit. A set of 50 ohm impedance matching circuits (including two 50 ohm impedance matching circuits) are shown in fig. 3, each connected to PCIe TX0 DP/DN. The MOS transistor comprises an MOS transistor and a grounding resistor. The drain of M1 inputs the signal PCIe TX0DP after specification test point TP0, the source of M1 is grounded through a grounding resistor M1, and the gate of M1 inputs a link strobe signal SEL Lane 0. The drain of M2 inputs the signal PCIe TX0 DN after specification test point TP0, the source of M2 is grounded through a grounding resistor R2, and the gate of M2 inputs a link strobe signal SEL Lane 0.
The 50 ohm impedance matching circuit is connected to the signal PCIe TX0 DP/DN, and the circuit structure of the 50 ohm impedance matching circuit is the same for PCIe signals of other links, and the difference is only that the input link strobe signals are different. The link strobe signal for link Lane0 is denoted by SEL Lane0 in fig. 3, and for link N, the link strobe signal for link N may be denoted by SEL Lane N. Specifically, for other PCIe signals, the drains D of M1 and M2 are connected after the specification test point TPN (N0-15) of TXN (N0-15) DP/DN. The source S is connected with the resistor and grounded. The grid G is connected with a link strobe signal SEL LanEn (N is 0-15). When the SEL Lanen input is H, DS is turned on and TXN DP/DN is grounded through a ground resistor. When the SEL Lanen input is L, the DS is disabled and the TXN DP/DN is coupled to the subsequent PCIe signal multiplexer (PCIe MUX). The sum of the drain-source resistance Rds of the MOS transistor and the grounding resistance is 50 ohms, and the 50-ohm termination design realizes that other Lanes are grounded through the resistors when a link Lane N is tested, which is equivalent to the 50-ohm termination of the existing test fixture. Except the link to be tested, other links have signal transmission, and the crosstalk possibly existing in the actual working state is truly and accurately simulated.
Based on the circuit structures of fig. 2 and 3, the gating conditions for 16 links of X16 are as follows:
the control signals SEL1, SEL2, SEL3, SEL4, SEL5, SEL LaneN in the above table are all from the control circuit 104. The control circuit 104 may be designed in a cap-skipping mode, or in an automation mode implemented based on an FPGA (Field Programmable Gate Array). FIG. 4 shows a control signal diagram for an FPGA.
In addition, when the test fixture provided by the utility model is used for PCIe signal consistency test, the finally required test data is data of the specification test points, and the actually tested data is data from the SMP differential interface, so to ensure the test accuracy, first, IL (Insertion loss) of the entire link in the fixture is ensured to be 8dB, that is, Insertion loss of the link from the signal connector 101 to each specification test point TP0 to TP15 is ensured to be 8 dB. Then, for each link, the link between the canonical test point and the SMP differential interface will be eliminated by de-embedding. And measuring the S parameter SDD21 between the standard test point and the SMP differential interface by using a network analyzer, and embedding the test data of the SMP differential interface into the SDD21 to obtain the data at the standard test point.
The test fixture for the PCIe signal consistency test provided by the embodiment of the utility model realizes convenient and efficient PCIe test under the condition of ensuring the accuracy, the test line is not required to be repeatedly plugged after being connected, and meanwhile, the control circuit is matched to control the connection of the link, so that the PCIe test can realize automatic test and the test efficiency is improved.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. A test fixture for PCIe signal conformance testing, comprising:
the signal connector is used for inputting N paths of PCIe signals to be tested, N is more than or equal to 2, each path of PCIe signal is a differential signal comprising a DP signal and a DN signal, and the N paths of PCIe signals are transmitted to respective specification test points of the N paths of PCIe signals;
the input end of the signal selection circuit is connected to the specification test point of the N paths of PCIe signals, and the output end of the signal selection circuit is connected to the SMP differential interface and is used for selecting one path of PCIe signal from the N paths of PCIe signals and outputting the PCIe signal to the SMP differential interface;
2N impedance matching circuits which are connected with the DP signals and the DN signals to which the N PCIe signals belong in a one-to-one correspondence manner, wherein every two impedance matching circuits form a group, and any one group of impedance matching circuits is used for realizing impedance matching of the DP signals and the DN signals to which the one PCIe signal belongs;
and the control circuit is used for sending control signals to the signal selection circuit and the 2N impedance matching circuits so that the signal selection circuit selects one path of PCIe signals and enables the impedance matching circuits connected with other paths of PCIe signals except the path of PCIe signals.
2. The test fixture of claim 1, wherein the canonical test point satisfies a condition: the insertion loss of the link with the signal connector is 8 dB.
3. The test fixture of claim 1, wherein the signal selection circuit comprises:
and the PCIe signal multiplexers are connected in series and used for selecting one PCIe signal from the input N PCIe signals according to the channel selection signal sent by the control circuit and outputting the selected PCIe signal.
4. The test fixture of claim 3, wherein if the 16 PCIe signals are input, the signal selection circuit comprises a first PCIe signal multiplexer, a second PCIe signal multiplexer, a third PCIe signal multiplexer, a fourth PCIe signal multiplexer, and a fifth PCIe signal multiplexer,
the first PCIe signal multiplexer is used for receiving 8 PCIe signals of the 16 PCIe signals and selectively outputting 4 PCIe signals;
the second PCIe signal multiplexer is used for receiving the other 8 PCIe signals of the 16 PCIe signals and selectively outputting 4 PCIe signals;
the third PCIe signal multiplexer is used for receiving 8 routes of PCIe signals selectively output by the first PCIe signal multiplexer and the second PCIe signal multiplexer and further selectively outputting 4 routes of PCIe signals;
the fourth PCIe signal multiplexer is used for receiving the 4 paths of PCIe signals selectively output by the third PCIe signal multiplexer and further selectively outputting 2 paths of PCIe signals;
and the fifth PCIe signal multiplexer is used for receiving the 2-path PCIe signal selectively output by the fourth PCIe signal multiplexer and further selectively outputting the 1-path PCIe signal.
5. The test fixture of claim 4, wherein the first, second, and third PCIe signal multiplexers are 8-way to 4-way PCIe signal multiplexers.
6. The test fixture of claim 4, wherein the fourth and fifth PCIe signal multiplexers are 4-way to 2-way PCIe signal multiplexers.
7. The test fixture of claim 1, wherein the impedance matching circuit is a 50 ohm impedance matching circuit.
8. The test fixture of claim 7, wherein the 50 ohm impedance matching circuit comprises a MOS transistor and a ground resistor, a signal of a DP signal or a DN signal to which a PCIe signal belongs is input to a drain of the MOS transistor after a specification test point, a source of the MOS transistor is grounded through the ground resistor, and a link strobe signal of the PCIe signal is input to a gate of the MOS transistor.
9. The test fixture of claim 1, wherein the control circuit comprises an FPGA.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123239401.7U CN216622463U (en) | 2021-12-21 | 2021-12-21 | Test fixture for PCIe signal consistency test |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123239401.7U CN216622463U (en) | 2021-12-21 | 2021-12-21 | Test fixture for PCIe signal consistency test |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216622463U true CN216622463U (en) | 2022-05-27 |
Family
ID=81704640
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202123239401.7U Active CN216622463U (en) | 2021-12-21 | 2021-12-21 | Test fixture for PCIe signal consistency test |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216622463U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114113714A (en) * | 2021-12-21 | 2022-03-01 | 海光信息技术股份有限公司 | Test fixture for PCIe signal consistency test |
-
2021
- 2021-12-21 CN CN202123239401.7U patent/CN216622463U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114113714A (en) * | 2021-12-21 | 2022-03-01 | 海光信息技术股份有限公司 | Test fixture for PCIe signal consistency test |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8384410B1 (en) | Parallel test circuit with active devices | |
| US7058131B2 (en) | Signal transmission system with programmable voltage reference | |
| WO2001079863A3 (en) | Method and apparatus for testing signal paths between an integrated circuit wafer and a wafer tester | |
| CN216622463U (en) | Test fixture for PCIe signal consistency test | |
| CN208922244U (en) | A kind of high-speed serial bus suitable for high-performance SOC chip unstrings IP kernel | |
| CN111104278B (en) | SAS connector conduction detection system and method thereof | |
| US11929902B2 (en) | PCIe signal bandwidth determining method, apparatus and device | |
| CN110515788A (en) | A kind of test device of data-interface | |
| CN211062033U (en) | Test adapter and test equipment | |
| CN219737696U (en) | Test fixture based on phased array antenna wave accuse board | |
| CN102565674A (en) | Automatic double-channel test circuit for radio frequency power amplifiers based on peripheral component interconnect extension for instrumentation (PXI) test equipment | |
| CN103248527A (en) | Testing tool device, testing system and testing method for Ethernet consistency | |
| CN105045748B (en) | A kind of PVIB specialties virtual instrument bus | |
| CN110659037B (en) | JTAG-based burning device | |
| CN111104279B (en) | SAS connector conduction detection system and method thereof | |
| CN112448867B (en) | Signal delay testing method and device, computer readable storage medium and electronic equipment | |
| CN101331723B (en) | Differential signal transmission device and differential signal receiving apparatus | |
| CN114113714A (en) | Test fixture for PCIe signal consistency test | |
| CN104216809A (en) | Signal testing device | |
| CN204334563U (en) | A kind of device of automatic detection LVDS signalling channel number | |
| CN114706718B (en) | PCIe signal integrity verification method, device, equipment and medium | |
| CN114935716A (en) | ATE-based FPGA embedded SERDES test system and method | |
| CN109840170B (en) | PCIE signal measuring circuit | |
| CN206451068U (en) | Single channel high speed signal adapter based on FPGA | |
| CN103095255A (en) | Method used for eliminating return channels and based on schmitt trigger |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |