CN111428431A - Method and system for supporting automatic test and recording of EDA (electronic design automation) software - Google Patents
Method and system for supporting automatic test and recording of EDA (electronic design automation) software Download PDFInfo
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Abstract
A method and a system for supporting automatic testing and recording of EDA software can test as early and fully as possible, find out the problems in the software to the maximum extent, greatly improve the testing efficiency of the software, save the testing time, clearly see the result of executing each condition and the error reason, and have extremely high efficiency for the smoke test of each software version. The method comprises the following steps: (1) carrying out automatic design; (2) carrying out verification design of the whole system flow; (3) EDA module level automatic verification; (4) and (4) background verification and automatic integrated verification.
Description
Technical Field
The invention relates to the technical field of C/S structure software testing for C # codes, in particular to a method and a system for supporting automatic testing and recording of EDA software.
Background
C # (read as "C sharp," chinese translation "sharp") is an object-oriented, high-level programming language published by microsoft that runs on NET Framework, and is specified for the appearance of listings in microsoft professional developer forum (PDC). C # is the latest outcome of Microsoft researchers, Anders Hejlsberg. C # looks surprisingly similar to Java: it includes procedures such as single inheritance, interfaces, almost the same syntax as Java, and compilation into intermediate code for re-execution. However, C # differs significantly from Java in that it uses a feature of Delphi, is directly integrated with COM (component object model), and is the home role of microsoft NET windows network framework.
With the development of integrated circuit technology, EDA (electronic Design Automation) software of an FPGA (Field-Programmable Gate Array) is particularly important, and the EDA software of the FPGA is different from other software systems and integrates functions including a Design circuit, a compiling circuit, a debugging circuit and an analysis circuit.
The general software system is fixed for the result of one process, different circuits can generate different results for the EDA software in the invention, even the same circuit can also generate different results, a large number of circuits are required to carry out configuration of various functions to verify whether the EDA software is correct, which BUGs exist can not verify the correctness of the software by a large number of test circuits only through manual test, a large amount of time and energy are required at the moment, the time and the energy of a tester are greatly increased due to too many setting items and options in the software, the coverage rate is not high, and an automation technology is required to support the rapid test of the EDA software and discover and record the corresponding BUGs.
Disclosure of Invention
In order to overcome the defects of the prior art, the technical problem to be solved by the invention is to provide a method for supporting automatic testing and recording of EDA software, which can test as early and full as possible, find out the problems existing in the software to the maximum extent, greatly improve the testing efficiency of the software, save the testing time, clearly see the result and error reasons of each condition, and have extremely high efficiency for the smoke test of each software version.
The technical scheme of the invention is as follows: the method for supporting the automatic test and recording of the EDA software comprises the following steps:
(1) carrying out automatic design, recording controls on EDA software, combing and executing steps according to the working flow of FPGA, firstly generating a data drive file, firstly placing required variables in each unit in a first line, storing paths, top-level entities, source verilog, mif and hex files and configuration parameters in the units, wherein each line below represents a circuit CASE, storing data according to the drive variables, then binding the variables used in automation with the variables in the first line in the data drive file to obtain different parameters of the data in each line below, and then carrying out the execution of the whole flow;
(2) carrying out verification design of the whole system flow, wherein the flow comprises the following steps: creating circuit engineering, configuring comprehensive setting, generating a netlist file, creating a logic analyzer, adding signal reinforcement, configuring pins, setting timing constraints, boxing, laying out, wiring and outputting a result file;
(3) EDA module level automatic verification is carried out, and each module is automatically verified;
(4) background verification and automatic integrated verification: and after the whole flow is executed, performing background verification on some results of the background, and directly calling and executing a background verification script by using C #.
The invention has the advantages that through the whole-flow test of tens of thousands of different circuits and random configuration, each round of test has different configuration information, different circuits are realized, and the configuration items in each execution are different, so that the problems in the software are found out to the maximum extent, and the test can be carried out as early as possible and fully; for testers, the software testing efficiency is greatly improved, and the testing time is saved; for the summary log of the result file, a tester can clearly see the result of executing each CASE and the reason of an error; the smoking test for each software version has extremely high efficiency.
There is also provided a system for supporting automated testing and logging of EDA software, comprising:
the automatic design module is configured to carry out automatic design, record controls on EDA software, and comb execution steps according to the working flow of the FPGA, firstly, a data drive file is generated, required variables are placed in each unit of a first line, the units store paths, top-level entities, source verilog, mif and hex files and configuration parameters, each line below represents a circuit CASE, data are stored according to the drive variables, then different parameters of the data of each line below are obtained by binding the variables used in the automation with the variables of the first line in the data drive file, and then the execution of the whole flow is carried out;
the system full-flow verification design module is configured to carry out verification design of the system full-flow, and the flow steps comprise: creating circuit engineering, configuring comprehensive setting, generating a netlist file, creating a logic analyzer, adding signal reinforcement, configuring pins, setting timing constraints, boxing, laying out, wiring and outputting a result file;
a module level automatic verification module configured to perform EDA module level automatic verification, performing automatic verification on each module;
the background verification and automatic integrated verification module is configured to perform background verification and automatic integrated verification: and after the whole flow is executed, performing background verification on some results of the background, and directly calling and executing a background verification script by using C #.
Drawings
Fig. 1 shows a flow chart of step (1) of the method of supporting automated testing and logging of EDA software according to the invention.
Fig. 2 shows the generated data driver file.
Fig. 3 shows a flow chart of step (2) of the method of supporting automated testing and logging of EDA software according to the invention.
FIG. 4 is a flow chart of a method of supporting automated testing and logging of EDA software according to the present invention.
Detailed Description
As shown in fig. 4, the method for supporting the automated testing and recording of EDA software comprises the following steps:
(1) carrying out automatic design, recording controls on EDA software, combing and executing steps according to the working flow of FPGA, firstly generating a data drive file, firstly placing required variables in each unit in a first line, storing paths, top-level entities, source verilog, mif and hex files and configuration parameters in the units, wherein each line below represents a circuit CASE, storing data according to the drive variables, then binding the variables used in automation with the variables in the first line in the data drive file to obtain different parameters of the data in each line below, and then carrying out the execution of the whole flow;
(2) carrying out verification design of the whole system flow, wherein the flow comprises the following steps: creating circuit engineering, configuring comprehensive setting, generating a netlist file, creating a logic analyzer, adding signal reinforcement, configuring pins, setting timing constraints, boxing, laying out, wiring and outputting a result file;
(3) EDA module level automatic verification is carried out, and each module is automatically verified;
(4) background verification and automatic integrated verification: and after the whole flow is executed, performing background verification on some results of the background, and directly calling and executing a background verification script by using C #.
The invention has the advantages that through the whole-flow test of tens of thousands of different circuits and random configuration, each round of test has different configuration information, different circuits are realized, and the configuration items in each execution are different, so that the problems in the software are found out to the maximum extent, and the test can be carried out as early as possible and fully; for testers, the software testing efficiency is greatly improved, and the testing time is saved; for the summary log of the result file, a tester can clearly see the result of executing each CASE and the reason of an error; the smoking test for each software version has extremely high efficiency.
Preferably, in the step (1), after the netlist is generated, the logic analyzer is configured, and if some circuit netlists are not generated, the following steps are directly terminated, a CASE is directly run next, and a USER CODE is added to perform the script control flow step.
Preferably, as shown in fig. 1, the step (1) comprises the following sub-steps:
(1.1) recording the control, storing the control in a control warehouse, and sharing one control warehouse by different automatic test scripts for the same software system; when the control cannot be identified, identifying by using a coordinate mode;
(1.2) configuring a logic analyzer, a reinforcement signal function and pins after generating a netlist, and configuring a time sequence after boxing, layout and wiring; randomly generating a USER CODE USER CODE for the selected values of the drop-down lists or check boxes of some configuration items; directly calling a bottom layer CHECK CHECK script by using the USER CODE to CHECK the bottom layer of each circuit;
(1.3) storing variables required to be used in EXCE L according to actual service requirements, storing variable names in a first line, storing CASE values in a second line, and acquiring the CASE values by using scripts;
(1.4) replaying the script, and if the script is checked to have no problem, carrying out automatic test; the executed result file comprises an interface part and a bottom layer part, wherein the interface part is the result of some assertions of the interface after the interface automation is executed, and the bottom layer part is the result file generated by calling a bottom layer verification script through the interface automation.
Preferably, in the step (1.3), the data-driven data is associated into the corresponding automation CASE and bound with the corresponding parameters.
Preferably, as shown in fig. 3, the step (2) comprises the following sub-steps:
(2.1) during synthesis, if a netlist file is generated, executing the step (2.2); if the netlist file is not generated, the CASE execution is finished, and a result log is recorded;
(2.2) acquiring an observation signal and a C L K signal in the logic analyzer in the generated netlist file, executing automatic configuration and synthesizing;
(2.3) carrying out comprehensive configuration, and randomly generating a value to be configured according to the value of each configuration item;
(2.4) acquiring reinforcement signals from the netlist file, wherein the number of the reinforcement signals is not more than 6 according to the service requirement, and the code control configuration times randomly generate integers within 6 for configuration;
(2.5) judging whether the synthesis is successful after the logic analyzer is carried on, and if so, executing the step (2.6); if the CASE fails, the CASE execution is ended, and a result log is recorded;
(2.6) acquiring the pin number of the device through the code, configuring the pins, and not configuring repeated pins for each signal; randomly distributing the on or off of the register, then performing boxing layout wiring, if the wiring is successful, executing the step (2.7), otherwise, ending the CASE execution and recording a result log;
(2.7) when time sequence constraints are configured, acquiring Net, Pins or Ports from a bottom file according to different constraints to configure, then performing boxing, layout and wiring, judging whether wiring is successful, recording that execution is successful if the wiring is successful, and otherwise, recording a result log after the CASE execution is finished;
and (2.8) performing background script verification, writing the PATH and PROJECTNAME into a storage file through the USER CODE, and calling the PYTHON script to verify various bottom layer files.
Preferably, in the step (2.6), C L K of P LL (Phase L ocked L oop ) is assigned to a specific pin.
Preferably, in the step (2.7), when the CREATE _ C L OCK constraint is performed, the SOURCE obtained is C L K, and the PERIOD, the RISING and the FA LL ING randomly generate reasonable values through the system.
Preferably, in the step (2), if the execution time exceeds 30 minutes, the process is directly stopped, and recorded as TIMEOUT, and the execution of the next CASE is performed, and the CASE of TIMEOUT is subsequently verified separately.
Preferably, the step (3) includes: verifying whether default values configured by different pins are correct under the conditions of output, input and dual ports; when some I/O Standard is configured in an output or input and dual port mode, whether the disabled register is successfully disabled or not and whether the configuration information is written into an underlying configuration file or not is correct; when the full flow is executed, whether the configuration information is cleared or covered is checked.
It will be understood by those skilled in the art that all or part of the steps in the method of the above embodiments may be implemented by hardware instructions related to a program, the program may be stored in a computer-readable storage medium, and when executed, the program includes the steps of the method of the above embodiments, and the storage medium may be: ROM/RAM, magnetic disks, optical disks, memory cards, and the like. Thus, in accordance with the method of the present invention, the invention also encompasses a system for supporting automated testing and logging of EDA software, which is generally represented in the form of functional modules corresponding to the steps of the method. The system comprises:
the automatic design module is configured to carry out automatic design, record controls on EDA software, and comb execution steps according to the working flow of the FPGA, firstly, a data drive file is generated, required variables are placed in each unit of a first line, the units store paths, top-level entities, source verilog, mif and hex files and configuration parameters, each line below represents a circuit CASE, data are stored according to the drive variables, then different parameters of the data of each line below are obtained by binding the variables used in the automation with the variables of the first line in the data drive file, and then the execution of the whole flow is carried out;
the system full-flow verification design module is configured to carry out verification design of the system full-flow, and the flow steps comprise: creating circuit engineering, configuring comprehensive setting, generating a netlist file, creating a logic analyzer, adding signal reinforcement, configuring pins, setting timing constraints, boxing, laying out, wiring and outputting a result file;
a module level automatic verification module configured to perform EDA module level automatic verification, performing automatic verification on each module;
the background verification and automatic integrated verification module is configured to perform background verification and automatic integrated verification: and after the whole flow is executed, performing background verification on some results of the background, and directly calling and executing a background verification script by using C #.
The present invention is described in more detail below. The method comprises the following aspects:
1. automated design process:
the main idea of the automatic design is to record controls on the EDA software, and to sort the execution steps according to the workflow of the FPGA, because the present invention does not automatically test a single circuit, the storage path, the top layer entity, the source verilog, the mif, the hex file storage path, and the configuration parameters of the circuit need to be stored in the data driving file, and then different parameters are obtained by obtaining the data of each line to execute the whole flow. The working schematic diagram is shown in fig. 1.
The workflow decomposition is illustrated as follows:
1) recording controls
The primary task of the EDA software is to record the controls and store the controls in a control warehouse, so that different automatic test scripts can share one control warehouse for the same software system, and multiple repeated warehouses are avoided. For an automatic tool, occasionally, due to the limitation of the tool, the situation that the control cannot be identified can be caused, and then the identification can be carried out in a coordinate mode.
2) Enhanced scripts
The full flow process in EDA software involves a number of modules with interrelationships between modules, logic analyzers, reinforcement signal functions, and pin configuration must be performed after the netlist is generated, and timing configuration must be performed after binning, placement, and routing. Because a large number of circuits, thousands or tens of thousands of circuits need to be tested, the logic conditions which possibly occur need to be judged; meanwhile, for the selected values of the drop-down lists or check boxes of some configuration items, the USER CODE can be randomly generated, the situation that the same parameter is used when the CASE is executed every time is avoided, and the randomness can be increased. In addition, the method and the device directly call the bottom CHECK script to CHECK the bottom layer of each circuit by using the USER CODE. See 2 for a detailed description.
3) EXCE L data drive
According to actual business requirements, variables needed to be used are stored in the EXCE L, a first line stores variable names, a second line starts to store CASE values, and since there are sometimes tens of thousands of CASE and many variables, which cannot be filled in by themselves, scripts are needed to obtain the CASE values, for example, a PATH is obtained through a BAT file, as shown below, PATHs of all files ending in v in the directory are stored in a generate _ path.txt file, and the scripts are shown below:
@echo off&setlocal EnableDelayedExpansion
for/f"delims＝"％％i in('"dir/a/s/b/on*.v"')do(
set file＝％％～fi
set file＝！file:/＝/！
echo！file！>>generate_path.txt
)
the generated data driver file is shown in fig. 2.
It should be noted here that data of the data driver must be associated with the corresponding automation CASE and bound to the corresponding parameter for use, otherwise, the parameter is not bound and the variable in the data driver cannot be acquired, and the set default value of the variable is directly taken.
4) Playback of scripts to perform automated testing
And (5) replaying the script, and if the script is checked to have no problem, carrying out automatic test. The result file after execution here includes an interface portion and an underlying portion. The interface part is mainly used for judging results of some assertions of the interface after the interface automation is executed, and the bottom part is mainly used for calling a result file generated by a bottom verification script through the interface automation.
2. EDA software system level full flow automation verification:
for the EDA software of the FPGA, the invention carries out verification design of the whole system flow, and the flow steps comprise circuit engineering creation, comprehensive configuration setting, netlist file generation, logic analyzer creation, signal reinforcement addition, pin configuration, timing constraint setting, boxing, layout, wiring and result file output. For such a large-scale circuit verification, logic controls need to be performed according to the characteristics of software, and specific logic controls are as follows:
(1) during synthesis, if a netlist file is generated, performing the operation (2); if a netlist file is not generated, this CASE execution ends and the result log is recorded.
(2) Acquisition of observed signals and C L K signals in the logic analyzer and performing automatic configuration, and synthesis are performed in the generated netlist file.
(3) And carrying out comprehensive configuration, and randomly generating a value to be configured according to the value of each configuration item, so that the data is not easy to test repeatedly.
(4) And acquiring reinforcement signals from the netlist file, wherein the reinforcement signals cannot exceed 6 according to the service requirement, and the code control configuration times randomly generate integers within 6 for configuration.
(5) Judging whether the synthesis is successful after the logic analyzer is carried on, and if so, performing the operation (6); if it fails, this CASE execution ends and the result log is recorded.
(6) C L K of a special P LL needs to be assigned to the assigned pin, at the moment, if the situation of P LL is judged to be met, C L K is assigned to the special pin, the pin assignment also relates to ON or OFF of a plurality of registers, random assignment is carried out, then boxing layout wiring is carried out, if wiring is successful, the subsequent (7) operation is carried out, otherwise, the CASE execution is finished, and a result log is recorded.
(7) When configuring time sequence constraint, according to different constraints, acquiring Net, Pins or Ports from a bottom layer file for configuration, for example, when performing CREATE _ C L OCK constraint, acquiring SOURCE as C L K, PERIOD, RISING and FA LL ING randomly generating reasonable values through a system, performing packing layout and wiring by the same method with other constraints, judging whether wiring is successful, recording execution success if successful, otherwise, finishing CASE execution and recording result log
(8) And (3) performing background script CHECK, writing the PATH and the PROJECTNAME into a storage file through the USER CODE, and calling the PYTHON script to verify various bottom files, so that each circuit can be verified as much as possible.
In the invention, because some circuits are overlarge and need to run for several hours, the test execution efficiency of other circuits is hindered, most circuits are executed within 30 minutes after analysis and judgment, so the judgment is carried out here, if the execution time exceeds 30 minutes, the STOP flow is directly carried out and recorded as TIMEOUT, the execution of the next CASE is carried out, and the CASE of TIMEOUT is subsequently and independently verified.
The system flow is shown in fig. 3.
3. EDA module level automated verification
The module level automation is to write the manual check of each module as automatic as possible for automatic check, and the using flow of the automatic tool is the same as the above 1. Different from the full-flow automation of the system, the full-flow execution is the whole-flow execution of the circuit, whether problems exist or not is verified, and the particles of the module-level automation are finer. The invention adds module level automation for the pin configuration, and roughly relates to the following points:
(1) verifying whether default values configured by different pins are correct under the conditions of output, input and dual ports;
(2) when some I/O Standard is configured in an output or input and dual port mode, whether the disabled register is successfully disabled or not and whether the configuration information is written into an underlying configuration file or not is correct;
(3) whether CHECK will cause configuration information to be cleared or overwritten while the full flow is executed.
Through the module-level automatic verification and the system full-flow automatic verification, whether a certain software version has a severe BUG or not can be quickly verified, and quick self-checking can be carried out.
4. Background verification and automated integration verification
The background verification is mainly performed on some results of the background after the whole process is executed, and the C # is used for directly calling and executing the background verification script, so that the interface and background problems of the circuit can be found out as much as possible, and the test coverage rate is more comprehensive.
The invention can test the EDA software of the FPGA as early as possible and fully, and through the whole-flow test of tens of thousands of different circuits and random configuration, each test has different configuration information, so that different circuits are realized, and the configuration items during each execution are different, thereby finding out the problems in the software to the maximum extent. For testers, the software testing efficiency is greatly improved, and the testing time is saved. For the summary log of the result file, a tester can clearly see the result of executing each CASE and the error reason, and the smoking test of each software version has extremely high efficiency.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and all simple modifications, equivalent variations and modifications made to the above embodiment according to the technical spirit of the present invention still belong to the protection scope of the technical solution of the present invention.
Claims (10)
1. A method for supporting automatic test and recording of EDA software is characterized in that: which comprises the following steps:
(1) carrying out automatic design, recording controls on EDA software, combing and executing steps according to the working flow of FPGA, firstly generating a data drive file, firstly placing required variables in each unit in a first line, storing paths, top-level entities, source verilog, mif and hex files and configuration parameters in the units, wherein each line below represents a circuit CASE, storing data according to the drive variables, then binding the variables used in automation with the variables in the first line in the data drive file to obtain different parameters of the data in each line below, and then carrying out the execution of the whole flow;
(2) carrying out verification design of the whole system flow, wherein the flow comprises the following steps: creating circuit engineering, configuring comprehensive setting, generating a netlist file, creating a logic analyzer, adding signal reinforcement, configuring pins, setting timing constraints, boxing, laying out, wiring and outputting a result file;
(3) EDA module level automatic verification is carried out, and each module is automatically verified;
(4) background verification and automatic integrated verification: and after the whole flow is executed, performing background verification on some results of the background, and directly calling and executing a background verification script by using C #.
2. The method for supporting automated testing and logging of EDA software according to claim 1, wherein: in the step (1), after the netlist is generated, the logic analyzer is configured, if some circuit netlists are not generated, the following steps are directly terminated, a CASE is directly started, and a USER CODE is added to perform a script control flow step.
3. The method for supporting automated testing and logging of EDA software according to claim 2, characterized in that: the step (1) comprises the following sub-steps:
(1.1) recording the control, storing the control in a control warehouse, and sharing one control warehouse by different automatic test scripts for the same software system; when the control cannot be identified, identifying by using a coordinate mode;
(1.2) configuring a logic analyzer, a reinforcement signal function and pins after generating a netlist, and configuring a time sequence after boxing, layout and wiring; randomly generating a USER CODE USER CODE for the selected values of the drop-down lists or check boxes of some configuration items; directly calling a bottom layer CHECK CHECK script by using the USER CODE to CHECK the bottom layer of each circuit;
(1.3) storing variables required to be used in EXCE L according to actual service requirements, storing variable names in a first line, storing CASE values in a second line, and acquiring the CASE values by using scripts;
(1.4) replaying the script, and if the script is checked to have no problem, carrying out automatic test; the executed result file comprises an interface part and a bottom layer part, wherein the interface part is the result of some assertions of the interface after the interface automation is executed, and the bottom layer part is the result file generated by calling a bottom layer verification script through the interface automation.
4. Method for supporting automated testing and logging of EDA software according to claim 3, characterized in that: in the step (1.3), the data-driven data is associated into the corresponding automation CASE and bound with the corresponding parameters.
5. Method for supporting automated testing and logging of EDA software according to claim 4, characterized in that: the step (2) comprises the following sub-steps:
(2.1) during synthesis, if a netlist file is generated, executing the step (2.2); if the netlist file is not generated, the CASE execution is finished, and a result log is recorded;
(2.2) acquiring an observation signal and a C L K signal in the logic analyzer in the generated netlist file, executing automatic configuration and synthesizing;
(2.3) carrying out comprehensive configuration, and randomly generating a value to be configured according to the value of each configuration item;
(2.4) acquiring reinforcement signals from the netlist file, wherein the number of the reinforcement signals is not more than 6 according to the service requirement, and the code control configuration times randomly generate integers within 6 for configuration;
(2.5) judging whether the synthesis is successful after the logic analyzer is carried on, and if so, executing the step (2.6); if the CASE fails, the CASE execution is ended, and a result log is recorded;
(2.6) acquiring the pin number of the device through the code, configuring the pins, and not configuring repeated pins for each signal; randomly distributing the on or off of the register, then performing boxing layout wiring, if the wiring is successful, executing the step (2.7), otherwise, ending the CASE execution and recording a result log;
(2.7) when time sequence constraints are configured, acquiring Net, Pins or Ports from a bottom file according to different constraints to configure, then performing boxing, layout and wiring, judging whether wiring is successful, recording that execution is successful if the wiring is successful, and otherwise, recording a result log after the CASE execution is finished;
and (2.8) performing background script verification, writing the PATH and PROJECTNAME into a storage file through the USER CODE, and calling the PYTHON script to verify various bottom layer files.
6. The method for supporting automated testing and recording of EDA software according to claim 5, wherein in said step (2.6), C L K of the phase locked loop P LL is assigned to a specific pin.
7. The method for supporting automated testing and recording of EDA software according to claim 6, wherein in said step (2.7), when CREATE _ C L OCK constraint is performed, the SOURCE SOURCE is obtained as C L K, PERIOD, RISING and FA LL ING randomly generate reasonable values through the system.
8. The method for supporting automated testing and logging of EDA software according to claim 7, wherein: in the step (2), if the execution time exceeds 30 minutes, the process is directly stopped, the time is recorded as TIMEOUT, the next CASE execution is performed, and the CASE of TIMEOUT is subsequently verified separately.
9. The method for supporting automated testing and logging of EDA software according to claim 7, wherein: the step (3) comprises the following steps: verifying whether default values configured by different pins are correct under the conditions of output, input and dual ports; when some I/O Standard is configured in an output or input and dual port mode, whether the disabled register is successfully disabled or not and whether the configuration information is written into an underlying configuration file or not is correct; when the full flow is executed, whether the configuration information is cleared or covered is checked.
10. A system for supporting automated testing and logging of EDA software, characterized by: it includes:
the automatic design module is configured to carry out automatic design, record controls on EDA software, and comb execution steps according to the working flow of the FPGA, firstly, a data drive file is generated, required variables are placed in each unit of a first line, the units store paths, top-level entities, source verilog, mif and hex files and configuration parameters, each line below represents a circuit CASE, data are stored according to the drive variables, then different parameters of the data of each line below are obtained by binding the variables used in the automation with the variables of the first line in the data drive file, and then the execution of the whole flow is carried out;
the system full-flow verification design module is configured to carry out verification design of the system full-flow, and the flow steps comprise: creating circuit engineering, configuring comprehensive setting, generating a netlist file, creating a logic analyzer, adding signal reinforcement, configuring pins, setting timing constraints, boxing, laying out, wiring and outputting a result file;
a module level automatic verification module configured to perform EDA module level automatic verification, performing automatic verification on each module;
the background verification and automatic integrated verification module is configured to perform background verification and automatic integrated verification: and after the whole flow is executed, performing background verification on some results of the background, and directly calling and executing a background verification script by using C #.
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