CN116738912B

CN116738912B - EDA software reconfigurable function automation method and electronic equipment

Info

Publication number: CN116738912B
Application number: CN202310997871.4A
Authority: CN
Inventors: 夏燕; 徐维涛; 蔡刚; 魏育成
Original assignee: Ehiway Microelectronic Science And Technology Suzhou Co ltd
Current assignee: Ehiway Microelectronic Science And Technology Suzhou Co ltd
Priority date: 2023-08-09
Filing date: 2023-08-09
Publication date: 2023-10-27
Anticipated expiration: 2043-08-09
Also published as: CN116738912A

Abstract

The invention provides an EDA software reconfigurable function automation method and electronic equipment, comprising the following steps: screening a circuit conforming to a reconfigurable function in a circuit library as a target circuit, and acquiring a verilog file in the target circuit as a file of a father run; modifying logic in the file of the father run to generate a new verilog file as a file of the child run; acquiring and storing all effective information in the target circuit, wherein the effective information comprises a circuit path, the names of the files of the father run and the names of the files of the son run; and executing the parent run and the child run. The reconfigurable function can be quickly checked, bug is exposed in time, the testing efficiency of the software is improved, the testing coverage rate is greatly improved, and the software reliability is optimized.

Description

EDA software reconfigurable function automation method and electronic equipment

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to an EDA software reconfigurable function automation method and corresponding electronic equipment.

Background

In the automated design of (field programmable gate array) FPGAs, an automated tool for designing electronic circuits, such as EDA software, first converts a circuit design into a netlist file, and then performs a series of processes such as packaging, placement, routing, code matching, and the like based on the netlist file. Reconfigurable (PR) allows a user to dynamically reconfigure portions of the contents of the FPGA while keeping the FPGA operational. The whole process requires the realization of a plurality of configuration functions, and finally a complete code stream file and a partial code stream file aiming at each reconfigurable module are generated. Outside the reconfigurable module, the area where the function is not changed is called a static area, and the area where the function is changed is called a dynamic area. In the PR process, the positions of the boxing, the layout and the wiring of different areas are different, so that a great deal of time and labor are required for carrying out manual testing, and the ideal result of the testing cannot be achieved in a short time. Specifically: in the process, the original FPGA content is changed into new content by changing logic, and more logic is involved in the process. Manual operation is time consuming and prone to error. And then, a dynamic area is required to be set for boxing, layout and wiring, the operation is complex and time-consuming, and the testing efficiency is difficult to further improve.

Therefore, it is needed to study how to automatically implement the reconfigurable function of the EDA software, provide a solution for implementing the automatic mode of the reconfigurable function in the programmable logic device FPGA EDA software, shorten the time, improve the test efficiency, further avoid errors and improve the reliability, so as to promote the deep application of the automatic circuit design.

Disclosure of Invention

In order to solve all or part of the problems in the prior art, the invention provides an EDA software reconfigurable function automation method, and an automation script is used, so that manual and manual operation errors can be effectively avoided, and the reliability and the testing efficiency are comprehensively improved; the invention further provides corresponding electronic equipment.

The invention provides an EDA software reconfigurable function automation method, which marks the content to be reconfigured as father run and the content to be replaced and reconfigured as son run, comprising the following steps: screening a circuit conforming to a reconfigurable function in a circuit library as a target circuit, and acquiring a verilog file in the target circuit as a file of a father run; modifying logic in the file of the father run to generate a new verilog file as a file of the child run; acquiring and storing all effective information in the target circuit, wherein the effective information comprises a circuit path, the names of the files of the father run and the names of the files of the son run; executing the parent run and the child run, including: writing a reconfigurable command into a constraint file; randomly designating the range of a dynamic area conforming to the rule, carrying out boxing, layout and wiring on the files of the father run in the static area, and carrying out boxing, layout and wiring on the files of the son run in the dynamic area.

The circuit conforming to the reconfigurable function is selected in an automatic mode, logic of a module to be subjected to the reconfigurable is modified randomly, and commands are input into the constraint file in different stages of operation, so that the operation of the whole process is completed. The automatic method is provided, the circuit conforming to the reconfigurable function can be selected from a larger number of circuits, the time for manually selecting the circuit is saved, the range of a dynamic area is not required to be manually input and planned, the range of the dynamic area can be randomly generated in a script, the error risks of manual operation and manual operation are avoided, the testing efficiency is improved, the automatic method is suitable for the operation of a large number of circuits, the testing coverage rate is greatly improved, and the reliability of software is further improved.

The criteria for the screening were: at least one circuit should be nested in the tested circuit. And finding a circuit conforming to the reconfigurable function by searching whether the verilog file is nested with other verilog files, wherein the verilog file in the circuit is used as a file of a father run. The circuitry conforming to the reconfigurable function refers to: in the circuit, one or more verilog files are nested in the verilog files.

The range of the dynamic area conforming to the rule means that the range of the dynamic area is within the range of the programmable logic module of the target circuit and does not comprise the input-output module and the data processing module of the target circuit. That is, the range of the dynamic region conforming to the rule means that the range of the dynamic region is within the range of clb and does not include io and dsp. clb and io, dsp are different common modules in the circuit, namely a logic module, an input-output module and a data processing module, respectively. In general cases, the io module is fixed and cannot be changed, the dsp module is a processor, the replacement difficulty is high, and the clb module is limited to be reconfigurable, so that the efficiency is optimized.

The process of obtaining the file of the father run comprises the following steps: traversing a circuit library file to obtain the target circuit, wherein a plurality of verilog files are instantiated in the target circuit; traversing the names of the verilog files in the target circuit, and randomly extracting the verilog files inside the target circuit to serve as a reconfigurable module, namely the file of the father run.

The logic in the v (verilog) file is modified after the file of the father run is obtained to obtain a new v file, the file of the child run is obtained by the v file, the random modification of the logic has more possibility, the logic is performed in an automatic mode, the process of manual thinking and operation is omitted in the middle, and the coverage rate is high and the time is saved by the automatic mode.

And modifying the verilog file obtained after the logic of the reconfigurable module as a reconfigurable file to obtain the sub run file.

The method for acquiring and storing all the effective information in the target circuit comprises the following steps: generating a character string (str) and a list (list), wherein the character string (str) characterizes the names of the files of the child run, and the list (list) is a path of the files of the child run and the files of the father run stored in a list form.

The constraint files comprise a first constraint file and a second constraint file; the method for executing the father run comprises the following steps: creating a result storage file of a father run; writing a reconfigurable command into the first constraint file; creating a first command file; the first command file comprises a comprehensive command file and a boxing command file; operating the boxing command file to obtain a boxing file (pcblock file); the reconfigurable signals are put together and placed in the dynamic area, and the normal signals are put together and placed in the static area.

The process for obtaining the boxing file comprises the following steps: creating the integrated command file and the boxing command file respectively; and writing the name of the command to be called and the path for storing the result in the boxed command file. Creating a comprehensive command file (tcl.bat file) and a boxed command file (pack.tcl file), writing a path needing to call tcl names and result storage in the pack.tcl file, and creating an edc file; writing a command in the edc file, wherein the command content comprises: the name of the parent run, the range of the dynamic zone. By running the pack.tcl file, a pcblock file can be obtained, and a dynamic area and a static area in the pcblock file can be boxed separately.

By means of the added command, normal signals of the boxing file (pcblock file) and reconfigurable signals can be boxed correctly.

The process of writing the first constraint file comprises the following steps: creating a file with a first preset format as the first constraint file; writing a command in the first constraint file, wherein the command content comprises: the name of the parent run, the range of the dynamic zone.

After obtaining the boxing file, the steps are carried out: judging whether the generation of the boxing file is successful, if so, creating a wiring command file, writing a command into the wiring command file, and operating the wiring command file to obtain a layout file and a wiring file. The boxing, placement and routing of parent run is completed.

The wiring file contains normal signals and reconfigurable signals; the reconfigurable signal contains partial reconfigurable PR (PR is the abbreviation of Partial Reconfiguration), and the normal signal does not contain PR; the reconfigurable signal is routed to limit the range of the dynamic region.

The method for executing the child run comprises the following steps: creating a result storage file of a child run; creating a second command file, wherein the second command file comprises a file of pin configuration; writing the path for storing the file into the file of the pin configuration; creating a file with a second preset format as the second constraint file, and writing a command in the second constraint file, wherein the command content comprises the child run name, the dynamic area range and the authorized file of the father run.

In some embodiments, the first constraint file and the second constraint file are files that support different automation design software read formats.

Another aspect of the invention provides an electronic device for performing the EDA software reconfigurable function automation method of the invention.

Compared with the prior art, the invention has the main beneficial effects that:

according to the EDA software reconfigurable function automation method, a reconfigurable command is written into a constraint file, a parent run file and a child run file are respectively and correspondingly packaged, laid out and wired in a static area and a dynamic area, a circuit conforming to the reconfigurable function can be selected from thousands of circuits through an automation means, the time for manually selecting the circuit is shortened, an automation script is used, packaging, layout and wiring can be automatically completed, manual command input and dynamic area planning are not needed, the dynamic area range can be randomly generated in the script, the reconfigurable function can be rapidly verified, the bug is exposed timely, and the software testing efficiency is improved. In addition, the automatic mode can realize the operation of a large number of circuits, thereby further improving the coverage rate of the test and being beneficial to improving the reliability of software. The electronic equipment has corresponding advantages because the automatic method can be realized.

Drawings

FIG. 1 is a schematic diagram of an EDA software reconfigurable function automation method according to an embodiment of the present invention.

FIG. 2 is a flow chart of EDA software reconfigurable function automation in accordance with an embodiment of the present invention.

FIG. 3 is a schematic diagram illustrating a process of executing a parent run according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully, and it is apparent that the embodiments described are only some, but not all, of the embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

An EDA software reconfigurable function automation method in an embodiment of the present invention as illustrated in fig. 1 is implemented by the electronic device provided in this embodiment. In this embodiment, the content to be reconstructed is denoted as a parent run, and the content to be reconstructed is denoted as a child run, as shown in fig. 1, the method includes: screening a circuit conforming to the reconfigurable function in a circuit library as a target circuit, and acquiring a verilog file in the target circuit as a file of a father run; modifying logic in the file of the father run to generate a new verilog file as the file of the child run; acquiring and storing all effective information in a target circuit, wherein the effective information comprises a circuit path, a name of a file of a father run and a name of a file of a son run; executing a parent run and child run, comprising: writing a reconfigurable command into a constraint file; randomly designating the range of a dynamic region conforming to the rule, boxing, laying out and wiring the files of the father run in the static region, and boxing, laying out and wiring the files of the son run in the dynamic region.

Modifying logic in the file of the father run means changing the file of the father run to achieve the reconstruction goal, wherein the logic refers to the logic function of the circuit, namely, the calculation or operation performed by the circuit; specifically, it refers to modifying the computation mode or operation mode of the circuits in the Verilog file to generate a new Verilog file to meet the required reconfiguration function; the modification of the logic described above includes at least one of the following: circuit element modification: the method involves replacing, adding or deleting elements such as logic gates, flip-flops, multiplexers and the like in the circuit to realize new functions; and (3) connection relation adjustment: the connection modes among different elements in the circuit are adjusted to adapt to new functional requirements; and (3) adjusting a control signal: modifying control signal paths in the circuit to achieve different operating sequences or modes; and (3) sequential logic adjustment: changing the time sequence relation in the circuit to meet the new reconstruction requirement; reconstruction of a data path: redesign the data path in the circuit to realize different data flows or operation flows; state machine reprogramming: the state machine behavior of the circuit is redefined to achieve different state transitions and state control.

The criteria for screening in this example are: at least one circuit should be nested in the tested circuit.

In some specific examples, the dynamic region should be within the range of clb and not include io and dsp. In this embodiment, only the reconfigurable of the clb module is supported, but the io module and the dsp module are not reconfigurable, which is a specific implementation of the reconfigurable object, and the reconfiguration of other modules is not attempted, so that the efficiency is better, but the present invention is not limited to the specific case. In a specific example, the random assignment of the dynamic zone ranges is written in a python script, and clb modules are scoped, for example: the area is 0-50 on the x-axis and 0-100 on the y-axis, and the script will automatically randomly draw a range within the area as the range of the dynamic zone.

The flow of the EDA software reconfigurable function automating method of the present embodiment is exemplified below in conjunction with fig. 2 and 3. In the case illustrated in fig. 2, the main steps are as follows.

The analysis circuit is used for obtaining a circuit meeting the conditions (a plurality of v files are instantiated in an example circuit, namely) verilog files, selecting the instantiated files, obtaining names of the instantiated v files through traversal, and randomly extracting one v file as a reconfigurable module, namely a parent run file; and modifying logic in the v file to obtain a new v file serving as a child run file. The conditions of the screening in the example case are preset as: in the circuit, one or more verilog files are nested in the verilog files. In the example case, a.v. file in a circuit, if one or more.v. files are nested, is eligible. The code for this example of the process is as follows:

Str = 'butterfly_unit_child'

List=['D:/new_file/PR_CASE/A0_4/fft_8192\\butterfly_unit_child.v','butterfly_unit:u0_butterfly_unit']

in the example case a string str is obtained, where str is the name of the child run, and a list of paths and modules (stored in list form) where the file can be reconstructed.

Referring to fig. 3 in combination, the parsing circuit then executes the parent run. Using the python os module in the example case, a result deposit file for the parent run is created; writing a reconfigurable command into a (first) constraint file, creating a first command file; the first command file comprises a comprehensive command file and a boxing command file; operating the boxing command file to obtain a boxing file; the reconfigurable signals are put together and placed in the dynamic area, and the normal signals are put together and placed in the static area. In one specific example: creating a tcl.bat file as a comprehensive command file, creating a pack.tcl file as a boxing command file, and writing a tcl name to be called and a path for storing a result in the pack.tcl file; an edc file is created as a (first) constraint file in which a command is written, (the command content includes the name of the parent run, the extent of the dynamic zone). And running the pack.tcl file to obtain a pcblock file, namely a boxing file, wherein a dynamic area and a static area in the pcblock file can be boxed separately. And the normal signal and the reconfigurable signal of the pcblock file are boxed correctly through the added command. The reconfigurable signals are put together in the dynamic area, and the normal signals are put together in the static area.

In this embodiment, the constraint files (the first constraint file and the second constraint file) when the parent run and the child run are executed are both in the file format edc of identifying and reading supported by the programmable logic chip development software eLinx. In some embodiments, the first constraint file and the second constraint file may be files with different preset formats, or may not be an edc file, and a file with another format, for example, a qsf file, is used as the constraint file, which is not limited in the specific case.

In some specific examples, after obtaining the pcblock file, judging whether the generation of the pcblock file is successful, creating a route.tcl file after the generation of the pcblock file is successful, writing a command into the route.tcl file, and running the route.tcl file to obtain a place and a route file. And (5) completing the boxing, layout and wiring of the parent run. The condition for judging whether the generation of the pcblock file is successful is that the pcblock file is under the syhth_1 folder of the father run.

Some specific examples of the process of executing the parent run include:

write command in qsf file (pin configuration file):

qsf.write(f'set_global_assignment name PROJECT_OUTPUT_DIRECTORY "{proj_info[0]}/{proj_info[1]}.runs/synth_{device0}"\n')

qsf.write(f'set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id "{top_module}"\n')

qsf.write(f'set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id "{top_module}"\n')

qsf.write(f'set_global_assignment -name PARTITION_COLOR 39423 -section_id "{top_module}"\n')

qsf.write(f'set_instance_assignment -name PARTITION_HIERARCHY 5GHctXA2Z6 -to "{top_module}" -section_id "{top_module}"\n')

where device0 is the name of the parent run and top_module is the name of the exemplary reconfigurable module.

The commands written in the edc file (first constraint file) are as follows:

f.write(f"set_global_assignment -name PR_FUNCTION 1 \n")

f.write(f"set_global_assignment -name FATHER_PR_SYN synth_1 \n")

f.write(f"set_global_assignment -name FATHER_PR_IMP imple_1 \n")

f.write(f"set_global_assignment-nameSET_PR 1/test/test_PR/5_17_12_20/{top_module}")

PR_FUNCTION 1 is the name of the parent run representing the reconfigurable project, synth_1 is the name of the synchronization of the parent run, image_1 is the name of the synchronization of the parent run, 5_17_12_20 is the range of the dynamic area, and top_module is the name of the reconfigurable module.

The obtained pcblock file comprises the steps of synchronously and respectively carrying out dynamic area and static area boxing, and the code of the example comprises the steps of:

alm_molecule_0_10

\divclk:inst_divclk|counter[20]~I

\divclk:inst_divclk|counter[22]~I

GROUP_END

alm_molecule_0_11

\divclk:inst_divclk|counter[19]~I

\divclk:inst_divclk|counter[1]~I

GROUP_END

dynamic zone boxing:

alm_molecule_1_24

\count_down_PR:inst_count|count_out[3]~2_I

\count_down_PR:inst_count|count_out[2]~1_I

GROUP_END

alm_molecule_1_23

\count_down_PR:inst_count|count_out[1]~0_I

\count_down_PR:inst_count|count_out[0]~3_I

GROUP_END

the obtained route file: net 11 \cnt16[3]

Normal signal:

node 6_17_496: SOURCE (6, 17) id:4 capacity:3 cn:24

node 6_17_497: OPIN (6, 17) id:0 capacity:3

node 6_17_500: OPIN (6, 17) id:0 capacity:1

node 6_17_783: CHAN (6, 17) id:-1 capacity:1

node 6_18_847: CHAN (6, 18) id:85 capacity:1

node 6_18_740: CHAN (6, 18) id:0 capacity:1

node 6_18_277: IPIN (6, 18) id:0 capacity:1

node 6_18_276: SINK (6, 18) id:11 capacity:1 cn:23

reconfigurable signal:

net 13:\count_down_PR:inst_count|count_out[0]~3

node 6_18_437: SOURCE (6, 18) id:5 capacity:3 cn:23

node 6_18_438: OPIN (6, 18) id:0 capacity:3

node 6_18_440: OPIN (6, 18) id:0 capacity:1

node 7_18_42: CHAN (7, 18) id:-1 capacity:1

node 7_17_928: CHAN (7, 17) id:-1 capacity:1

node 6_17_875: CHAN (6, 17) id:85 capacity:1

node 6_17_707: CHAN (6, 17) id:0 capacity:1

node 6_17_481: IPIN (6, 17) id:0 capacity:1

node 6_17_480: SINK (6, 17) id:17 capacity:1 cn:24

unlike conventional route without reconfigurable signal, in this embodiment, there is PR in reconfigurable signal in example route, normal signal is not, and the function of distinguishing between them in this embodiment is: the reconfigurable signal can only be routed in the dynamic region and not in the static region.

In this embodiment, after the parent run is executed, it is determined whether the execution is successful, if the execution is successful, the child run is continued, and if the problem is not successful, the execution is directly ended.

In the case of the specific example, the execution of the child run is also using the python os module (operating system interface module) to create the result deposit file for the child run. A second command file is created that includes a file of pin configurations, in the example case a file of pin configurations, qsf file. Creating the second command file includes creating qsf file, tcl.bat, and pack.tcl file. In the example case qsf, in addition to the basic command, a path for storing the file is also put in the file, the name of tcl to be written in the pack. By running the pack. Tcl file, a pcblock file can be obtained.

Also in some examples, after determining that the pcblock file is successfully generated, creating a route.tcl file, writing a command into the route.tcl file, and running the route.tcl file to obtain the place and route files. To this end, the boxing, placement and routing of the child run are all completed.

One example of a basic command is as follows:

Source $vecdir/retertg.srcs/constrs_1/new/config_1.edc

Read_sdc $vecdir/retertg.srcs/constrs_1/new/config_1.edc

Set_global_assignment -name file $vecdir/retertg.srcs/constrs_1/new/config_1.edc

some examples place a path to deposit a file in a constraint file. The function is to save the file generated by the run sub run under the path. In the example case, in executing the child run, the qsf file command is written:

qsf.write(f'set_global_assignment-namePROJECT_OUTPUT_DIRECTORY "{proj_info[0]}/{proj_info[1]}.runs/synth_{device0}_child"\n')

writing an edc file command:

f.write(f"set_global_assignment -name PR_FUNCTION 2 \n")

f.write(f"set_global_assignment -name FATHER_PR_SYN synth_1_child\n”)

f.write(f"set_global_assignment -name FATHER_PR_IMP imple_1_child\n”)

f.write(f"set_global_assignment-nameSET_PR 1/test/test_PR/5_17_12_20/{top_module}\n")

f.write(f'set_global_assignment-name REFERENCE_CHECKPOINT_FILE "{proj_info[0]}/{proj_info[1]}.runs/imple_{device[2]}/{proj_info[1]}_eHiChip9_EQ9HL20-T.ecp"')

PR_FUNCTION 2 represents a reconfigurable FUNCTION child run, synth_1_child is the synthenis name of the child run, synth_1_child is the materialization of the child run, proj_info [0] }/{ proj_info [1] }, run/synth_ { device0} _child is the path of the child run, and eHiChip9_EQ9HL20-T.ecp is the file generated by the parent run.

In this embodiment, as shown in fig. 2, the sub run is executed, and then whether the sub run is successful is determined, if the sub run is successful, the finally generated file is stored in four folders, and the flow is ended. Example folder names are: synth_1, example_1, synth_1_child, example_1_child.

Wherein, synth_1 is a folder for storing results after parent run running synchronization, image_1 is a folder for storing results after parent run running animation, synth_1_child is a file for storing results after child run running synchronization, and image_1_child is a file for storing results after child run running animation. In some embodiments, if not successful, the process is directly ended and an error is reported.

In this embodiment, by automatically selecting a circuit that meets the reconfigurable function to randomly modify the logic of the module to be reconfigurable, thousands of circuits exist in the circuits that can be operated in this example, and the coverage rate of the test can reach more than 90%.

The use of certain conventional english terms or letters for the sake of clarity of description of the invention is intended to be exemplary only and not limiting of the interpretation or particular use, and should not be taken to limit the scope of the invention in terms of its possible chinese translations or specific letters.

Claims

An automated method for eda software reconfigurable functions, wherein the recording of a content to be reconfigured as a parent run and the replacing of a content to be reconfigured as a child run comprises:

screening a circuit conforming to a reconfigurable function in a circuit library as a target circuit, and acquiring a verilog file in the target circuit as a file of a father run;

modifying logic in the file of the father run to generate a new verilog file as a file of the child run;

acquiring and storing all effective information in the target circuit, wherein the effective information comprises a circuit path, the names of the files of the father run and the names of the files of the son run;

executing the parent run and the child run, including: writing a reconfigurable command into a constraint file; randomly designating the range of a dynamic region conforming to a rule, carrying out boxing, layout and wiring on the files of the father run in a static region, and carrying out boxing, layout and wiring on the files of the son run in the dynamic region; wherein, the liquid crystal display device comprises a liquid crystal display device,

the constraint files comprise a first constraint file and a second constraint file;

the method for executing the father run comprises the following steps: creating a result storage file of a father run; writing a reconfigurable command into the first constraint file; creating a first command file; the first command file comprises a comprehensive command file and a boxing command file; operating the boxing command file to obtain a boxing file; placing the reconfigurable signals together in a dynamic area, placing the normal signals together in a static area;

the method for executing the child run comprises the following steps: creating a result storage file of a child run; creating a second command file, wherein the second command file comprises a file of pin configuration; writing the path for storing the file into the file of the pin configuration; creating a file with a second preset format as the second constraint file, and writing a command in the second constraint file, wherein the command content comprises the child run name, the dynamic area range and the authorized file of the father run.
2. The EDA software reconfigurable functional automation method of claim 1, wherein: the criteria for the screening were: at least one circuit should be nested in the tested circuit.
3. The EDA software reconfigurable functional automation method of claim 1, wherein: the range of the dynamic area conforming to the rule means that the range of the dynamic area is within the range of the programmable logic module of the target circuit and does not comprise the input-output module and the data processing module of the target circuit.
4. The EDA software reconfigurable functional automation method of claim 1, wherein: the process of obtaining the file of the father run comprises the following steps: traversing a circuit library file to obtain the target circuit, wherein a plurality of verilog files are instantiated in the target circuit; traversing the names of the verilog files in the target circuit, and randomly extracting the verilog files inside the target circuit to serve as a reconfigurable module, namely the file of the father run.
5. The EDA software reconfigurable functional automation method of claim 1, wherein: the method for acquiring and storing all the effective information in the target circuit comprises the following steps: and generating a character string and a list, wherein the character string represents the names of the files of the child run, and the list is a path of the files of the child run and the files of the father run stored in a list form.
6. The automated EDA software reconfigurable functional method of any of claims 1-5, wherein the process of obtaining the case file comprises: creating the integrated command file and the boxing command file respectively; and writing the name of the command to be called and the path for storing the result in the boxed command file.
7. The EDA software reconfigurable functional automation method of any of claims 1-5, wherein writing the first constraint file comprises: creating a file with a first preset format as the first constraint file; writing a command in the first constraint file, wherein the command content comprises: the name of the parent run, the range of the dynamic zone.
8. The automated EDA software reconfigurable functional method of any of claims 1-5, wherein the obtaining of the case file is followed by: judging whether the generation of the boxing file is successful, if so, creating a wiring command file, writing a command into the wiring command file, and operating the wiring command file to obtain a layout file and a wiring file.
9. The EDA software reconfigurable functional automation method of any of claims 1-5, wherein the first constraint file and the second constraint file are files supporting different automation design software read formats.