JP2010118082A - Information processing apparatus and program verifying method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processing apparatus achieving low-cost operation verification in programs processed in parallel. <P>SOLUTION: A parallel processing verification part 230 of a runtime library 200 saves data in a work memory for all inputs before executing each serial basic module 101. After saving the data, the parallel processing verification part 230 executes the serial basic modules 101, and after that, whether all the saved data are completely match original data is checked. If there is a mismatch, the parallel processing verification part 230 executes error processing so as to display a warning message, for example, and to forcibly terminate the program. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a program verification technique suitable for application to, for example, a computer having a CPU incorporating a plurality of CPU cores, a computer having a plurality of CPUs, and the like.

  In recent years, various types of personal computers (personal computers) such as notebook types and desktop types have been widely used. In this type of computer, for example, high-definition moving image data is reproduced by software, and the demand for information processing capability is increasing as it approaches the limit of CPU performance improvement.

  For this reason, for example, computers equipped with a plurality of CPUs or recently equipped with a CPU incorporating a plurality of CPU cores have appeared. That is, by parallel processing the program, the required time is shortened, thereby improving the performance of the computer. Various mechanisms for efficiently performing parallel processing of programs have been proposed (see, for example, Patent Document 1).

JP 2005-258920 A

  One form of parallel processing of a program is to assign each processing unit in the program to an execution unit (in a computer equipped with a plurality of CPUs, an assignment is made to each CPU and a CPU incorporating a plurality of CPU cores is installed. In the computer, it is composed of two components: a runtime process including a scheduler (assigned to each CPU core) and a processing unit operating on each execution unit.

  By the way, in order to process a program in parallel, it is necessary for each processing unit operating in parallel to maintain an independent relationship. For example, when the output data of the processing unit A is input and the processing unit B and the processing unit C are executed, the result of each of the processing unit B and the processing unit C is determined only by the output data of the processing unit A. Must be. For this reason, the area on the system memory in which the input data of each processing unit is held must be managed as a read-only, that is, non-rewritable area when each processing unit is executed. For example, if the processing unit B that has started execution overwrites the input data, it will affect the result of the processing unit C that has started execution thereafter.

  When such an event does not occur, that is, when the validity of a program is verified, a test code has been embedded in the program until now. However, this work has a problem that it costs more work than programming. In parallel processing, there is a problem that the reproducibility of defects is low due to the problem of operation timing, and debugging becomes difficult.

  Furthermore, in order to process a program in parallel, it is necessary to verify that each processing unit of the program has re-entrance considering the case where the same basic module is called simultaneously from multiple execution units. The verification also has the same problem as described above.

  The present invention has been made in consideration of such circumstances, and an object of the present invention is to provide an information processing apparatus and a program verification method that realizes cost reduction of operation verification in a program to be processed in parallel.

  In order to achieve the above-described object, an information processing apparatus according to the present invention uses a plurality of execution units, a system memory shared by the plurality of execution units, and output data of a preceding basic module as input data, and In order to execute in parallel by the plurality of execution units a program that is divided into a plurality of basic modules that do not need to be synchronized with other modules and in which execution order constraints of the plurality of basic modules are defined A scheduler that controls allocation of the plurality of basic modules to the plurality of execution units based on order constraints, the scheduler for each of the plurality of execution units prior to execution of the basic module, The system that each execution unit inputs as input data of the basic module Data in the area on the system memory is copied and saved in another area on the system memory, and after execution of the basic module, the data in the area on the system memory input by each execution unit as input data of the basic module And verifying means for verifying that the basic module has not overwritten the input data by comparing the data saved in another area on the system memory.

  The information processing apparatus according to the present invention uses a plurality of execution units, a system memory shared by the plurality of execution units, and output data of a preceding basic module as input data, and is synchronized with other modules. In order to execute a program that is divided into a plurality of basic modules that do not need to be taken and that defines execution order constraints of the plurality of basic modules in parallel by the plurality of execution units, based on the execution order constraints, A scheduler for controlling allocation of the plurality of basic modules to a plurality of execution units, and the scheduler allocates the basic module to any execution unit of the plurality of execution units for execution. Any execution unit inputs as input data of the basic module The same basic module as the basic module having the same data in the area on the system memory as input data is assigned to another execution unit and executed separately. After the execution of the two same basic modules, the two basic modules Verifying means for comparing the data in two areas on the system memory output by each execution unit as the output data of the module and verifying that the basic module obtains the same output data for the same input data It is characterized by having.

  According to the present invention, it is possible to realize cost reduction of operation verification in a program to be processed in parallel.

The figure which shows an example of the system configuration | structure of the information processing apparatus which concerns on embodiment of this invention. The figure for demonstrating schematic structure of the program of the parallel processing specification performed by the information processing apparatus of this embodiment. The figure which shows general multithread processing. The figure which shows the relationship between the serial basic module which comprises the program run by the information processing apparatus of this embodiment, and parallel execution control description. The figure for demonstrating the parallel execution control description of the program run by the information processing apparatus of this embodiment. The figure for demonstrating the parallel processing control of the program which the runtime library which operate | moves on the information processing apparatus of this embodiment performs. The figure which shows the operation state of the runtime library on the information processing apparatus of this embodiment. FIG. 3 is a diagram showing functional blocks of a runtime library that operates on the information processing apparatus according to the embodiment. The figure which shows a memory model when a parallel program operate | moves. The figure for demonstrating the 1st operation | movement of the parallel processing verification which the runtime library which operate | moves on the information processing apparatus of this embodiment performs. The figure for demonstrating the 2nd operation | movement of the parallel processing verification which the runtime library which operate | moves on the information processing apparatus of this embodiment performs. The figure for demonstrating the example in case the runtime library which operate | moves on the information processing apparatus of this embodiment advances the 1st and 2nd operation | movement of parallel processing verification simultaneously. 6 is a flowchart showing a first operation flow of parallel processing verification executed by a runtime library operating on the information processing apparatus according to the embodiment. 10 is a flowchart showing a second operation flow of parallel processing verification executed by a runtime library operating on the information processing apparatus according to the embodiment. The 1st figure for demonstrating the modification of the parallel processing verification which the runtime library which operate | moves on the information processing apparatus of this embodiment performs. The 2nd figure for demonstrating the modification of the parallel processing verification which the runtime library which operate | moves on the information processing apparatus of this embodiment performs.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram illustrating an example of a system configuration of the information processing apparatus according to the present embodiment. This information processing apparatus is realized as a so-called personal computer such as a notebook type or a desktop type. As shown in FIG. 1, the computer includes a processor 1, a main memory 2, and a hard disk drive (HDD) 3, which are connected to each other via an internal bus.

  The processor 1 is a central processing unit (CPU) that controls execution of a program loaded from the HDD 3 to the main memory, and includes a plurality of cores 11 that are arithmetic circuits (CPU cores) of the main part.

  The main memory 2 is a storage device made of, for example, a semiconductor that can be accessed by the processor 1. On the other hand, the HDD 3 is a low-speed and large-capacity storage medium (compared to the main memory 2) that plays a role of auxiliary storage in the computer.

  Although not shown, an input / output device such as a display for displaying a processing result of the program by the processor 1 and a keyboard for inputting processing data, for example, is further provided in the case of a notebook type. For example, in the case of a desktop type, it is externally connected by a cable or the like.

  The computer equipped with the processor 1 incorporating a plurality of cores 11 can execute a plurality of programs in parallel, and can also execute a plurality of processes in one program in parallel. Here, with reference to FIG. 2, a schematic configuration of a parallel processing specification program executed by the computer will be described.

  As shown in FIG. 2, a parallel processing specification execution program 100 executed by the computer includes a plurality of serial basic modules 101 and a parallel definition that defines the order in which the serial basic modules 101 should be executed. And an execution control description 102.

  In so-called multithread processing, generally, as shown in FIG. 3, each thread performs processing while maintaining synchronization (including communication) with other threads, that is, maintaining the integrity of the entire program. Let it go. Therefore, it is possible that the expected parallel performance cannot be obtained if synchronization waits occur frequently.

  Therefore, in this embodiment, as shown in FIG. 4, a plurality of serial basic modules 101 are created by dividing a program into processing units that can be executed asynchronously without having to synchronize with other modules. At the same time, a parallel execution control description 102 that defines constraints on the execution order of the plurality of serial basic modules 101 is created. For parallel execution control, each serial basic module 101 is represented as a node. Thus, the serial basic module refers to a module of a processing unit that can be executed asynchronously with other modules. Next, the parallel execution control description 102 will be described with reference to FIG.

  FIG. 5A is a conceptual diagram of a node representing a certain series basic module 101. As shown in the figure, each serial basic module 101 can be regarded as a node having a link to a preceding node and a connector to a subsequent node. The parallel execution control description 102 defines the execution order of the plurality of serial basic modules 101 by writing link information to the preceding node for each serial basic module 101. FIG. 5B is a diagram illustrating a parallel execution control description relating to a certain serial basic module 101. As illustrated, the serial basic module ID that is each identifier and the preceding node of the serial basic module 101 are shown. Link information is written. In addition, information such as output buffer type and cost is also described.

  Next, how the computer executes the execution program 100 having a unique configuration composed of the plurality of serial basic modules 101 and the parallel execution control description 102 will be described.

  In order to perform parallel processing on the execution program 100 having such a unique configuration, a runtime library 200 shown in FIG. 6 is prepared in this computer. The runtime library 200 has a function as a scheduler, and a parallel execution control description 102 is given as graph data structure generation information 201. The parallel execution control description 102 is created using a functional language, for example, and is converted into graph data structure generation information 201 by a translator.

  When some data is input, it is necessary to execute some serial basic modules 101 for processing this data. In each case, the runtime library 200 uses the graph data structure generation information 201 to execute the graph data structure 202. Will be generated and updated dynamically. The graph data structure 202 is graph data indicating the context of the node group that is appropriately executed from time to time, and the runtime library 200 is waiting for execution as well as the context between the nodes to be added. Considering the context between nodes, the node group is added to the graph data structure 202.

  In addition, when the execution of a certain node is completed, the runtime library 200 deletes this node from the graph data structure 202, sets this node as a preceding node, and there are no other preceding nodes, or other preceding nodes. Is checked, and if there is a subsequent node that satisfies this condition, that node is assigned to one of the cores 11.

  Due to the function of the runtime library 200, parallel execution of the plurality of serial basic modules 101 based on the parallel execution control description 102 proceeds without contradiction. The runtime library 200 is called exclusively after the execution of the serial basic module 101 is completed, performs input / output check, graph data update, and selection of the serial basic module 101 to be executed next, and returns. On the core 11, the selected serial basic module 101 is executed. Another core calls the runtime library 200 one after another to obtain the serial basic module 101 to be executed next and execute it. Since exclusive control between threads is limited only to selection of a node from the graph data structure 202 and update of the graph data structure by the runtime library 200 (see FIG. 7), the general multithread shown in FIG. High parallel performance is achieved compared to processing.

  In this way, by dividing the program into processing units that can be executed asynchronously, a plurality of serial basic modules 101 are created, and the runtime library 200 orders the plurality of serial basic modules 101 into the plurality of cores 11 in order. The computer 1 that is often assigned provides a mechanism for detecting a problem that the serial basic module 101 overwrites input data without rewriting the source code during program execution. The computer 1 also provides a mechanism for checking that there is re-entrance when the same serial basic module 101 is simultaneously called from a plurality of cores 11. Hereinafter, this mechanism will be described in detail.

  FIG. 8 is a functional block diagram of the runtime library 200.

  As illustrated in FIG. 8, the runtime library 200 includes a node generation unit 210, a graph structure interpretation execution engine 220, and a parallel processing verification unit 230.

  The above-described dynamic generation / update of the graph data structure 202 based on the graph data structure generation information 201 by the runtime library 200 and the assignment control of the node to the core 11 using the graph data structure 202 are as follows: This is realized by the generation unit 210 and the graph structure interpretation execution engine 220. Then, the parallel processing verification unit 230 performs verification of the parallel processing realized by the node generation unit 210 and the graph structure interpretation execution engine 220.

  FIG. 9 shows a memory model when a parallel program operates. In order for programs to operate in parallel, the processes that operate in parallel must maintain an independent relationship. In the graph-based parallel processing, the execution result of the preceding node serving as input data is managed as a read-only, that is, non-rewritable area. In addition, the area where the value is written in the serial basic module 101 is only the result output buffer. By doing so, the execution of the serial basic module 101 is determined by the input data alone, and can be prevented from interfering with the operations of the other serial basic modules 101.

  However, even if such a restriction is provided, if the implementation of the serial basic module 101 is described in C language or C ++ language to achieve performance, the compiler cannot check this restriction. The program loader can allocate data to the read-only section depending on the address space allocation. However, since the serial basic module 101 of the preceding node writes the result, simple hardware protection is not sufficient.

  Therefore, the parallel processing verification unit 230 of the runtime library 200 first checks that there is no change in input data during the execution of the serial basic module 101. More specifically, as shown in FIG. 10, before the execution of each serial basic module 101, the execution result of the preceding node as an input is saved in the working memory, and the execution of the serial basic module 101 is finished. At the time, the original input data is compared with the saved data, and it is checked that there is no change in the input data. Since the runtime library 200 is a part that can be used in common for all parallel programs, it is possible to save time and effort to embed such a check code in the source code every time the parallel program is implemented, thereby improving development efficiency. In addition, since test code implementation omissions can be prevented, exhaustive testing is possible, and highly reliable programs can be created.

  Further, the parallel processing verification unit 230 of the runtime library 200 not only monitors the change of input data, but secondly checks the re-entrance property (also thread-safe) of the serial basic module 101. More specifically, as shown in FIG. 11, at the time of executing each serial basic module 101, two buffers for output of results (which can also be regarded as objects) are prepared, and the same basic input is connected to the serial basic at the same time. Module 101 is executed and the two results are compared. If the results match, discard one of the results and continue the process. This allows verification to proceed without interruption as long as the test passes.

  Note that the check that there is no change in input data shown in FIG. 10 and the re-entrance check shown in FIG. 11 can be performed simultaneously. In this case, as shown in FIG. 12, before the execution of each serial basic module 101, the execution result of the preceding node to be input is saved in the working memory, and two result output buffers are prepared. The serial basic module 101 is input with the input data and the saved data as inputs. Thus, after the execution, the original input data and the saved data can be compared to check that there is no change in the input data, and by comparing the two results, You can check the entrance.

  FIG. 13 is a flowchart showing the flow of the first operation of the parallel processing verification executed by the computer.

  The parallel processing verification unit 230 of the runtime library 200 saves data to the working memory for all inputs before the execution of each serial basic module 101 (step A1).

  After saving the data, the parallel processing verification unit 230 executes the serial basic module 101 (step A2), and checks whether the original input and the saved data all match after the execution (step A3). ). When a mismatch is detected (NO in step A3), the parallel processing verification unit 230 executes error processing such as displaying a warning message and forcibly terminating the execution of the program (step A4).

  FIG. 14 is a flowchart showing a second operation flow of the parallel processing verification executed by the computer.

  The parallel processing verification unit 230 of the runtime library 200 secures another result output buffer when each serial basic module 101 is executed (step B1), and executes two serial basic modules 101 (step B2). .

  After the execution, the parallel processing verification unit 230 checks whether or not these two results match (step B3). If a mismatch is detected (NO in step B3), the parallel processing verification unit 230, for example, displays a warning message. Is displayed and error processing such as forcibly terminating the execution of the program is executed (step B4). When the match is confirmed (YES in step B3), the parallel processing verification unit 230 releases one of the results (step B5) and continues execution of the program.

  As described above, by installing the parallel processing verification unit 230 that performs parallel processing verification in the runtime library 200, the computer can realize cost reduction of operation verification in a parallel processing program.

  In the above, an example of performing the overwrite check of the input data of the serial basic module 101 and the reentrant check of the serial basic module 101 has been described. Further, a potential timing problem due to parallel processing is discovered early. It is also effective to provide the parallel processing verification unit 230 with a mechanism for this.

  For example, a table for holding the average execution time of each serial basic module 101 as shown in FIG. 15 is managed, and the procedure as shown in FIG. 16 is performed (within an appropriate range derived from the average execution time). By providing the parallel processing verification unit 230 with a function of inserting a random waiting time for delaying the execution timing of each serial basic module 101, it is possible to provide a mechanism for identifying a problem location when a malfunction occurs due to a timing problem.

  As described above, the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

DESCRIPTION OF SYMBOLS 1 ... Processor, 2 ... Main memory, 3 ... Hard disk drive (HDD), 11 ... Core, 100 ... Execution program, 101 ... Serial basic module, 102 ... Parallel execution control description, 200 ... Runtime library, 201 ... Graph data structure Generation information, 202 ... graph data structure, 210 ... node generation unit, 220 ... graph structure interpretation execution engine, 230 ... parallel processing verification unit.

Claims (11)

Multiple execution units;
System memory shared by the plurality of execution units;
A program in which the output data of the preceding basic module is input data and is divided into a plurality of basic modules that do not need to be synchronized with other modules, and constraints on the execution order of the plurality of basic modules are defined. A scheduler for controlling the allocation of the plurality of basic modules to the plurality of execution units based on the execution order constraint for parallel execution by the plurality of execution units;
Comprising
The scheduler
For each of the plurality of execution units, before executing the basic module, the data in the area on the system memory that is input by each execution unit as input data of the basic module is copied to another area on the system memory. Compare the data in the area on the system memory input by each execution unit as the input data of the basic module with the data saved in another area on the system memory after the execution of the basic module. An information processing apparatus comprising verification means for verifying that the basic module does not overwrite input data.   When the value of the data in the area on the system memory input by each execution unit as the input data of the basic module is different from the data saved in another area on the system memory, The information processing apparatus according to claim 1, further comprising means for notifying that effect.   The basic module uses the data saved in another area on the system memory as input data when the verification module allocates and executes the basic module to any execution unit of the plurality of execution units. The same basic module is assigned to another execution unit and executed separately, and after the execution of the two same basic modules, two execution data output by the execution units as the output data of the two basic modules 2. The information processing apparatus according to claim 1, further comprising means for comparing the data in the areas and verifying that the basic module obtains the same output data for the same input data.   The information processing apparatus according to claim 1, further comprising a setting unit configured to set whether or not the verification unit functions. Multiple execution units;
System memory shared by the plurality of execution units;
A program in which the output data of the preceding basic module is input data and is divided into a plurality of basic modules that do not need to be synchronized with other modules, and constraints on the execution order of the plurality of basic modules are defined. A scheduler for controlling the allocation of the plurality of basic modules to the plurality of execution units based on the execution order constraint for parallel execution by the plurality of execution units;
Comprising
The scheduler
When the basic module is assigned to any execution unit of the plurality of execution units and executed, the data in the area on the system memory input by the execution unit as the input data of the basic module is the same. The same basic module as the basic module as input data is assigned to another execution unit and executed separately, and after execution of the two same basic modules, each execution unit outputs the output data of the two basic modules. An information processing apparatus comprising verification means for comparing data in two areas on the system memory and verifying that the basic module obtains the same output data for the same input data.   6. The information processing apparatus according to claim 5, wherein the verification means includes means for notifying the fact that data values in the two areas on the system memory outputted by the execution units are different. .   6. The information processing apparatus according to claim 5, further comprising setting means for setting whether or not the verification means functions. The scheduler
A measuring means for measuring an average execution time by the plurality of execution units of each of the plurality of basic modules;
The verification means randomly calculates a time for delaying the start of execution of the basic module using the average execution time of the basic module measured by the measurement means before the execution of the basic module. Including means for delaying the start of execution of the basic module,
The information processing apparatus according to claim 1, 3 or 5. Divided into multiple execution modules, system memory shared by the execution units, and output data of the preceding basic module as input data, and does not need to be synchronized with other modules The plurality of basic modules for the plurality of execution units is executed based on the execution order constraint, in order to execute the program in which the constraints on the execution order of the plurality of basic modules are defined in parallel by the plurality of execution units. A method for verifying a program in an information processing apparatus comprising a scheduler for controlling allocation of
The scheduler
For each of the plurality of execution units, before executing the basic module, the data in the area on the system memory that is input by each execution unit as input data of the basic module is copied to another area on the system memory. Compare the data in the area on the system memory input by each execution unit as the input data of the basic module with the data saved in another area on the system memory after the execution of the basic module. And verifying that the basic module does not overwrite the input data. Divided into multiple execution modules, system memory shared by the execution units, and output data of the preceding basic module as input data, and does not need to be synchronized with other modules The plurality of basic modules for the plurality of execution units is executed based on the execution order constraint, in order to execute the program in which the constraints on the execution order of the plurality of basic modules are defined in parallel by the plurality of execution units. A method for verifying a program in an information processing apparatus comprising a scheduler for controlling allocation of
The scheduler
When the basic module is assigned to any execution unit of the plurality of execution units and executed, the data in the area on the system memory input by the execution unit as the input data of the basic module is the same. The same basic module as the basic module as input data is assigned to another execution unit and executed separately. After execution of the two same basic modules, each execution unit outputs the output data of the two basic modules. A program verification method comprising: comparing data in two areas on the system memory to verify that the basic module obtains the same output data for the same input data. The scheduler
further,
Measuring an average execution time by the plurality of execution units of each of the plurality of basic modules;
Prior to the execution of the basic module, the average execution time of the basic module measured by the measuring unit is used to randomly calculate a time for delaying the execution start of the basic module. Delay execution start,
11. The program verification method according to claim 9, wherein the program is verified.

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