CN108011878A - The remote testing analogue system and method for facing multiple users design of hardware and software project - Google Patents
The remote testing analogue system and method for facing multiple users design of hardware and software project Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/02—Protocols based on web technology, e.g. hypertext transfer protocol [HTTP]
- H04L67/025—Protocols based on web technology, e.g. hypertext transfer protocol [HTTP] for remote control or remote monitoring of applications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
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- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/06—Protocols specially adapted for file transfer, e.g. file transfer protocol [FTP]
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/34—Network arrangements or protocols for supporting network services or applications involving the movement of software or configuration parameters
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Abstract
The invention belongs to the remote testing analogue system and method for technical field of integrated circuits, specially a kind of facing multiple users design of hardware and software project.The present invention has opened part FPGA resource using FPGA dynamic partial reconfigurable technology on FPGA based SoC to user, the management server carried using on piece realizes the test emulation of multi-user's software and hardware project, and project simulation result is stored under User Catalog, so that user's remote download emulates data.The remote emulation of the present invention can be applied to FPGA based SoC, have higher application value to the emulation of software and hardware project testing.It is of the invention that there is the features such as emulation cost is low, and server is built conveniently, and it is convenient to be wirelessly transferred, and partial code streams are configured without network delay, and hardware circuit code stream re-matching is low in energy consumption, the test of support software-hardware synergism project.
Description
Technical field
The invention belongs to technical field of integrated circuits, and in particular to utilize the dynamic restructuring technology of FPGA-based SoC
, the design of hardware and software project remote testing analogue system and method for facing multiple users.
Background technology
Field programmable gate array（Field Programmable Gate Array, FPGA）It is that one kind can pass through volume
Journey changes the chip of its internal circuit logic function.
High-performance FPG-based SoC (System on Chip) are the mainstream development trend of fpga chip in recent years, its
Feature is in addition to the programmable logic PL (Programmable Logic) of tradition FPGA, is also integrated with comprising ARM microprocessor
Chip processing system PS (Processing System), retain FPGA hardware programmable features itself outside, additionally it is possible to assist
More functions are realized with piece microprocessor, obtain better performance lifting, meet variation FPGA exploitation demands.
The design of Hardware/Software Collaborative Design project SW/HW (Software/Hardware) Co-design Project
It is complex.For designer, the software emulation of hardware design part is difficult to ensure that the logically true of actual physics signal,
And the equipment cost of system hardware test is high；Secondly, the configuration of conventional hardware circuit needs special host computer will by Ethernet
Code stream is downloaded in FPGA, wherein network connection inconvenience, and postpone it is difficult to predict, it is more difficult to software code and hardware design are existed
Time of running efficient combination.Therefore easy to use, the flexible software-hardware synergism engineering of operation a test method is lacked now
It is present problems faced.
Bibliography：
[1]Jiaqi Gu, Ruoyao Wang, Jian Wang, Jinmei Lai, Qinghua Duan, "Remote
Embedded Simulation System for SW/HW Co-design Based On Dynamic Partial
Reconfiguration," 2017 IEEE 12th International Conference on ASIC, 2017.
[2]Fei Chen, Yi Shan, Yu Zhang, Yu Wang, Hubertus Franke, Xiaotao Chang,
Kun Wang, “Enabling FPGAs in the Cloud”, the 11th ACM Conference onComputing
Frontiers, 2014, pp. 1-10
[3]A. A. Prince and V. Kartha, "A framework for remote and adaptive
partial reconfiguration of SoC based data acquisition systems under Linux,"
2015 10th International Symposium on Reconfigurable Communication-centric
Systems-on-Chip (ReCoSoC), Bremen, 2015, pp. 1-5.
[4]V. Mishra, Q. Chen and G. Zervas, "REoN: A protocol for reliable
software-defined FPGA partial reconfiguration over network," 2016
International Conference on ReConFigurable Computing and FPGAs (ReConFig),
Cancun, 2016, pp. 1-7. 。
The content of the invention
Present invention aims at the remote testing analogue system and side for providing a kind of facing multiple users design of hardware and software project
Method, can support multi-user access, support project remote testing, support the project testing of a variety of programming language fusions.
Design of hardware and software project remote testing analogue system provided by the invention, includes the client and system-on-chip at PC ends
Embedded testing server；Using FPGA dynamic partial reconfigurable technology to test user's open portion system-on-chip can
Programmed logic resource；
User uploads software and hardware engineering using client to test server, and sends test emulation request；
Test server responds multi-user access using the framework of I/O asynchronous multiplexings, while next using distributed task scheduling queue
On piece software and hardware resources are dispatched, to respond and perform the remote testing simulation request of multi-user；
System-on-chip is handled by the collaboration of microprocessor and programmable logic resource to complete the software and hardware engineering test of user
Emulation；
After user obtains the real-time informing of testing progress, test emulation is downloaded as a result, being finally completed embedded from test server
The remote testing of design of hardware and software project emulates.
In test emulation system of the present invention, functional unit necessary to can developing remote testing in client, it is such as local and
Server directory tree, engineering transmission option, test request option, real-time task push display etc., to lift this test convenient degree.
In order to handle multi-user test simulation request, embedded OS can be carried on system-on-chip, and in the behaviour
The network test server of multi-client access can be handled by making exploitation in system.Can development of user account on network test server
The functions such as the software and hardware resources scheduling of family and information management, user test request response and execution request.The embedded testing
Server can provide the management and dispatching of totality for this test method.
Meanwhile can be into order to reduce the equipment of traditional FPGA configuration, line limitation and cost, on embedded testing server
Row network configuration（As wireless network card configures）, can both realize access of the server itself to network, and can also realize user to test
The wireless network access of server.
Specifically, above-mentioned remote testing analogue system can be mounted in FPGA-based SoC, can be run thereon as embedded
The embedded OSs such as Linux, can provide good running environment for remote testing server.Pass through embedded OS
Carrying, it is possible to achieve the expansion to traditional bare nucleus system, such as easily support more flexible more programming language development environments, energy
The flexibility of software and hardware project development is enough lifted, the Development characteristics of disparity items are adapted to, so as to improve development efficiency and system
Expansibility.
In order to support the test emulation of Hardware/Software Collaborative Design engineering, user can be used into FPGA in FPGA-based SoC
Resource is divided into two parts with FPGA resource necessary to test system.Test system can be by user's hardware circuit with dynamic part weight
The mode of structure can be with realization be configured, so as to fulfill the test of Hardware/Software Collaborative Design engineering in user in FPGA resource region
Emulation.
Design of hardware and software project remote testing emulation mode based on above-mentioned test emulation system, comprises the following steps that：
（1）First, the related data for designing the software and hardware engineering completed and code are passed through network by user using above-mentioned client
Then remote transmission sends the request of engineering test to the operating system at test server end；
（2）After the engineering test request that test server response user sends, software and hardware is completed using distributed task scheduling queue
The scheduling of resource；Embedded OS performs Software for Design portion in project to be measured using the disposal ability of on piece microprocessor
The test divided；Microprocessor can control the partially dynamical reconfiguration of on piece programmable logic, the part marked off into above-mentioned FPGA
Restructural region programming user hardware circuit code stream.Microprocessor, can be in software code while software project is handled
Be in communication with each other under convenient control with programmable logic circuit by interconnection bus, for example, to programmable logic transmission data, from can
Programmed logic reads return data etc., so as to support the complete emulation testing of Hardware/Software Collaborative Design engineering.
In the present invention, the testing engineering data of user can pass through respective encrypted algorithm（Such as AES, RSA）Encryption, to increase
Add the information security of user test engineering.
, can be from storage facilities when testing software and hardware engineering in the present invention（Such as SD card）Read in bit stream file and pass
Enter PL, the partial bit stream file of engineering to be tested can be stored in advance in server end.
Compared with traditional soft hardware testing emulation mode, the present invention has the advantage that：
Present invention reduces the hardware cost needed for software and hardware project testing person, tester is only needed to remote embedded testing service
Device uploads design engineering, and sends test emulation request.
The present invention gives the test of software and hardware project to a FPGA-based SoC to handle, and utilizes PS in FPGA and PL
The characteristics of collaborative work, reduces when traditional PL is configured to the demand of the equipment such as host computer, cable, JTAG lines.
PS and PL cooperates on same FPGA-based SoC so that the emulation of software-hardware synergism engineering is more just
It is prompt.The part that nested hardware circuit accelerates in software code can easily obtain under the control of PS on piece programmable logic
Completely to realize.
The visible part of user and system resource mutually decouple in programmable logic resource, can not influence test system
User's hardware circuit is realized in the case of resource use itself.
Test server is equipped with embedded OS, can be that user engineering is tested compared to traditional bare nucleus system
The development environment of more flexible, convenient, vdiverse in function, more programming languages is provided.Be conducive to improve development efficiency, reduce test,
In the cycle of exploitation, adapt to the Development characteristics of disparity items, lifting system expansibility.
The testing engineering data of user can pass through respective encrypted algorithm（Such as AES, RSA）Encryption.This method can increase
The information security of user test engineering.
Compared to traditional FPGA application methods, by the present invention in that with asynchronous network server and distributed task scheduling queue
Management, scheduling, can support multi-user to access the software and hardware resources of server, and the multi-user that can solve FPGA resource uses punching
Prominent problem, can efficiently utilize FPGA Resources on Chip.
Can be from storage facilities during test software and hardware engineering（Such as SD card）Read in bit stream file and incoming PL, trial work to be measured
The partial bit stream file of journey can be stored in advance in server end.Compared to traditional FPGA configuration method, advantage be can eliminate it is soft
The network delay that code stream in hardware engineering test process is downloaded, can improve testing efficiency.
Technique effect
The present invention easily can build remote emulation server on mainstream FPGA-based SoC, handle the long-range of multi-user
Access, managing user information and data, the project simulation request of scheduling software-hardware synergism.This method applies the dynamic part of FPGA
Reconfiguration Technologies, there is that hardware circuit code stream re-matching speed is fast, low in energy consumption, support the test of software-hardware synergism project simulation, support more
The project testing of kind programming language synthesis, multi-user data information management is convenient, safety, portable height, versatile to wait spy
Point.
Brief description of the drawings
Fig. 1 software and hardware project remote emulation test platform work flow diagrams.
Fig. 2 built-in Linuxes build schematic block diagram.
Fig. 3 distributed task scheduling queue work principle schematics.
Embodiment
The multi-user's software and hardware project remote emulation test system flow chart built on FPGA-based SoC is shown in Fig. 1 institutes
Show.It is used below to be applied with hardware-accelerated Image Edge-Detection as test to be specifically described the content of the method for the present invention
The specific embodiment of method illustrates.
First, test emulation system hardware components are built
1. system-on-chip model selects
First, the equipment for selecting the system to carry is Xilinx Zynq-7000 AP (All Programmable) SoC Z-
7010 on ZYBO。
2.FPGA bit streams generate
The microprocessor of corresponding model is configured on Xilinx Vivado（Including interruption, clock, GPIO buses, interconnection matrix
Deng）.According to the Gaussian wave filters used in test application and Sobel filter write it is corresponding can dynamic re-matching it is hard
Part circuit code, is embedded into the way circuit of test system, generate respectively the FPGA portion bit stream of above-mentioned filter circuit with
And the way circuit FPGA bit streams with partial reconfiguration region.
3. built-in Linux operating system carries
Fig. 2 shows a kind of starting pinciple of built-in Linux operating system.Change embedded Linux kernel（Such as add nothing
Line network-driven configuration etc.）, and utilize ARM-Linux cross compiles chain compiling generation kernel mirror image file uImage.
For used in the present invention can partial reconfiguration region, in Linux device tree files add corresponding peripheral hardware and retouch
State, and compile generation device tree binary file.
For the linux kernel model used in the present invention, applicable u-boot loaders are selected, and compile generation to hold
Part u-boot.elf compose a piece of writing for the original upload of (SuSE) Linux OS.
The BOOT.bin binary files of specific format will be fused into maker of the above-mentioned file in Xilinx SDK.
Micro-SD cards are divided into EXT4 and FAT32 Liang Ge areas.The file of above-mentioned generation is stored in FAT32 subregions.
15.04 file system of Linaro Ubuntu is placed in EXT4 subregions.
The start-up mode of ZYBO development boards is set to start from SD card, built-in Linux operating system can be loaded after the power is turned on.
Next wireless network connection configuration can be easily carried out in an operating system so that test system can pass through
Realtek wireless network cards save cable between host computer and FPGA and connect to realize that long-distance user accesses the Wi-Fi of server
Equipment cost.
2nd, test emulation system software section is built
1. test and management server is built
The I/O asynchronous multiplexing network test servers using Linux EPOLL models are write using Python.Developed in server
Following functions：The instruction such as login, file transmission, project testing of long-distance user is handled, manages data, the information of multi-user.Clothes
The communication synthesis being engaged between device and client uses the Encryption Algorithm such as AES, RSA, it is ensured that network transfer speeds, enhancing multi-user's letter
Breath, the security of data.The runtime server in (SuSE) Linux OS, waits the remote access of user.
2. test system client is built
Using Python developing operations in the client software with graphic user interface of Windows operating system.In software
Functional unit necessary to developing remote testing（As local and server directory tree, engineering transmission option, test request option,
Real-time task push display etc.）.
Three, software and hardwares engineering tests emulate
1. engineering code pre-preparation to be measured
Using C, Python bilingual write image obscure, the software code of edge detection, will wherein filter main body operate
Replace with FPGA hardware realization.In code dynamic part weight is opened come register in control sheet using the mode of kernel file read-write
Structure function, and the partial code streams that Gaussian filter synthesis generates are passed through into DevC peripheral hardwares programming to FPGA dynamic reconfigurables area
In domain, afterwards by the virtual memory of the peripheral hardware address of cache of dynamic restructuring to PS ends, by virtual memory read-write come to FPGA
Hardware circuit transmits data, the gaussian filtering result that the FPGA that then reads back is calculated.After gaussian filtering, above-mentioned FPGA configurations are repeated
Step, in FPGA dynamic reconfigurables region programming Sobel filter circuits, and controls its data processing, side of finally reading back by PS
Data after edge detection.View data after processing is stored in the file mesh of the user in file system as engineering test result
In record.
2. remote control project testing
Remote testing server is logged in by the Account Logon mechanism of client, and obtains active user's catalogue.
The item code, data, partial code streams of above-mentioned pre-preparation are uploaded to clothes by the network transmission function of client
It is engaged in device under User Catalog.
Choose software and hardware project to be measured and send test execution request to server.
After server receives test request, using distributed task scheduling queue as shown in Figure 3, the resource of system-on-chip is dispatched
Access and use.According to scheduling of resource situation, the executive process of distributed task scheduling queue will run above-mentioned project software generation to be measured
Code, and, by network Real-time Feedback to subscription client. by the situation record of user items emulation in the database；
User can download test result file, data in the suitable time after being fed back from Server remote.
So far, above-mentioned software and hardware project testing demonstration example is illustrated and finished.
In above-mentioned implementation, each step can build environment according to real system and flexibly change.Such as, FPGA hardware
Circuit design can be according to actual platform resource, FPGA scales and server working mechanism flexible design；The reality of the webserver
Required function now can be arbitrarily developed in server OS；The client that user uses can be according to practical application institute
Need flexible design；Configuring the mode of FPGA can use long-range Wi-Fi to transmit, and can also use in document [2] [3] [4] and use
Ethernet code stream download etc.；The mode of dynamic re-matching can utilize various ways, such as the PCAP that Zynq 7000 is supported
PCIe buses that Bridge, UltraScale+ MPSoC are supported, configuration module ICAP Bridge etc. inside FPGA.
Claims (8)
1. a kind of remote testing analogue system of facing multiple users design of hardware and software project, it is characterised in that include the visitor at PC ends
Family end and the embedded testing server of system-on-chip；Using the technology of FPGA dynamic partial reconfigurable to test user opening portion
Divide the programmable logic resource of system-on-chip；Wherein：
The client uploads software and hardware engineering for user to test server, and sends test emulation request；
The test server responds multi-user access using the framework of I/O asynchronous multiplexings, while uses distributed task scheduling team
Arrange to dispatch on piece software and hardware resources, to respond and perform the remote testing simulation request of multi-user；
System-on-chip is handled by the collaboration of microprocessor and programmable logic resource to complete the software and hardware engineering test of user
Emulation；
After user obtains the real-time informing of testing progress, test emulation is downloaded as a result, being finally completed embedded from test server
The remote testing of design of hardware and software project emulates.
2. the remote testing analogue system of facing multiple users design of hardware and software project according to claim 1, its feature exist
In exploitation has functional unit necessary to remote testing in the client, including local and server directory tree, engineering are transmitted
Option, test request option, real-time task push display.
3. the remote testing analogue system of facing multiple users design of hardware and software project according to claim 2, its feature exist
In being equipped with embedded OS on system-on-chip, and exploitation has and can handle multi-client access in the operating system
Network test server；Exploitation has user account and information management, user test request response on network test server
And perform the software and hardware resources scheduling feature module of request.
4. the remote testing analogue system of facing multiple users design of hardware and software project according to claim 3, its feature exist
In can carry out network configuration on the embedded testing server, to realize access of the server itself to network, and realize
Wireless network access of the user to test server.
5. the remote testing analogue system of facing multiple users design of hardware and software project according to claim 4, its feature exist
In the remote testing analogue system is mounted in FPGA-based SoC, runs built-in Linux embedded operation system thereon
System；
User can be divided into two parts with FPGA resource necessary to FPGA resource and test system in FPGA-based SoC；
Can be with realization be configured in FPGA resource region, so that real in user in a manner of partially dynamical reconfiguration by user's hardware circuit
The test emulation of existing Hardware/Software Collaborative Design engineering.
6. the facing multiple users design of hardware and software project based on the remote testing analogue system described in one of claim 1-4 is remote
Journey test emulation method, it is characterised in that comprise the following steps that：
（1）First, the related data for designing the software and hardware engineering completed and code are passed through network remote by user using client
The operating system at test server end is transferred to, then sends the request of engineering test；
（2）After the engineering test request that test server response user sends, software and hardware is completed using distributed task scheduling queue
The scheduling of resource；Embedded OS performs Software for Design portion in project to be measured using the disposal ability of on piece microprocessor
The test divided；The partially dynamical reconfiguration of programmable logic in microprocessor control sheet, the part marked off into above-mentioned FPGA can
Reconstruction region programming user's hardware circuit code stream；Microprocessor is while software project is handled, in the convenient control of software code
System is lower and programmable logic circuit is in communication with each other by interconnection bus, including is patrolled to programmable logic transmission data, from programmable
Collect and read return data, so as to support the complete emulation testing of Hardware/Software Collaborative Design engineering.
7. the remote testing emulation mode of facing multiple users design of hardware and software project according to claim 6, its feature exist
In the testing engineering data of user pass through respective encrypted algorithm for encryption, to increase the information security of user test engineering.
8. the remote testing emulation mode of facing multiple users design of hardware and software project according to claim 6, its feature exist
In when testing software and hardware engineering, from storage facilities reading bit stream file and incoming PL, the partial bit stream of engineering to be tested
File is stored in advance in server end.
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