CN111427839B - Remote online configuration and debugging method for Intel SoC FPGA - Google Patents
Remote online configuration and debugging method for Intel SoC FPGA Download PDFInfo
- Publication number
- CN111427839B CN111427839B CN202010228285.XA CN202010228285A CN111427839B CN 111427839 B CN111427839 B CN 111427839B CN 202010228285 A CN202010228285 A CN 202010228285A CN 111427839 B CN111427839 B CN 111427839B
- Authority
- CN
- China
- Prior art keywords
- sld
- debugging
- soc fpga
- intel
- intel soc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000013461 design Methods 0.000 claims description 15
- 239000000523 sample Substances 0.000 claims description 8
- 230000003993 interaction Effects 0.000 claims description 7
- 238000002474 experimental method Methods 0.000 claims description 6
- 230000005540 biological transmission Effects 0.000 claims description 3
- 238000011161 development Methods 0.000 description 5
- 230000018109 developmental process Effects 0.000 description 5
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000033772 system development Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/177—Initialisation or configuration control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
- G06F9/4451—User profiles; Roaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44521—Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/02—Standardisation; Integration
- H04L41/0246—Exchanging or transporting network management information using the Internet; Embedding network management web servers in network elements; Web-services-based protocols
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/02—Standardisation; Integration
- H04L41/0246—Exchanging or transporting network management information using the Internet; Embedding network management web servers in network elements; Web-services-based protocols
- H04L41/0266—Exchanging or transporting network management information using the Internet; Embedding network management web servers in network elements; Web-services-based protocols using meta-data, objects or commands for formatting management information, e.g. using eXtensible markup language [XML]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/34—Network arrangements or protocols for supporting network services or applications involving the movement of software or configuration parameters
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computing Systems (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Debugging And Monitoring (AREA)
Abstract
The invention discloses a remote online configuration and debugging method of an Intel SoC FPGA, which comprises the following steps: s1, configuring an SLD application program and an Ethernet controller on an HPS side of an Intel SoC FPGA; s2, designing an Intel SoC FPGA, compiling to obtain a configuration file containing SLD debugging information, and downloading the configuration file into the Intel SoC FPGA; s3, converting the SLD debugging information in the configuration file into an Avalon-ST data packet so as to bridge bottom hardware and an SLD application program of the Intel SoC FPGA; s4, bridging an SLD Hub controller and an Ethernet controller of the Intel SoC FPGA through an SLD application program; and S5, accessing the SLD application program running on the HPS side of the Intel SoC FPGA in a network mode through the PC to perform online debugging. The invention combines the SLD debugging tool of the PC with the SLD Hub controller of the Intel SoC FPGA through an Ethernet TCP/IP protocol, provides hardware support, allows a plurality of nodes to share the access to a user debugging interface, is superior to the point-to-point debugging of the traditional JTAG mode, and has high universality.
Description
Technical Field
The invention relates to the technical field of debugging in the FPGA development process, in particular to a remote online configuration and debugging method of an Intel SoC FPGA.
Background
An FPGA (Field-Programmable Gate Array), i.e. a Field Programmable Gate Array, is a new SoC chip that is released by an Intel PSG (original Altera) and integrates an HPS (Hardware Processor System) hard core Processor and FPGA logic resources on a single chip. The HPS is based on an ARM core-A9 dual-core processor, and is also integrated with various high-performance peripherals such as an MMU (memory management unit), a DDR3 controller, a Nand FLASH controller and the like, and the HPS can run a Linux operating system. The HPS and the FPGA can work independently, and high-speed broadband data communication can be realized through high-performance AXI bus bridging. The Intel SoC FPGA not only has the flexible and efficient data operation and transaction processing capability of the ARM processor, but also integrates the high-speed parallel processing advantage of the FPGA.
As shown in fig. 1, a general configuration and debugging method of an Intel SoC FPGA includes: and connecting the PC with the FPGA device to be debugged by using a JTAG cable, and then debugging by using a debugging tool integrated in a Quartus development kit. However, in SoC FPGA hardware system development, multiple persons commonly cooperate to develop the method, and developers may be distributed in different places. In consideration of the fact that SoC FPGA development equipment is expensive, in order to save cost, one set of SoC FPGA development equipment cannot be guaranteed. In addition, in the FPGA teaching experiment, the student FPGA experiment operation can only be completed in the FPGA laboratory, and the experiment effect is low due to the development time of the laboratory. Therefore, it is a need to remotely configure and debug the FPGA system online via a network. The configuration and debugging mode of the conventional FPGA system is limited by the length of a JTAG cable, so that remote operation is difficult to realize.
At present, the existing method for remote debugging of an FPGA, for example, patent application No. 20151103058.7 describes a system and a method for remote debugging of an FPGA/CPLD, which mainly solve the problem that only pin signals can be observed, but internal signals of a chip cannot be observed to complete on-line logic analysis. For example, the patent application No. 201710252578.X describes an FPGA remote debugging system and a remote debugging method, which only support logic analysis and additionally require a target PC to be remotely located.
Most of the FPGA remote configuration and debugging methods on the market have single function, complex operation steps and redundant structures. The bottom layer depends on JATG protocol, JTAG is converted into USB or parallel port, an Intel JTAG simulator is required to be connected with FPGA point to point, universality is low, and time-sharing configuration and debugging of a plurality of PCs to the same FPGA cannot be realized.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the problems, the remote online configuration and debugging method of the Intel SoC FPGA is provided, and the remote online configuration and debugging of the FPGA without using a JTAG connector can be realized.
The technical scheme adopted by the invention is as follows:
a remote online configuration and debugging method for an Intel SoC FPGA comprises the following steps:
s1, configuring an SLD application program and an Ethernet controller for realizing data interaction with a PC (personal computer) through a TCP/IP (transmission control protocol/Internet protocol) on an HPS (host platform system) side of an Intel SoC FPGA (field programmable gate array);
s2, carrying out Intel SoC FPGA design on the PC, adding SLD debugging information by using an SLD debugging tool after the design is finished, obtaining a configuration file containing the SLD debugging information through compiling, and downloading and configuring the configuration file into the Intel SoC FPGA;
s3, an SLD Hub controller of the Intel SoC FPGA converts SLD debugging information in the configuration file into an Avalon-ST data packet so as to bridge bottom hardware and an SLD application program of the Intel SoC FPGA;
s4, bridging an SLD Hub controller and an Ethernet controller of the Intel SoC FPGA through an SLD application program, and enabling an SLD debugging tool of the PC to perform data interaction with the Intel SoC FPGA through a TCP/IP protocol;
and S5, accessing the SLD application program running on the HPS side of the Intel SoC FPGA in a network mode through the PC to perform online debugging.
Further, the method of S5 includes:
s51, connecting the PC and the Intel SoC FPGA through an Ethernet, so that the PC and the Intel SoC FPGA are in the same network segment;
s52, starting a design experiment, designing an Intel SoC FPGA on a PC, adding SLD debugging information by using an SLD debugging tool after the design is finished, obtaining a configuration file containing the SLD debugging information by compiling, downloading the configuration file and configuring the configuration file into the Intel SoC FPGA;
s53, starting remote debugging service, executing a remote debugging script command in SoC EDS software, and establishing remote connection;
s54, selecting an SLD Hub Controller System at a Hardware position in an SLD debugging tool, and starting debugging after successful loading;
and S55, verifying the designed experimental result, if the expected requirement is not met, skipping to the step S2, and after the PC machine modifies the Intel SoC FPGA design, re-executing the steps S52-S55.
In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:
the invention combines the SLD debugging tool of the PC with the SLD Hub controller of the Intel SoC FPGA through a non-JTAG channel chain, namely an Ethernet TCP/IP protocol, provides hardware support, allows a plurality of nodes to share the access to a user debugging interface, is superior to the point-to-point debugging of the traditional JTAG mode, and has high universality.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a block diagram of a conventional JTAG configured and debugged system.
Fig. 2 is a system block diagram of the remote online configuration and debugging method of the Intel SoC FPGA of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration only, not by way of limitation, i.e., the embodiments described are intended as a selection of the best mode contemplated for carrying out the invention, not as a full mode. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
The features and properties of the present invention are described in further detail below with reference to examples. In the embodiment, a PC and an Intel SoC FPGA are used for remote online configuration and debugging, wherein an SLD debugging tool adopted on the PC is an SLD System-level debugging tool In the query software, and the SLD debugging tools supported by the PC comprise a SignalTap II logic analyzer, an In-System resources and Probes System internal Signal source and Probe, a Memory Content Editor and a Signal Probe Signal Probe.
Example 1
The remote online configuration and debugging method for the Intel SoC FPGA provided by the embodiment comprises the following steps:
s1, configuring an SLD application program and an Ethernet controller for realizing data interaction with a PC (personal computer) through a TCP/IP (transmission control protocol/Internet protocol) on an HPS (host platform system) side of an Intel SoC FPGA (field programmable gate array); as shown in FIG. 2, at the HPS side of the Intel SoC FPGA, link APP is configured as SLD application, EMMC/Driver is configured as Ethernet controller, and another Driver is used for connecting the HPS of the Intel SoC FPGA with the FPGA. The SLD application is an application designed in a common programming language, and runs on an operating system on the HPS side. Preferably, the SLD application is set to run automatically upon power up.
S2, carrying out Intel SoC FPGA design on the PC, adding SLD debugging information by using an SLD debugging tool after the design is finished, obtaining a configuration file containing the SLD debugging information through compiling, and downloading and configuring the configuration file into the Intel SoC FPGA; generally, the configuration file is in the rbf format, and configuration software, such as an FPGA manager peripheral of the HPS, may be used to download and configure the configuration file into the Intel SoC FPGA.
S3, an SLD Hub controller of the Intel SoC FPGA converts SLD debugging information in the configuration file into an Avalon-ST data packet so as to bridge bottom hardware and an SLD application program of the Intel SoC FPGA;
s4, bridging an SLD Hub controller and an Ethernet controller of the Intel SoC FPGA through an SLD application program, and enabling an SLD debugging tool of the PC to perform data interaction with the Intel SoC FPGA through a TCP/IP protocol; after the SLD debugging tool of the PC and the Intel SoC FPGA can perform data interaction through a TCP/IP protocol, the SLD application program can pack data generated by the SLD Hub controller into a TCP/IP data packet, and the data is transmitted through the socket. Therefore, in the embodiment, the non-JTAG channel chain, i.e., the ethernet TCP/IP protocol, is used to combine the SLD debug tool of the PC with the SLD Hub controller of the Intel SoC FPGA, so as to provide hardware support, allow multiple nodes to share access to the user debug interface, and have better point-to-point debugging than the conventional JTAG method and high universality.
And S5, accessing an SLD application program running on an HPS side of the Intel SoC FPGA in a network mode through an SLD debugging tool of the PC to perform online debugging. The configuration of the Intel SoC FPGA is completed through the steps S1-S4, and when the Intel SoC FPGA is needed to be used for debugging, the remote online debugging can be realized by utilizing the SLD debugging tool only after the PC is connected with the Intel SoC FPGA through the Ethernet. The specific address, the method of S5 includes:
s51, connecting the PC with the Intel SoC FPGA through an Ethernet, so that the PC and the Intel SoC FPGA are in the same network segment;
s52, starting a design experiment, designing an Intel SoC FPGA on a PC, adding SLD debugging information by using an SLD debugging tool after the design is finished, obtaining a configuration file containing the SLD debugging information by compiling, downloading the configuration file and configuring the configuration file into the Intel SoC FPGA;
s53, starting remote debugging service, executing a remote debugging script command in SoC EDS software, and establishing remote connection;
s54, selecting an SLD Hub Controller System at a Hardware position in an SLD debugging tool, and starting debugging after successful loading;
and S55, verifying the designed experimental result, if the expected requirement is not met, skipping to the step S2, and after the PC machine modifies the Intel SoC FPGA design, re-executing the steps S52-S55.
The above description is intended to be illustrative of the preferred embodiment of the present invention and should not be taken as limiting the invention, but rather, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.
Claims (5)
1. A remote online configuration and debugging method for an Intel SoC FPGA is characterized by comprising the following steps:
s1, configuring an SLD application program and an Ethernet controller for realizing data interaction with a PC (personal computer) through a TCP/IP (transmission control protocol/Internet protocol) protocol on an HPS (host platform system) side of an Intel SoC FPGA (field programmable gate array);
s2, carrying out Intel SoC FPGA design on the PC, adding SLD debugging information by using an SLD debugging tool after the design is finished, obtaining a configuration file containing the SLD debugging information through compiling, and downloading and configuring the configuration file into the Intel SoC FPGA;
s3, an SLD Hub controller of the Intel SoC FPGA converts SLD debugging information in the configuration file into an Avalon-ST data packet so as to bridge bottom hardware and an SLD application program of the Intel SoC FPGA;
s4, bridging an SLD Hub controller and an Ethernet controller of the Intel SoC FPGA through an SLD application program, and enabling an SLD debugging tool of the PC to perform data interaction with the Intel SoC FPGA through a TCP/IP protocol;
s5, accessing an SLD application program running on an HPS side of the Intel SoC FPGA in a network mode through a PC (personal computer) for online debugging;
the method of S5 comprises:
s51, connecting the PC and the Intel SoC FPGA through an Ethernet, so that the PC and the Intel SoC FPGA are in the same network segment;
s52, starting a design experiment, designing an Intel SoC FPGA on a PC, adding SLD debugging information by using an SLD debugging tool after the design is finished, obtaining a configuration file containing the SLD debugging information by compiling, downloading the configuration file and configuring the configuration file into the Intel SoC FPGA;
s53, starting remote debugging service, executing a remote debugging script command in SoC EDS software, and establishing remote connection;
s54, selecting an SLD Hub Controller System at a Hardware position in an SLD debugging tool, and starting debugging after successful loading;
and S55, verifying the designed experimental result, if the expected requirement is not met, skipping to the step S2, and after the PC machine modifies the Intel SoC FPGA design, re-executing the steps S52-S55.
2. The remote online configuration and debugging method of Intel SoC FPGA of claim 1, wherein the SLD debugging tool is an SLD system-level debugging tool in the Quartus software.
3. The remote online configuration and debugging method of Intel SoC FPGA according to claim 2, wherein the SLD debugging tool comprises a SignalTap II logic analyzer, in-System resources and Probes System internal Signal Sources and Probes, memory Content Editor, signal Probe Signal Probe.
4. The remote online configuration and debugging method of the Intel SoC FPGA of claim 1, wherein the configuration file is in rbf format.
5. The remote online configuration and debugging method of an Intel SoC FPGA of claim 1, wherein said SLD application is configured to run automatically upon power up.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010228285.XA CN111427839B (en) | 2020-03-27 | 2020-03-27 | Remote online configuration and debugging method for Intel SoC FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010228285.XA CN111427839B (en) | 2020-03-27 | 2020-03-27 | Remote online configuration and debugging method for Intel SoC FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111427839A CN111427839A (en) | 2020-07-17 |
| CN111427839B true CN111427839B (en) | 2023-04-07 |
Family
ID=71549030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010228285.XA Active CN111427839B (en) | 2020-03-27 | 2020-03-27 | Remote online configuration and debugging method for Intel SoC FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111427839B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113268031A (en) * | 2021-06-07 | 2021-08-17 | 深圳市蔚来芯科技有限公司 | System and method for electronic equipment remote debugging tool |
| CN113504463A (en) * | 2021-07-02 | 2021-10-15 | 芯启源(上海)半导体科技有限公司 | Probe signal multiplexing method in FPGA prototype verification |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103617054A (en) * | 2013-11-15 | 2014-03-05 | 中国航空无线电电子研究所 | Device for remotely loading FPGA (field programmable gate array) configuration files and loading method |
| CN107122304A (en) * | 2017-05-03 | 2017-09-01 | 成都定为电子技术有限公司 | A kind of JTAG remote debugging methods |
| CN107566524A (en) * | 2017-10-11 | 2018-01-09 | 中船重工（武汉）凌久电子有限责任公司 | A kind of remote loading management system and remote loading management method based on Ethernet |
| CN107819656A (en) * | 2017-11-21 | 2018-03-20 | 上海航天测控通信研究所 | A kind of FPGA remote onlines deployment device and method based on RS422 and CAN |
| CN108011878A (en) * | 2017-11-29 | 2018-05-08 | 复旦大学 | The remote testing analogue system and method for facing multiple users design of hardware and software project |
| CN110442488A (en) * | 2019-07-02 | 2019-11-12 | 中国航空工业集团公司雷华电子技术研究所 | A method of Ethernet remote debugging FPGA is passed through based on Zynq platform |
-
2020
- 2020-03-27 CN CN202010228285.XA patent/CN111427839B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103617054A (en) * | 2013-11-15 | 2014-03-05 | 中国航空无线电电子研究所 | Device for remotely loading FPGA (field programmable gate array) configuration files and loading method |
| CN107122304A (en) * | 2017-05-03 | 2017-09-01 | 成都定为电子技术有限公司 | A kind of JTAG remote debugging methods |
| CN107566524A (en) * | 2017-10-11 | 2018-01-09 | 中船重工（武汉）凌久电子有限责任公司 | A kind of remote loading management system and remote loading management method based on Ethernet |
| CN107819656A (en) * | 2017-11-21 | 2018-03-20 | 上海航天测控通信研究所 | A kind of FPGA remote onlines deployment device and method based on RS422 and CAN |
| CN108011878A (en) * | 2017-11-29 | 2018-05-08 | 复旦大学 | The remote testing analogue system and method for facing multiple users design of hardware and software project |
| CN110442488A (en) * | 2019-07-02 | 2019-11-12 | 中国航空工业集团公司雷华电子技术研究所 | A method of Ethernet remote debugging FPGA is passed through based on Zynq platform |
Non-Patent Citations (4)
| Title |
|---|
| 一种基于CPCI总线和以太网的FPGA远程自动配置技术;叶彦;《电子技术》;20180925(第09期);94+98-100 * |
| 基于 Cyclone IV 的单核 FPGA 远程更新系统设计;徐晓康 等;《船电技术》;20200215;第40卷(第2期);59-61 * |
| 基于CAN和RS422实现FPGA远程调试与配置;周兴云等;《无线电工程》;20180205(第02期);76-80 * |
| 基于XVC网络协议的多FPGA远程更新与调试;薛乾等;《核技术》;20151210(第12期);37-41 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111427839A (en) | 2020-07-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112580295B (en) | Automatic verification method, system and device for multi-core SoC chip | |
| CN113330322B (en) | Automated test equipment using system-on-chip test controller | |
| JP4456420B2 (en) | Network-based hierarchical emulation system | |
| US12093631B2 (en) | Method, system and verifying platform for system on chip verification | |
| US20070016827A1 (en) | Systems and methods for providing remotely accessible in-system emulation and/or debugging | |
| CN102508753B (en) | IP (Internet protocol) core verification system | |
| CN101344899B (en) | Simulation test method and system of on-chip system | |
| JPH0769853B2 (en) | In-circuit emulator | |
| US10489543B1 (en) | Productivity platform using system-on-chip with programmable circuitry | |
| CN111427839B (en) | Remote online configuration and debugging method for Intel SoC FPGA | |
| EP1782204A2 (en) | Emulation and debug interfaces for testing an integrated circuit with an asynchronous microcontroller | |
| CN115496034A (en) | Multi-mode GPU joint simulation system | |
| US6442725B1 (en) | System and method for intelligent analysis probe | |
| JP2004178591A (en) | Progressive extended compression mask for dynamic trace | |
| CN116610590A (en) | Method and system for realizing remote debugging of multiple FPGAs based on ZYNQ platform | |
| CN117370093B (en) | Chip debugging method, device, equipment and storage medium | |
| JP2004178590A (en) | Address range comparator for detecting memory accesses of multi sizes by data matching qualification and full or partial ovrlap | |
| JP2005346517A (en) | Verification device and verification method | |
| Chang et al. | A unified GDB-based source-transaction level SW/HW co-debugging | |
| CN108334313A (en) | Continuous integrating method, apparatus and code management system for large-scale SOC research and development | |
| EP1367489A1 (en) | A microprocessor development system | |
| CN112882876A (en) | PLD device remote debugging and configuration system | |
| CN112329369A (en) | Method for debugging software on chip simulation model | |
| US20230289500A1 (en) | Method and system for building hardware images from heterogeneous designs for eletronic systems | |
| Vaish et al. | Uniform debugging interface for simulators |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20240304 Address after: Room 1101, 11th Floor, Pacific International Building, No.106 Zhichun Road, Haidian District, Beijing, 100000 Patentee after: Beijing Haiyunjiexun Technology Co.,Ltd. Country or region after: China Address before: Room 503, building B3, phase I, R & D building, 62-1 Xuecheng Avenue, Shapingba District, Chongqing 404100 Patentee before: Chongqing Haiyun Jiexun Technology Co.,Ltd. Country or region before: China |
|
| TR01 | Transfer of patent right |