CN111427839A - Remote online configuration and debugging method for Intel SoC FPGA - Google Patents
Remote online configuration and debugging method for Intel SoC FPGA Download PDFInfo
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- G06F15/76—Architectures of general purpose stored program computers
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Abstract
The invention discloses a remote online configuration and debugging method of an Intel SoC FPGA, which comprises the steps of S1, configuring an S L D application program and an Ethernet controller on an HPS side of the Intel SoC FPGA, S2, designing the Intel SoC FPGA, compiling to obtain a configuration file containing S L D debugging information, downloading the configuration file to the Intel SoC FPGA, S3, converting S L D debugging information in the configuration file into an Avalon-ST data packet, bridging bottom hardware of the Intel SoC FPGA and an S L D application program, S4, bridging an S L D Hub controller and an Ethernet controller of the Intel SoC FPGA through the S L D application program, S5, accessing the S L D application program running on the HPS side of the Intel SoC FPGA in a network mode through a PC to carry out online debugging, debugging the S L D debugging tool of the PC and the S L D of the Intel SoC FPGA in a network mode through the Ethernet TCP/IP protocol, controlling the JTAG to be combined with the USB, and provide a plurality of high-point-to-point debugging and high-point interfaces.
Description
Technical Field
The invention relates to the technical field of debugging in the FPGA development process, in particular to a remote online configuration and debugging method of an Intel SoC FPGA.
Background
The FPGA (Field-Programmable Gate Array) is a novel SoC chip which is released by an Intel PSG (original Altera) and integrates an HPS (hardware processor System) hard core processor and FPGA logic resources on a single chip, wherein the HPS is based on an ARM core-A9 dual-core processor, and also integrates various high-performance peripherals such as an MMU (memory management unit), a DDR3 controller, a Nand F L ASH controller and the like, the HPS can operate a L inux operating system, the HPS and the FPGA not only can work independently, but also can realize high-speed broadband data communication through high-performance AXI bus bridging, and the Intel SoC FPGA not only has the flexible and efficient data operation and transaction processing capacity of the ARM processor, but also integrates the high-speed parallel processing advantages of the FPGA.
As shown in fig. 1, a general configuration and debugging method of an Intel SoC FPGA includes: and connecting the PC with the FPGA device to be debugged by using a JTAG cable, and then debugging by using a debugging tool integrated in a Quartus development kit. However, in SoC FPGA hardware system development, multiple persons commonly cooperate to develop the method, and developers may be distributed in different places. Considering that SoC FPGA development equipment is expensive, in order to save cost, one set of SoC FPGA development equipment can not be ensured. In addition, in the FPGA teaching experiment, the student FPGA experiment operation can only be completed in the FPGA laboratory, and the experiment effect is low due to the development time of the laboratory. Therefore, it is a need to remotely configure and debug the FPGA system online via a network. The configuration and debugging mode of the conventional FPGA system is limited by the length of the JTAG cable, so that remote operation is difficult to realize.
At present, an existing method for debugging an FPGA remotely, for example, a patent (application No. 20151103058.7) describes an FPGA/CP L D remote debugging system and method, which mainly have the problem that only pin signals can be observed, but internal signals of a chip cannot be observed to complete online logic analysis.
Most of the FPGA remote configuration and debugging methods on the market have single function, complex operation steps and redundant structures. The bottom layer depends on JATG protocol, JTAG is converted into USB or parallel port, an Intel JTAG simulator is required to be connected with FPGA point to point, universality is low, and time-sharing configuration and debugging of a plurality of PCs to the same FPGA cannot be realized.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the problems, the remote online configuration and debugging method of the Intel SoC FPGA is provided, and the remote online configuration and debugging of the FPGA without using a JTAG connector can be realized.
The technical scheme adopted by the invention is as follows:
a remote online configuration and debugging method for an Intel SoC FPGA comprises the following steps:
s1, configuring an S L D application program and an Ethernet controller for realizing data interaction with a PC through a TCP/IP protocol on the HPS side of the Intel SoC FPGA;
s2, carrying out Intel SoC FPGA design on a PC, adding S L D debugging information by using an S L D debugging tool after the design is finished, obtaining a configuration file containing S L D debugging information through compiling, and downloading and configuring the configuration file into the Intel SoC FPGA;
s3, converting S L D debugging information in the configuration file into an Avalon-ST data packet by an S L D Hub controller of the Intel SoC FPGA so as to bridge bottom hardware and an S L D application program of the Intel SoC FPGA;
s4, bridging the S L D Hub controller and the Ethernet controller of the Intel SoC FPGA through an S L D application program, and enabling an S L D debugging tool of the PC to perform data interaction with the Intel SoC FPGA through a TCP/IP protocol;
and S5, accessing the S L D application program running on the HPS side of the Intel SoC FPGA in a network mode through the PC to perform online debugging.
Further, the method of S5 includes:
s51, connecting the PC with the Intel SoC FPGA through the Ethernet, so that the PC and the Intel SoC FPGA are in the same network segment;
s52, starting a design experiment, designing an Intel SoC FPGA on a PC, adding S L D debugging information by using an S L D debugging tool after the design is finished, obtaining a configuration file containing S L D debugging information by compiling, and downloading and configuring the configuration file into the Intel SoC FPGA;
s53, starting remote debugging service, executing a remote debugging script command in SoC EDS software, and establishing remote connection;
s54, selecting an S L D Hub Controller System at Hardware in the S L D debugging tool, and starting debugging after successful loading;
and S55, verifying the designed experimental result, if the designed experimental result does not meet the expected requirement, jumping to the step S2, and after the design of the Intel SoC FPGA is modified by the PC, re-executing the steps S52-S55.
In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:
the invention combines the S L D debugging tool of the PC with the S L D Hub controller of the Intel SoC FPGA through a non-JTAG channel chain, namely an Ethernet TCP/IP protocol, provides hardware support, allows a plurality of nodes to share the access to a user debugging interface, is superior to the point-to-point debugging of the traditional JTAG mode, and has high universality.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a block diagram of a conventional JTAG configured and debugged system.
Fig. 2 is a system block diagram of the remote online configuration and debugging method of the Intel SoC FPGA of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
In this embodiment, a PC and an Intel SoC FPGA are used for remote online configuration and debugging, wherein an S L D debugging tool used In the PC is an S L D System level debugging tool In the qualtus software, and the supported S L D debugging tools include a SignalTap II logic analyzer, an In-System Sources and Probes In the systems, a Memory Content Editor, and a Signal Probe Signal.
Example 1
The remote online configuration and debugging method for the Intel SoC FPGA provided by the embodiment comprises the following steps:
the method comprises the steps of S1, configuring an S L D application program and an Ethernet controller for realizing data interaction with a PC through a TCP/IP protocol on an HPS side of an Intel SoC FPGA, configuring L ink APP as an S L D application program, configuring EMMC/Driver as the Ethernet controller and another Driver for connecting the HPS of the Intel SoC FPGA with the FPGA as shown in FIG. 2, wherein the S L D application program is an application program designed through a common programming language and runs on an operating system on the HPS side, and preferably, the S L D application program is set to be automatically operated after being electrified.
S2, carrying out Intel SoC FPGA design on a PC, adding S L D debugging information by using an S L D debugging tool after the design is finished, obtaining a configuration file containing S L D debugging information by compiling, downloading and configuring the configuration file into the Intel SoC FPGA, wherein the configuration file is in an rbf format generally, and can be downloaded and configured into the Intel SoC FPGA by adopting configuration software, such as an FPGA manager peripheral of an HPS.
S3, converting S L D debugging information in the configuration file into an Avalon-ST data packet by an S L D Hub controller of the Intel SoC FPGA so as to bridge bottom hardware and an S L D application program of the Intel SoC FPGA;
s4, bridging the S L D Hub controller and the Ethernet controller of the Intel SoC FPGA through the S L D application program, and enabling the S L D debugging tool of the PC and the Intel SoC FPGA to carry out data interaction through a TCP/IP protocol, wherein after the S L D debugging tool of the PC and the Intel SoC FPGA can carry out data interaction through the TCP/IP protocol, the S L D application program can pack data generated by the S L D Hub controller into a TCP/IP data packet and transmit the data through a socket.
S5, accessing an S L D application program running on the HPS side of the Intel SoC FPGA in a network mode through an S L D debugging tool of the PC to perform online debugging, completing the configuration of the Intel SoC FPGA through the steps S1-S4, and when the Intel SoC FPGA is needed to be used for debugging, realizing remote online debugging by using the S L D debugging tool after the PC is in Ethernet connection with the Intel SoC FPGA, wherein the method of S5 comprises the following steps:
s51, connecting the PC with the Intel SoC FPGA through the Ethernet, so that the PC and the Intel SoC FPGA are in the same network segment;
s52, starting a design experiment, designing an Intel SoC FPGA on a PC, adding S L D debugging information by using an S L D debugging tool after the design is finished, obtaining a configuration file containing S L D debugging information by compiling, and downloading and configuring the configuration file into the Intel SoC FPGA;
s53, starting remote debugging service, executing a remote debugging script command in SoC EDS software, and establishing remote connection;
s54, selecting an S L D Hub Controller System at Hardware in the S L D debugging tool, and starting debugging after successful loading;
and S55, verifying the designed experimental result, if the designed experimental result does not meet the expected requirement, jumping to the step S2, and after the design of the Intel SoC FPGA is modified by the PC, re-executing the steps S52-S55.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (6)
1. A remote online configuration and debugging method for an Intel SoC FPGA is characterized by comprising the following steps:
s1, configuring an S L D application program and an Ethernet controller for realizing data interaction with a PC through a TCP/IP protocol on the HPS side of the Intel SoC FPGA;
s2, carrying out Intel SoC FPGA design on the PC, adding S L D debugging information by using an S L D debugging tool after the design is finished, obtaining a configuration file containing S L D debugging information through compiling, and downloading and configuring the configuration file into Intel SoCFPGA;
s3, converting S L D debugging information in the configuration file into an Avalon-ST data packet by an S L D Hub controller of the Intel SoC FPGA so as to bridge bottom hardware and an S L D application program of the Intel SoC FPGA;
s4, bridging the S L D Hub controller and the Ethernet controller of the Intel SoC FPGA through an S L D application program, and enabling an S L D debugging tool of the PC to perform data interaction with the Intel SoC FPGA through a TCP/IP protocol;
and S5, accessing the S L D application program running on the HPS side of the Intel SoC FPGA in a network mode through the PC to perform online debugging.
2. The remote online configuration and debugging method of the Intel SoC FPGA of claim 1, wherein the method of S5 comprises:
s51, connecting the PC with the Intel SoC FPGA through the Ethernet, so that the PC and the Intel SoC FPGA are in the same network segment;
s52, starting a design experiment, designing an Intel SoC FPGA on a PC, adding S L D debugging information by using an S L D debugging tool after the design is finished, obtaining a configuration file containing S L D debugging information by compiling, and downloading and configuring the configuration file into the Intel SoC FPGA;
s53, starting remote debugging service, executing a remote debugging script command in SoC EDS software, and establishing remote connection;
s54, selecting an S L D Hub Controller System at Hardware in the S L D debugging tool, and starting debugging after successful loading;
and S55, verifying the designed experimental result, if the designed experimental result does not meet the expected requirement, jumping to the step S2, and after the PC machine modifies the Intel SoC FPGA design, re-executing the steps S52-S55.
3. The remote online configuration and debugging method of Intel SoC FPGA according to claim 1 or 2, wherein the S L D debugging tool is an S L D system-level debugging tool in Quartus software.
4. The remote online configuration and debugging method of Intel SoC FPGA according to claim 3, wherein the S L D debugging tool comprises a SignalTap II logic analyzer, In-System resources and Probes System internal Signal Sources and Probes, Memory Content Editor, Signal Probe Signal Probe.
5. The remote online configuration and debugging method of the Intel SoC FPGA according to claim 1 or 2, wherein the configuration file is in rbf format.
6. The remote online configuration and debugging method of the Intel SoC FPGA of claim 1, wherein the S L D application program is set to run automatically upon power-up.
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