CN112580295B

CN112580295B - Automatic verification method, system and device for multi-core SoC chip

Info

Publication number: CN112580295B
Application number: CN202011334559.XA
Authority: CN
Inventors: 黎金旺; 张彦欣; 贺龙龙; 宁振海; 杨小坤; 李德建; 杨立新; 谭浪; 白志华; 刘胜; 唐志军; 李智诚
Original assignee: State Grid Corp of China SGCC; State Grid Information and Telecommunication Co Ltd; Electric Power Research Institute of State Grid Fujian Electric Power Co Ltd; State Grid Fujian Electric Power Co Ltd; Beijing Smartchip Microelectronics Technology Co Ltd
Current assignee: State Grid Corp of China SGCC; State Grid Information and Telecommunication Co Ltd; Electric Power Research Institute of State Grid Fujian Electric Power Co Ltd; State Grid Fujian Electric Power Co Ltd; Beijing Smartchip Microelectronics Technology Co Ltd
Priority date: 2020-11-24
Filing date: 2020-11-24
Publication date: 2022-07-05
Anticipated expiration: 2040-11-24
Also published as: CN112580295A

Abstract

The invention provides an automatic verification method, system and device for a multi-core SoC chip, and belongs to the technical field of chip test verification. The method comprises the following steps: dividing codes of digital circuits of the multi-core SoC chip; the codes of the divided digital circuits are synthesized into netlists corresponding to at least two FPGA chips; according to the netlist, laying out and wiring the circuit images of the at least two FPGA chips, and generating a file to be verified of the hardware after laying out and wiring; deploying the file to be verified of the hardware to a verification system with at least two FPGA chips; compiling a multi-core processor program code of the multi-core SoC chip, and obtaining a file to be verified of the software after compiling; and deploying the file to be verified of the software to the verification system, and executing the verification before the multi-core SoC chip stream on the deployed verification system. The invention can be used for chip stream chip front prototype verification of SoC or MCU.

Description

Automatic verification method, system and device for multi-core SoC chip

Technical Field

The invention relates to the technical field of chip test and verification, in particular to an automatic verification method of a multi-core SoC chip, an automatic verification system of the multi-core SoC chip, an automatic verification device of the multi-core SoC chip, electronic equipment and a computer readable storage medium.

Background

With the rapid progress of semiconductor technology and the continuous development of architecture, the performance of a cpu (central Processing unit) of a processor is continuously improved, and the processor is also developed from the original single core and double cores to the current multi-core technology. Due to the strong performance of the multi-core processor, the multi-core processor is widely applied to terminal devices in various fields, and meanwhile, more and more system on chip (soc) chips or main Control chip (mcu) (micro Control unit) chips are integrated with the multi-core processor, so that the logic resources, the design complexity and the technical difficulty of the chips are inevitably increased. Meanwhile, the multi-core technology also brings severe requirements and serious challenges to SoC chip system design, software and hardware cooperative processing, Field Programmable Gate Array (FPGA) hardware platform design and FPGA verification, while most of the existing SoC or MCU chip verification frameworks are single-core system frameworks, which mainly map SoC or MCU chip design to one FPGA chip, and thus, an automatic verification method and an FPGA verification system or platform supporting a multi-core processor chip are required.

Disclosure of Invention

The invention aims to provide an automatic verification method, system and device of a multi-core SoC chip, which adopt tool software and pre-designed scripts to realize a complex automatic verification system of the multi-core SoC chip, solve the complex design flow problems of code division, comprehensive layout and wiring, generation of mapping files, software and hardware collaborative verification and the like of the multi-core SoC chip, avoid the difficulty in software and hardware collaborative characteristic verification among a plurality of CPU cores caused by the instantiation of digital circuit codes of the multi-core SoC chip to an FPGA chip, and improve the working efficiency and correctness of the design of the multi-core SoC chip.

In order to achieve the above object, an embodiment of the present invention provides an automatic verification method for a multi-core SoC chip, where the automatic verification method includes:

dividing codes of digital circuits of the multi-core SoC chip;

the codes of the divided digital circuits are synthesized into netlists corresponding to at least two FPGA chips;

according to the netlist, laying out and wiring the circuit images of the at least two FPGA chips, and generating a file to be verified of the hardware after laying out and wiring;

deploying the file to be verified of the hardware to a verification system with at least two FPGA chips;

compiling a multi-core processor program code of the multi-core SoC chip, and obtaining a file to be verified of the software after compiling;

and deploying the file to be verified of the software to the verification system, and executing the verification before the multi-core SoC chip stream on the deployed verification system.

Specifically, the code for dividing the digital circuit of the multi-core SoC chip includes:

according to a code structure of a digital circuit of the multi-core SoC chip, identifying bus architecture information of the multi-core SoC chip through a script file which is configured on tool software;

and dividing the code of the digital circuit of the multi-core SoC chip according to the bus architecture information.

Specifically, the code of the digital circuit of the multi-core SoC chip is divided according to the bus architecture information, wherein,

codes of digital circuits corresponding to the CPU cores in the multi-core SoC chip are respectively and independently divided into core modules,

code of digital circuits corresponding to a bus architecture within the multi-core SoC chip is partitioned into bus modules,

the code of the digital circuit corresponding to the external interface or device within the multi-core SoC chip is divided into peripheral modules,

any one of the CPU cores is connected to the external interface or device through the bus architecture, and the any one of the CPU cores accesses and controls the external interface or device through the bus architecture.

Specifically, the code of the synthetically divided digital circuit is a netlist corresponding to at least two FPGA chips, and includes:

and synthesizing the kernel module, the bus module and the peripheral module into netlists corresponding to at least two FPGA chips.

Specifically, the laying out and routing the circuit images of the at least two FPGA chips according to the netlist, and generating a hardware to-be-verified file after laying out and routing includes:

connecting the same synchronous clock source to each FPGA chip of the at least two FPGA chips;

laying out the functional blocks in the netlist to physical locations within each FPGA chip,

the functional blocks laid out in each FPGA chip are wired,

generating a file to be verified of hardware corresponding to each FPGA chip, wherein,

the chip bus of the bus architecture is mapped as an FPGA chip bus,

the at least two FPGA chips are connected with each other through the FPGA chip bus.

Specifically, the deploying the file to be verified of the hardware to the verification system with the at least two FPGA chips includes:

downloading the file to be verified of the hardware to each FPGA chip connected with the FPGA debugging interface by using an FPGA downloader through the FPGA debugging interface, wherein,

the verification system is provided with the FPGA debugging interface.

Specifically, the deploying the file to be verified of the software to the verification system includes:

downloading the software to-be-verified file to a program memory of an FPGA chip in the verification system through a CPU debugging interface by using a CPU program debugger, wherein,

the program memory has a function of being read by a CPU core in each FPGA chip.

The embodiment of the invention provides an automatic verification system of a multi-core SoC chip, which comprises:

the multi-core processor hardware image generation module is used for dividing codes of digital circuits of the multi-core SoC chips, synthesizing the codes of the divided digital circuits into netlists corresponding to the at least two FPGA chips, performing layout and wiring on the circuit images of the at least two FPGA chips according to the netlists, and generating a hardware to-be-verified file after the layout and wiring;

the multi-core processor software program generation module is used for compiling multi-core processor program codes of the multi-core SoC chip and obtaining a software to-be-verified file after compiling;

the deployment module is used for deploying the hardware to-be-verified file to a verification system with the at least two FPGA chips, deploying the software to-be-verified file to the verification system, and performing verification before the multi-core SoC chip stream on the deployed verification system.

The embodiment of the invention provides an automatic verification device of a multi-core SoC chip, which comprises: the system comprises an automation software platform, an automation control platform and an FPGA hardware platform;

the automatic software platform is configured to have a function of forming a hardware to-be-verified file corresponding to the multi-core SoC chip in the automatic verification method of the multi-core SoC chip;

the automation control platform is configured to have a function of a software to-be-verified file corresponding to the multi-core SoC chip in an automatic verification method for forming the multi-core SoC chip;

the FPGA hardware platform is provided with at least two FPGA chips, a CPU debugging interface, an FPGA debugging interface and a plurality of peripheral interfaces, wherein the CPU debugging interface, the FPGA debugging interface and the plurality of peripheral interfaces are connected with the at least two FPGA chips, and the peripheral interfaces comprise interfaces for connecting with a storage medium and serial interfaces for data transmission;

the FPGA hardware platform is also provided with a synchronous clock source or a synchronous clock input interface which is connected with the at least two FPGA chips;

the FPGA hardware platform is configured by the automation software platform through the hardware file to be verified;

the FPGA hardware platform is configured by the automation control platform through the software to-be-verified file;

the FPGA hardware platform is configured to have a function of supporting the execution of pre-stream-chip verification on the multi-core SoC chip.

The system comprises an automation software platform, an automation control platform and an FPGA hardware platform;

the automated software platform is configured to have an instruction execution function corresponding to the automated verification method of the multi-core SoC chip of any one of claims 1 to 5;

the automation control platform is configured to have an instruction execution function corresponding to the automated verification method of the multi-core SoC chip of claim 6 or 7;

the FPGA hardware platform is configured by the automation software platform through a hardware to-be-verified file corresponding to the multi-core SoC chip;

the FPGA hardware platform is configured by the automation control platform through a software to-be-verified file corresponding to the multi-core SoC chip;

In another aspect, an embodiment of the present invention provides an electronic device, including:

at least one processor;

a memory coupled to the at least one processor;

wherein the memory stores instructions executable by the at least one processor, the at least one processor implements the aforementioned method by executing the instructions stored by the memory.

In yet another aspect, an embodiment of the present invention provides a computer-readable storage medium storing computer instructions, which, when executed on a computer, cause the computer to perform the foregoing method.

The invention provides a realization scheme for the code segmentation of a SoC/MCU (MCU can be regarded as the SoC of a multi-CPU core) digital circuit, the clock domain crossing and the software and hardware collaborative verification among multiple cores of a multi-core SoC/MCU chip in a cross-FPGA chip verification scene; the invention can verify the correctness of the chip function and check the defects in the hardware design, can develop Firmware (Firmware), early development and debugging test of operating system software and evaluate the system performance at the same time, can quickly and accurately find out the design defects, is convenient for problem location and logic search of verification, has the characteristics of good debugging and verification real-time performance, has the characteristics of stability and synchronism of data transmission among a plurality of pieces of FPGA, can be suitable for prototype verification of SoC chips with various sizes, and can be repeatedly utilized to verify items of each chip, and has the characteristics of strong compatibility and expandability and the like.

Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:

FIG. 1 is a schematic diagram of the main steps of the method of the present invention;

FIG. 2 is a schematic diagram of a conventional AMBA-type bus architecture;

FIG. 3 is a block diagram of an exemplary split code and mapping chip according to an embodiment of the invention;

fig. 4 is a schematic block diagram of an automation software and control platform and an FPGA hardware platform according to an embodiment of the present invention.

Detailed Description

The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.

Example 1

The embodiment of the invention provides an FPGA (field programmable gate array) verification method of a multi-core SoC (system on chip), as shown in figure 1, the FPGA verification method comprises the following steps:

automatically segmenting codes of a digital circuit of the multi-core SoC chip by executing the configured script file on tool software;

deploying the file to be verified of the software to the verification system, and executing verification before the multi-core SoC chip stream on the deployed verification system; the above processes can be automatically executed by tool software and pre-designed scripts.

In some specific implementations, the multi-core SoC chip includes an SoC or an MCU, taking the SoC as an example, in the implementation of the present invention, the SoC may have at least 2 cores, may be 2 cores, 3 cores or 4 cores, and the CPU core of the multi-core SoC chip may include one or more ARM processor cores and/or one or more digital Signal processor (dsp) (digital Signal processor) cores, and the like, and may also include one or more MIPS processors or microprocessors, and the like, and each processor may have a plurality of compute cores, and the compute core may at least include an arithmetic logic unit, a register file, and a corresponding bus interface; the processor bus architecture of the SoC may include a bus controller, memory, peripheral translation bridge, etc., in some cases with external interfaces or devices within the multi-core SoC chip; under a bus architecture, each CPU core can be combined with the bus architecture (such as a bus controller) to perform communication connection through a chip bus (or a system bus) and realize the use of system resources; the Bus architecture may include a micro control Bus architecture AMBA (Advanced Microcontroller Bus architecture-capture), an Avalon Bus architecture, a CoreConnect Bus architecture, an STBus architecture, and the like; for example, for an SoC of an AMBA bus-type architecture, an ARM processor core (which should be distinguished from the aforementioned compute core and may be referred to as the SoC) and a DSP processor core are both connected to a system bus ASB (advanced system bus) or an advanced high-performance bus AHB (advanced high-performance bus), an on-chip random access memory may also be provided in the SoC, the SoC has a bus bridge (which may be implemented by a bus controller), and the two processor cores are connected to peripherals or various interfaces through the bus bridge or to the AHB or the ASB through the bus bridge.

As shown in fig. 2, the architecture is a common AMBA-type bus architecture, and can obtain connection information corresponding to modules according to the bus architecture, for example, 3 processors are connected to an AHB or ASB bus, the 3 processors may be an ARM processor, a DSP processor, and a microprocessor, respectively, and an On-chip random access memory (On-chipRAM) and a high-bandwidth memory interface are further connected to the AHB or ASB bus, and are connected to a timer, a UART interface, an interactive interface (e.g., a key), and a PIO interface through a bus bridge.

For codes of a digital circuit for segmenting the multi-core SoC chip, according to the code structure of the digital circuit of the multi-core SoC chip, bus architecture information of the multi-core SoC chip is identified through executing a configured script file on tool software, wherein the analysis mode of each code structure and the bus architecture information corresponding to the analysis result can be predefined through the tool software and the script file, and the analysis mode can comprise semantic analysis or logic level analysis, such as a logic tree diagram and the like; then, according to the obtained bus architecture information, the bus architecture can be divided according to a specific SoC bus architecture, for example, an SoC having two processor cores can be divided into one core module for each core, two FPGA chips can be considered for mapping in the subsequent processing, a larger number of FPGA chips can be considered for mapping, and the FPGA chips which are not mapped with the core modules can be used for mapping external modules and/or bus modules such as a high-speed memory and/or a high-speed bus controller; before synthesis (synthesis may include operations of converting a hardware description language program into a gate-level structure netlist, and the like), the number of FPGA chips may be selected according to the number of cores of a multi-core SoC chip, and the number of FPGA chips may be greater than or equal to the number of cores, and a specific development kit (a tool software) may be determined according to the type of the FPGA chip of a specific manufacturer to be used, for example, a development kit synclify, ISE, VIVADO, or the like may be used, and various gate-level structures corresponding to codes of a digital circuit are preset in the development kit, so that a specific process may be implemented by using the development kit when synthesizing and laying out wiring; secondly, the bus architecture of the multi-core SoC chip has module characteristics of processing logic, such as a processor core, a memory, a bus controller and the like which can be used as a basis for dividing the core module, the logic of the code of the digital circuit of the multi-core SoC chip can be divided according to the bus architecture to obtain the core module, and the core module can comprehensively obtain the corresponding digital circuit by inquiring a circuit template corresponding to the code; during synthesis, according to the relative position characteristics of the CPU core and the external interface or device in the bus architecture of the multi-core SoC chip, all or part of the peripheral modules corresponding to the external interface or device may also be mapped into a netlist corresponding to the FPGA chip (to which the core module has been mapped), such as an interface bus, a bus bridge for high-speed memory access, etc., and the bus module and/or the peripheral modules may be mapped into the netlist corresponding to the FPGA chip in the form of an IP core, and for example, the modules for synchronization and conversion may also be mapped through a digital or analog logic circuit, and for example, the interface bus and the bus controller may also be mapped into the FPGA chip to which the core module has not been mapped.

After the synthesis, the gate-level circuit of the synthesized netlist can be mapped to the actual resources of the FPGA chip, the synchronization of the clocks of each FPGA chip can be executed in coordination with the layout and wiring operations without distinguishing the sequence of operations, and specifically, the same synchronous clock source is connected to each FPGA chip of the at least two FPGA chips; functional blocks in the netlist (e.g., clock logic, processing logic, inputs and outputs) are placed into physical locations within each FPGA chip, the functional blocks arranged in each FPGA chip are wired, the hardware files to be verified corresponding to each FPGA chip can be generated through the development kit, wherein the chip bus of the bus architecture is mapped as an FPGA chip bus, the at least two FPGA chips are connected to each other through the FPGA chip bus, at this time, the digital circuit code logic of multi-core SoC has been partitioned into N pieces of FPGA chips (N is the number of target FPGAs and is a positive integer greater than 1) using a multi-core SoC bus architecture, the N FPGA chips may be connected by a bus, and the FPGA chips may be respectively integrated, laid out and wired by an FPGA integrated layout and wiring tool (the development kit described above) to generate N image files (e.g., image files of bit suffixes) corresponding to the respective FPGA chips.

After the layout and wiring are performed and before the image file is downloaded, debugging and analysis matched with the development kit can be performed, for example, timing analysis, and the file deployment operation can be performed after the debugging and analysis are completed. Then, the file to be verified of the hardware can be deployed to a verification system having at least two FPGA chips, for example, an FPGA downloader is used to download N image files to N FPGAs connected to the FPGA debug interface of the FPGA through the FPGA debug interface (1 image file may only configure one FPGA chip), wherein the corresponding positions of the specific image file and the FPGA chip on the verification system can be determined during layout and wiring, and the number and type of the FPGA chips of the verification system can be consistent with those of the FPGA chips in the circuit image processed during layout and wiring (because the FPGA chips in the same series may have compatibility, the types may not be completely consistent and may also be applicable), thereby completing the hardware instantiating the multi-core SoC digital circuit to the FPGA.

In some specific implementations, the partitioning, the synthesis, the layout and the wiring can be performed according to actual conditions such as the selected resources of the FPGA chip, SoC design requirements and the like. For example, as shown in fig. 3, in an SoC design using an AMBA-based bus architecture, there may be 4 processors (processor 1 to processor 4), memory interfaces, and bus bridges (which may include multiple bus interfaces and/or bus controllers, and a bus controller may belong to a processor in some cases), a basic Core (Core1 to Core4) block may be distinguished on a per processor basis, logic of codes of the SoC may be divided according to the bus architecture information, a memory interface, a bus interface, and an on-chip memory may be arranged around a Core in the bus architecture, and the on-chip memory may be divided into 4 parts according to actual demand conditions and respectively matched with one Core module or be divided independently, as a module that is not mapped to an FPGA chip, codes corresponding to the bus interfaces and the memory interfaces may be respectively matched with one Core module, after synthesis and layout wiring, the core module is respectively mapped to a CPU in the FPGA chip, the bus interface and the memory interface can be mapped in the FPGA chip in the form of an IP core or a LOGIC, and each FPGA chip is in bus connection with the FPGA chip and completes synchronization through a CLOCK source CLOCK.

The compiling of the program code of the multicore processor may be performed before, simultaneously with, or after the above-described steps of dividing, synthesizing, laying out, wiring, and the like. The compiling operation may be performed by compiling debugging software (a tool software), such as KeilMDK or IAR, and compiling the multi-core processor program code to generate a file to be verified (e.g., a file of the hex or bin suffix) of the software. Then, a CPU program debugger may be used to download the file to be verified of the software to a program memory of an FPGA chip in the verification system through a CPU debug interface, where the program memory has a function of being read by a CPU core in each FPGA chip, so as to form a software system with a function of a multi-core SoC chip in the verification system.

After the deployment of the hardware to-be-verified file and the software to-be-verified file is completed, the verification system with the N pieces of FPGA chips forms a simulated hardware model in front of a multi-core SoC chip, software is run on the hardware model, and according to defined verification operation, the correctness and performance of software and hardware cooperative work can be determined to verify the correctness of chip digital circuit design and the correctness of software programs, illustratively, the defined verification can specifically include the correctness of the startup (such as processor core program configuration and loading) of the hardware model, functional modules (such as an ethernet port, a PCIE interface, a UART interface and other IP cores) on each FPGA, and the verification can also specifically include the verification of an operating system (such as Linux) of the hardware model, for example, after the verification system is connected with a storage medium with an installed operating system, whether the hardware model can read the storage medium and complete the startup of the operating system can be tested, after starting, the script file can be continuously used for debugging and analyzing the system function.

In contrast, in the conventional FPGA verification system, a piece of FPGA chip is used to map a CPU core, an interface IP core (internal performance core) and a digital and analog Logic (Logic) circuit of an SoC or MCU chip, a peripheral circuit has a plurality of interfaces to transmit data, and the FPGA chip and the peripheral circuit form a complete FPGA verification system. According to the existing single-core SoC/MCU chip software and hardware collaborative FPGA verification scheme, digital circuit resources are small, only one CPU core is provided, digital circuits of all SoC/MCU chips can be instantiated on the same FPGA, the problems of SoC/MCU digital circuit code division across FPGA chips, clock domain crossing, software and hardware collaborative verification among multiple cores and the like do not exist, and therefore the adaptability is narrow.

The automatic verification of the embodiment of the invention aims at the design of a multi-core SoC or a large-scale SoC system, realizes the whole multi-core SoC on an FPGA platform, and is used as a platform for software development to complete software and hardware collaborative verification of the SoC through the design and debugging of system software, so that the design defect can be quickly and accurately found out, and the real-time performance is good;

the automatic verification of the embodiment of the invention adopts a multi-core-based bus architecture segmentation technology to logically segment a digital circuit of a multi-core SoC onto a plurality of FPGAs (field programmable gate arrays), and the plurality of FPGAs are connected by a multi-core bus architecture instead of any logic segmentation, so that all logics can be sequentially divided according to the bus architecture, and the problem positioning and the logic searching are facilitated;

the verification system in the embodiment of the invention adopts a synchronous clock design, so that the stability and the synchronism of data transmission among a plurality of FPGAs are ensured;

the verification system in the embodiment of the invention can flexibly prepare FPGA hardware resources with different quantities according to the design scale capacities of different chips, is suitable for prototype verification of SoC chips with various sizes, and repeatedly utilizes each chip verification project.

Example 2

The embodiment of the invention and the embodiment 1 belong to the same inventive concept, and the embodiment of the invention provides an automatic verification system of a multi-core SoC chip, which comprises the following steps:

the multi-core processor hardware image generation module is used for dividing codes of digital circuits of the multi-core SoC chips, comprehensively dividing the codes of the divided digital circuits into netlists corresponding to at least two FPGA chips, performing layout and wiring on the circuit images of the at least two FPGA chips according to the netlists, and generating a hardware to-be-verified file after the layout and wiring;

the deployment module is used for deploying the hardware to-be-verified file to a verification platform with the at least two FPGA chips, deploying the software to-be-verified file to the verification platform, and executing the verification before the multi-core SoC chip stream to the deployed verification platform.

The automated verification system, which may be deployed on one or more computers, may be configured with the development kit and compiled debug software of embodiment 1.

The automatic verification system can communicate with an interface conversion device (such as a conversion device of a serial interface conversion JTAG interface) to realize file transmission and debugging with a hardware platform.

Example 3

In the embodiment of the present invention, the embodiment of the present invention and embodiments 1 and 2 all belong to the same inventive concept, and the embodiment of the present invention provides an automatic verification apparatus for a multi-core SoC chip, including: the system comprises an automation software platform, an automation control platform and an FPGA hardware platform;

the automated software platform is configured to have an execution function of instructions corresponding to the automated verification method of the multi-core SoC chip described in embodiment 1, where the execution function may include functions of automatic code division, comprehensive netlist generation, and circuit image file (hardware to-be-verified file) generation, and the automated software platform may be a device such as a computer or a server with an instruction processing capability, and the computer or the server may be installed with tool software and may be configured with a storage medium having a script file, and the script file may record instructions with the aforementioned execution function;

the automation control platform is configured to have an instruction execution function corresponding to the automated verification method for the multi-core SoC chip described in embodiment 1, where the instruction execution function may include a function of forming and compiling a processor program (a file to be verified for software), and the automation control platform may be a device such as a computer or a server that has an instruction processing capability, where the computer or the server (which may be the aforementioned computer or the server, or may be a different device) may be installed with tool software, and may be configured with a storage medium having a script file, where the script file may be recorded with an instruction having the aforementioned execution function;

the FPGA hardware platform may include the verification system having a plurality of FPGA chips in embodiment 1.

As shown in fig. 4, the automation software platform can divide the multi-core SoC digital circuit code into N blocks, generate N bit (mirror image) files using the FPGA comprehensive layout and wiring tool, then download the debugger through the FPGA to burn each of the N bit files as the files to be verified of the hardware into the FPGA hardware platform, complete the process from the instantiated digital circuit to the hardware, wherein the analysis and debugging can be performed through the FPGA debugging tool software, and the bit files can be regenerated and burned into the FPGA hardware platform again; on the CPU program side, the automation control platform imports the multi-core CPU program code into the compiling and debugging software KeilMDK or IAR, and generates the hex or the bin file on the automation control platform through the compiling and debugging software, and the CPU program downloads the debugger to write the hex or the bin file into the program memory of the FPGA hardware platform, wherein the multi-core CPU program code can be analyzed and debugged, and the hex or the bin file can be newly compiled to generate a new hex or bin file and written into the program memory of the FPGA hardware platform.

In the FPGA hardware platform, there may be 4 FPGA chips, and also peripheral circuits, each FPGA chip has an IP core, a processor CPU core and a digital and analog LOGIC LOGIC circuit, each FPGA chip is connected with an FPGA chip bus (as in FIG. 3), each FPGA chip CAN obtain the interface resources of each peripheral circuit through the FPGA chip bus under the normal configuration condition, and CAN be used to realize the circuit function that is not mapped to the FPGA chip, the peripheral circuit may include a CPU debug interface, a USB interface, an Ethernet interface, a PCIE interface, an SRAM memory (having an SRAM interface or already carrying an SRAM memory chip), a PI interface, a CAN bus interface, a UART interface, an SD card (having an SD card interface or already carrying an SD card), a NorFlash memory (having a NorFlash interface or already carrying a NorFlash chip), a NADNFlash memory (having an NADNFlash interface or already carrying a NADNFlash chip), a hard disk (SATA) interface, a USB interface, a peripheral circuit interface, a peripheral circuit, a peripheral, The interface comprises a memory (DDR) interface, a 7816 interface, an SPI interface, an I2C interface, an FPGA debugging interface, a ClOCK and reset module (CLOCK), wherein the interfaces can comprise physical interfaces which are matched with an IP core (such as an interface bus controller) on an FPGA chip to realize complete interface functions, a peripheral circuit is connected with the FPGA chip and can form a closed loop, so that the correctness of the functions and the performances of the interface module (the IP core and a Logic input and output interface Logic) of the multi-core SoC chip can be verified, the ClOCK and reset module can provide synchronous ClOCK sources and reset functions for all FPGA chips, and the time sequence synchronism and the reusability of the whole system are realized. In the embodiment of the invention, the FPGA hardware platform in the verification system has rich peripheral circuit interfaces, meets the verification requirements of a multi-core SoC/MCU chip, can expand the peripheral circuit and has strong compatibility and expandability.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solutions of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications all belong to the protection scope of the embodiments of the present invention.

It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present invention do not describe every possible combination.

Those skilled in the art will understand that all or part of the steps in the method according to the above embodiments may be implemented by a program, which is stored in a storage medium and includes several instructions to enable a single chip, a chip, or a processor (processor) to execute all or part of the steps in the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

In addition, any combination of various different implementation manners of the embodiments of the present invention can be made, and the embodiments of the present invention should also be regarded as the disclosure of the embodiments of the present invention as long as the combination does not depart from the spirit of the embodiments of the present invention.

Claims

1. An automatic verification method of a multi-core SoC chip is characterized by comprising the following steps:

code to segment a digital circuit of a multi-core SoC chip, wherein the multi-core SoC chip has a bus controller;

compiling the multi-core processor program codes of the multi-core SoC chip, and obtaining a software to-be-verified file after compiling;

deploying the file to be verified of the software to the verification system, and executing verification before the multi-core SoC chip stream on the deployed verification system;

the code for dividing the digital circuit of the multi-core SoC chip comprises the following steps:

identifying bus architecture information of the multi-core SoC chip by executing a configured script file on tool software according to a code structure of a digital circuit of the multi-core SoC chip,

dividing codes of a digital circuit of the multi-core SoC chip according to the bus architecture information;

the code of the digital circuit of the multi-core SoC chip is divided according to the bus architecture information, wherein,

any one CPU core is connected with the external interface or the device through the bus architecture, and accesses and controls the external interface or the device through the bus architecture;

the code of the synthetically divided digital circuit is a netlist corresponding to at least two FPGA chips, wherein,

during synthesis, according to the relative positions of a CPU core and an external interface or equipment in the bus architecture of the multi-core SoC chip, mapping all or part of peripheral modules corresponding to the external interface or equipment to a netlist corresponding to the FPGA chip mapped with the core module,

and the bus controller is mapped to a netlist corresponding to the FPGA chip which is not mapped with the kernel module.

2. The method for automated verification of multi-core SoC chips of claim 1, wherein the code of the synthetically segmented digital circuit is a netlist corresponding to at least two FPGA chips, comprising:

3. The automatic verification method for the multi-core SoC chip according to claim 2, wherein the step of laying out and wiring the circuit images of the at least two FPGA chips according to the netlist and generating a hardware to-be-verified file after laying out and wiring comprises:

the functional blocks laid out in each FPGA chip are wired,

the chip bus of the bus architecture is mapped as an FPGA chip bus,

4. The automatic verification method for the multi-core SoC chip according to claim 3, wherein the deploying the file to be verified of the hardware to a verification system having the at least two FPGA chips comprises:

the verification system is provided with the FPGA debugging interface.

5. The automatic verification method for the multi-core SoC chip according to any of claims 1 to 4, wherein the deploying the software to-be-verified file to the verification system comprises:

6. An automated verification system for a multi-core SoC chip, the automated verification system comprising:

the multi-core processor hardware image generation module is used for dividing codes of digital circuits of a multi-core SoC chip, comprehensively dividing the codes of the digital circuits into netlists corresponding to at least two FPGA chips, performing layout and wiring on the circuit images of the at least two FPGA chips according to the netlists, and generating a hardware to-be-verified file after the layout and wiring are performed, wherein the multi-core SoC chip is provided with a bus controller;

the deployment module is used for deploying the hardware to-be-verified file to a verification system with at least two FPGA chips, deploying the software to-be-verified file to the verification system, and performing verification before the multi-core SoC chip is subjected to chip flow on the deployed verification system;

any one CPU core is connected with the external interface or device through the bus architecture, and accesses and controls the external interface or device through the bus architecture;

synthesizing the code of the divided digital circuit into a netlist corresponding to at least two FPGA chips, wherein,

during synthesis, according to the relative positions of a CPU core and an external interface or equipment in the bus architecture of the multi-core SoC chip, mapping all or part of the peripheral modules corresponding to the external interface or equipment to the netlist corresponding to the FPGA chip mapped with the core module,

the bus controller is mapped to a netlist corresponding to the FPGA chip which is not mapped with the kernel module.

7. An automatic verification device of a multi-core SoC chip is characterized by comprising: the system comprises an automation software platform, an automation control platform and an FPGA hardware platform;

the automated software platform is configured to have a function of forming a hardware to-be-verified file corresponding to the multi-core SoC chip in the automatic verification method for the multi-core SoC chip according to any one of claims 1 to 5;

8. An electronic device, characterized in that the electronic device comprises:

at least one processor;

a memory coupled to the at least one processor;

wherein the memory stores instructions executable by the at least one processor, the at least one processor implementing the method of any one of claims 1 to 5 by executing the instructions stored by the memory.