CN102521444A - Cooperative simulation/verification method and device for software and hardware - Google Patents
Cooperative simulation/verification method and device for software and hardware Download PDFInfo
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Abstract
The invention discloses a cooperative simulation/verification method for software and hardware, which uses a software operating terminal to simulate CPU in SoC design to develop/operate the software and develops the software during hardware simulation/verification. The method comprises the steps of mapping the SoC design to a FPGA (Field Programmable Gata Array); connecting the SoC design to the software operating terminal through a bus main device and an FPGA communication device; developing the software required by the SoC design and operating the software at the software operating terminal to send an excitation signal to the SoC design; and responding to the excitation signal by the SoC design, wherein the responding signal is fed back to the software operating terminal. The invention discloses a cooperative simulation/verification device for software and hardware. The device comprises the FPGA mapped to the SoC design without the CPU and the software operating terminal having the software development function and/or operating function. The bus main device converts the read-write operation of the software to read-write operation of the bus.
Description
Technical field
The present invention relates to a kind of software and hardware cooperating simulation/verification method and device.
Background technology
Along with integrated circuit technology gets into sub-micro, the integrated level of single-chip increases greatly, and the IC design has got into the SoC design phase.A SoC system generally comprises CPU, on-chip bus, storer and various peripheral hardware.The design of SoC not only comprises the design of hardware circuit, also comprises the design that runs on CPU institute operating software on the sheet simultaneously.
The FPGA checking is with designing through the SoC to be tested behind the front-end simulation; Through being mapped to the FPGA device someway is in the reconfigurable hardware platform of base configuration; Set up the SoC prototype; Imitation chip behavior comprehensively, thus move test procedure above that, realize the method that design is verified to SoC.SoC is mapped to rtl code or comprehensive back net table among the FPGA after front-end simulation passes through, and sets up the hardware prototype, on hardware prototype basis, carries out test procedure again, verifies various functions.
Along with the increase of integrated level, traditional can not satisfy the demand of VLSI (very large scale integrated circuits) emulation based on the method for software emulation, need to adopt verification method based on hardware-accelerated software-hardware synergism.
The existing technology one of improving: PC software section and FPGA hardware components, divide three layers on the structure: lower floor realizes transmission of Information on the physical channel; The encapsulation and the decapsulation of Frame accomplished in the middle layer; The input and output that respective signal is implanted are then carried out on the upper strata.Join the policy that FPGA hardware is accomplished hardware through the specific software of operation on PC.
The existing technology two of improving: the system and method for verifying based on the software and hardware cooperating simulation of FPGA comprises setting and the software systems part of user PC end and the hardware system part that IC chip is simulated; Software section comprises the control platform and the embedded system interface module of network tester; Hardware system partly comprises the cpu i/f module; Interface conversion logic module in the FPGA, the interface conversion logic module in the FPGA, chip virtual to be measured and the Network Interface Module realized in the FPGA.
The inventor finds that above-mentioned two kinds are improved one's methods and all lay particular emphasis on the checking to hardware, and is all relevant with specific project at the software of PC end operation, and with software among the SoC certain difference arranged, can not be directly or only do minor modifications and just be used for the SoC of system.
Summary of the invention
In order to overcome above-mentioned defective, the present invention provides a kind of software and hardware cooperating simulation/verification method that carries out hardware verification and software development simultaneously.
For achieving the above object, on the one hand, the present invention provides a kind of software and hardware cooperating simulation/verification method, and said method is carried out software development/operation for using the CPU in the running software terminal simulation SoC design, in emulation/checking hardware, carries out software development; Said method comprises the steps:
The SoC design map is gone into FPGA;
Said SoC design is connected to the running software terminal through bus master and FPGA communication facilities;
Said running software terminal development SoC design software and operation are sent pumping signal to the SoC design;
Said SoC design responsing excitation signal, response signal feeds back to said running software terminal.
On the other hand, the present invention provides a kind of software and hardware cooperating simulation/demo plant, and said device comprises FPGA and the running software terminal with software-development function and/or operation function, is mapped into the SoC design of no CPU in the said FPGA; Said SoC designs connecting bus main equipment and FPGA communication facilities successively, and said communication facilities connects the running software terminal; Bus master is converted into the read-write operation of software the read-write operation of bus.
Software and hardware cooperating simulation/verification method of the present invention does not need the process of cross compile, can before the integrated SoC of advancing of CPU, carry out the exploitation of the driver of independent IP, accelerates development of projects.Make things convenient for the FPGA hardware debug, accelerate SoC Development of Software progress simultaneously.
Running software terminal in software and hardware cooperating simulation/demo plant of the present invention is connected to FPGA through communication facilities, and the simulation that software development/operation realizes FPGA is gone up CPU in the SoC design is carried out at the running software terminal.That is, come out the cpu function in the SoC design is abstract, use the running software terminal to simulate its behavior, thereby software development and particular CPU have nothing to do, and have reusability.Can in different SoC projects, reuse this device, reduce cost, save time, be convenient to the software and hardware cooperating simulation/checking of SoC design.Be the development environment that the software developer of SoC provides a kind of close friend when making things convenient for hardware verification, quicken the SoC Development of Software.
Description of drawings
Fig. 1 is the step of software and hardware cooperating simulation/verification method of the present invention.
Fig. 2 is software and hardware cooperating simulation of the present invention/demo plant preferred embodiment structural representation.
Fig. 3 is FPGA end bus master preferred embodiment structural representation.
Embodiment
Below in conjunction with Figure of description and embodiment the present invention is done detailed description.
Software and hardware cooperating simulation/verification method of the present invention carries out software development/operation for using the CPU in running software terminal (like PC) the simulation SoC design, in emulation/checking hardware, carries out software development.Alleged SoC design is meant SoC in flow (TapOut) technological form before among the present invention, and it comprises relevant document, code, and information such as domain.
Software and hardware cooperating simulation/verification method of the present invention is applicable to the stage of on FPGA, carrying out hardware verification.At this moment, the realization of other hardware components in FPGA in the SoC design except that CPU comprises on-chip bus (AXI, AHB etc.), and the various IP that has the on-chip bus interface.Use the software development environment (C and C++, GNU gcc etc.) on the PC (PC) to accomplish exploitation and compiling, can on PC, move SoC software, accomplish debugging SOC software and hardware.
Software and hardware cooperating simulation/verification method of the present invention has used PC to simulate the CPU among the SoC, so need not compile to the CPU among the specific SoC, does not promptly need the process of cross compile.Can carry out the exploitation of the driver of independent IP before entering system in that CPU is integrated, the software developer can participate in project as early as possible, and the quickening development of projects in the shortening cycle, reduces cost.
The key step of this method comprises:
The SoC design map is gone into FPGA;
The SoC design is connected to the running software terminal through bus master and FPGA communication facilities;
Running software terminal development SoC design software and operation are sent pumping signal to the SoC design;
SoC design responsing excitation signal, response signal feeds back to said running software terminal.
Through above-mentioned steps, simple, be prone to realize software and hardware cooperating simulation/checking capablely, when not influencing simulation hardware/checking, carried out the checking of software, respond well.
In the said method, the running software terminal connects said to FPGA through communication facilities, and the simulation that software development/operation realizes FPGA is gone up CPU in the SoC design is carried out at the running software terminal.That is, come out the cpu function in the SoC design is abstract, use the running software terminal to simulate its behavior, thereby software development and particular CPU have nothing to do, and have reusability.Can in different SoC projects, reuse this device, be convenient to the software and hardware cooperating simulation/checking of SoC design.
In order to realize said method, software and hardware cooperating simulation/demo plant of the present invention comprises FPGA and the running software terminal with software-development function and/or operation function at least.Be mapped into the SoC design of no CPU in the FPGA; SoC designs connecting bus main equipment and FPGA communication facilities successively, and communication facilities connects the running software terminal.Bus master is converted into the read-write operation of software the read-write operation of bus.
Used PC to simulate the CPU in the SoC design, need not compile, therefore do not needed the process of cross compile, realized software and hardware cooperating simulation/checking to the CPU in the specific SoC design.The software developer can participate in project as early as possible, accelerates development of projects, in the shortening cycle, reduces cost.
The running software terminal comprises software module and running software terminal communication equipment (like USB, serial ports, PCI etc.).Running software terminal communication equipment one end is connected to the API of software module, and the other end is connected to FPGA communication facilities (with the corresponding equipment of communication facilities on the PC, like USB, serial ports etc.).Running software terminal communication equipment, FPGA communication facilities and communication line are between the two formed communication unit jointly, become the passage of the information transmission between running software terminal and the FPGA.
API has partly isolated the operation of software through peripheral hardware on the pc access SoC sheet, and CPU among the SoC is encapsulated the visit of peripheral hardware on the sheet.See that from software developer's angle CPU and peripheral hardware mutual only needs to carry out read-write operation and get final product, therefore need provide API to these kinds situation to the software developer.When real CPU is integrated into SoC, only need these API be replaced with the corresponding read-write operation of CPU and get final product.
The API that provides among the present invention comprises: ReadApi (), WriteApi (), WaitIntr (), OpenChannel () and CloseChannel ();
ReadApi () is to the read operation of SoC peripheral hardware;
WriteApi () is to the write operation of SoC peripheral hardware;
WaitIntr () waits for the SoC terminal operation, the hardware interrupts of inspection SoC;
OpenChannel () enables software and hardware cooperating simulation/demo plant of the present invention, opens communication facilities, communicates;
CloseChannel () closes software and hardware cooperating simulation/demo plant of the present invention, communication close equipment.
Convert the read-write operation on the bus into through read-write operation, the operation of CPU on the emulation bus with software.Miscellaneous equipment in SoC, bus Master is identical with the operation of CPU to the operation of bus.Bus master comprises scheduler module Schecduler, configuration module CONFIG, read through model READ, writing module WRITE, memory module, synchronization module Sync and bus module for reading and writing BUS_RW.
Scheduler module Schecduler: scheduling configuration module CONFIG, read through model READ and writing module WRITE accomplish layoutprocedure and read-write operation to the operation of FPGA communication facilities.
Configuration module CONFIG: accomplish configuration, open the FPGA communication facilities, for the information transmission between FPGA communication facilities and the running software terminal communication equipment is prepared to the FPGA communication facilities.
Read through model READ: from the FPGA communication facilities, read data from the running software terminal, and with the gained data storage in memory module.
Writing module WRITE: the data from the SoC peripheral hardware of storing in the memory module are write in the FPGA communication facilities, be sent to the running software terminal.
Memory module: the data in the storage read-write process have the synchronous effect of data-signal between communication clock territory and the SoC bus clock territory that makes.
Synchronization module Sync: and memory module makes between communication clock territory and the SoC bus clock territory data-signal synchronous jointly.
Bus module for reading and writing BUS_RW: the data in the memory module are write on the SoC bus, perhaps the data of SoC are write in the memory module.
Being based upon alternately on certain communication protocol of data between software section and the SoC is to use UART as the communication protocol of communicator and the concrete realization of communication process below.
Communication protocol comprises 9 Byte, and wherein, Byte1 describes communication type, and Byte2-Byte5 describes 32 bit address, and Byte6-Byte9 describes 32 data; Said communication type comprises reading and writing and interruption.
Synchronous IO (block type) is adopted in communication, because CPU just carries out next bar instruction after when carrying out read-write operation, waiting this instruction complete.Communicate by letter between running software terminal and the SoC peripheral hardware and adopt two step handshake mechanisms, carry out write operation, read operation and wait interrupt operation.
The step of write operation comprises: write communication protocol address and data, wait for FPGA return state continued execution command.
The step of read operation comprises: write the communication protocol address, wait for after the running software terminal receives data and returning, continue execution command.
The step of waiting for interrupt operation comprises: waits for receiving data until the running software terminal, and the inspection data type, data type is to interrupt then returning, and continues to carry out; The non-interruption of data type is reporting errors then.
Preferred embodiment one: in FPGA, shine upon SoC design to be verified with the method for burning.PC is through the USB on it, and serial ports, communication facilitiess such as PCI connect FPGA and go up communication facilitiess such as corresponding USB, serial ports or PCI, and FPGA communication facilities connecting bus main equipment, bus master connect the SoC design.PC has successfully simulated the CPU among the SoC.SoC is designed to the realization of other hardware components in FPGA except that CPU, comprises on-chip bus (AXI, AHB etc.), and the various IP that has the on-chip bus interface.
Use the C/C++ compiler (like GNU GCC etc.) of PC environment the SoC software translating to be become the binary file of target machine as PC, the USB IP drive software of exploitation SoC design, and operation.PC sends pumping signal to the SoC design, and this pumping signal of SoC design response feeds back to PC with response signal.Operation SoC software on PC.
The API that uses comprises: ReadApi (), WriteApi (), WaitIntr (), OpenChannel () and CloseChannel ().
What this operation was directed against is the SoC software development, and software development can be carried out with hardware verification simultaneously, has improved efficient, has shortened the construction cycle.
Preferred embodiment two: with the process that be applied as example explanation hardware verification of software and hardware cooperating simulation/demo plant of the present invention in DDRII SDRAM IP (IP core) checking.
Be downloaded among the FPGA after the SoC that band is comprised the no CPU of DDRII SDRAM IP uses the corresponding compilation tool QuartusII compiling of FPGA, then this FPGA is equivalent to the actual chips of SoC.
FPGA is connected to the running software terminal PC.The concrete grammar that connects is promptly: the communication facilities of FPGA is connected with the communication facilities at running software terminal, forms communication unit jointly, the information transmission between realization FPGA and the running software terminal.
Use c/c++ to write drive software at the running software terminal.Visit the ReadAPI/WriteAPI that the register of SoC among the FPGA then uses this device to provide if desired, wait for and interrupt using WaitIntr ().Drive software comprises configuration DDRII SDRAM IP; Wait for that the DDRII terminal takes place; In DDRII SDRAM, write data, whether sense data from DDRII SDRAM, the data that relatively write and the data of reading be consistent and at running software end print object information.
The software program that compiling and operation are write.
This device is with simulating real read-write requests on the bus of software to read-write SoC in FPGA of SoC register and storer; In the IP that has the on-chip bus interface, pass software with the data transmission of writing it is said that total will be read from the IP that has the on-chip bus interface.
Preferred embodiment three: with the process that be applied as example explanation hardware verification of software and hardware cooperating simulation/demo plant of the present invention in DDRII SDRAM IP (IP core) checking.
Be downloaded among the FPGA after the SoC that band is comprised the no CPU of DDRII SDRAM IP uses the corresponding compilation tool ISE compiling of FPGA, then this FPGA is equivalent to the actual chips of SoC.
FPGA is connected to the running software terminal PC.The concrete grammar that connects is promptly: the communication facilities of FPGA is connected with the communication facilities at running software terminal, forms communication unit jointly, the information transmission between realization FPGA and the running software terminal.
Use c/c++ to write drive software at the running software terminal.Visit the ReadAPI/WriteAPI that the storer of SoC among the FPGA then uses this device to provide if desired, wait for and interrupt using WaitIntr ().Drive software comprises configuration DDRII SDRAM IP; Wait for that the DDRII terminal takes place; In DDRII SDRAM, write data, whether sense data from DDRII SDRAM, the data that relatively write and the data of reading be consistent and at running software end print object information.
The software program that compiling and operation are write.
This device is with simulating real read-write requests on the bus of software to read-write SoC in FPGA of SoC register and storer; In the IP that has the on-chip bus interface, pass software with the data transmission of writing it is said that total will be read from the IP that has the on-chip bus interface.
In preferred embodiment two and preferred embodiment three, see that from hardware to be measured the implementation of software is:
1. the cpu port of simulating from this device sends the read-write to the register of DDRII SDRAM IP successively, accomplishes the configuration to DDRII SDRAM IP.
2.CPU port is no longer initiated read-write, up to interrupting generation.
3. after interrupt taking place, the port of the CPU that simulates from this device sends the read-write to DDRII SDRAM storer again.
See that from the PC end implementation of software is:
1. some address is read and write, accomplished configuration DDRII SDRAM IP register.
2. wait for and interrupt (carry out WaitIntr (), withdraw from behind the interrupting information of wait reception arrival FPGA), this process is not initiated any read-write to SoC among the FPGA.
3. after interrupting withdrawing from, the DDRII SDRAM storer of FPGA end is read and write.
4. the data of relatively reading and writing, and, be convenient to debugging with object information (PC) printing at the running software terminal.
More than; Be merely preferred embodiment of the present invention, but protection scope of the present invention is not limited thereto, any technician who is familiar with the present technique field is in the technical scope that the present invention discloses; The variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain that claim was defined.
Claims (10)
1. software and hardware cooperating simulation/verification method is characterized in that: said method is carried out software development/operation for using the CPU in the running software terminal simulation SoC design, in emulation/checking hardware, carries out software development; Said method comprises the steps:
The SoC design map is gone into FPGA;
Said SoC design is connected to the running software terminal through bus master and FPGA communication facilities;
Said running software terminal development SoC design software and operation are sent pumping signal to the SoC design;
Said SoC design responsing excitation signal, response signal feeds back to said running software terminal.
2. software and hardware cooperating simulation/verification method according to claim 1; It is characterized in that: said running software terminal is connected to said FPGA through communication facilities, and the simulation that software development/operation realizes FPGA is gone up CPU in the SoC design is carried out at said running software terminal.
3. software and hardware cooperating simulation/demo plant is characterized in that: said device comprises FPGA and the running software terminal with software-development function and/or operation function, and the SoC that is mapped into no CPU in the said FPGA designs; Said SoC designs connecting bus main equipment and FPGA communication facilities successively, and said communication facilities connects the running software terminal; Bus master is converted into the read-write operation of software the read-write operation of bus.
4. software and hardware cooperating simulation/demo plant according to claim 3 is characterized in that, said running software terminal comprises software module and running software terminal communication equipment, and said running software terminal communication equipment is connected to the API of software module; Said running software terminal communication equipment connects the FPGA communication facilities.
5. software and hardware cooperating simulation/demo plant according to claim 4 is characterized in that, said API comprises: ReadApi (), WriteApi (), WaitIntr (), OpenChannel () and CloseChannel ();
ReadApi () is to the read operation of SoC peripheral hardware;
WriteApi () is to the write operation of SoC peripheral hardware;
WaitIntr () waits for the SoC terminal operation, the hardware interrupts of inspection SoC;
OpenChannel () enables said software and hardware cooperating simulation/demo plant, opens communication facilities, communicates;
CloseChannel () closes said software and hardware cooperating simulation/demo plant, communication close equipment.
6. software and hardware cooperating simulation/demo plant according to claim 4 is characterized in that, the software development environment of said software module is at least a among C, C++ or the GNU gcc.
7. software and hardware cooperating simulation/demo plant according to claim 3 is characterized in that, said bus master comprises scheduler module, configuration module, read through model, writing module, memory module, synchronization module and bus module for reading and writing;
Scheduler module, scheduling configuration module, read through model and writing module are accomplished layoutprocedure and read-write operation to the operation of FPGA communication facilities;
Configuration module is accomplished the configuration to the FPGA communication facilities, opens the FPGA communication facilities, for the information transmission between FPGA communication facilities and the running software terminal communication equipment is prepared;
Read through model reads the data from the running software terminal from the FPGA communication facilities, and with the gained data storage in memory module;
Writing module writes the data from the SoC peripheral hardware of storing in the memory module in the FPGA communication facilities, is sent to the running software terminal;
Memory module, the data in the storage read-write process have the synchronous effect of data-signal between communication clock territory and the SoC bus clock territory that makes;
Synchronization module, and memory module makes between communication clock territory and the SoC bus clock territory data-signal synchronous jointly;
The bus module for reading and writing is write the data in the memory module on the SoC bus, perhaps the data of SoC is write in the memory module.
8. software and hardware cooperating simulation/demo plant according to claim 3 is characterized in that, communicates by letter between said running software terminal and the SoC peripheral hardware and adopts two step handshake mechanisms, carries out write operation, read operation and wait interrupt operation;
The step of write operation comprises: write communication protocol address and data, wait for FPGA return state continued execution command;
The step of read operation comprises: write the communication protocol address, wait for after communication protocol receives data and returning, continue execution command;
The step of waiting for interrupt operation comprises: waits for receiving data until communication protocol, and the inspection data type, data type is to interrupt then returning, and continues to carry out; The non-interruption of data type is reporting errors then.
9. software and hardware cooperating simulation/demo plant according to claim 8 is characterized in that: said communication protocol comprises 9 Byte, and wherein, Byte1 describes communication type, and Byte2-Byte5 describes 32 bit address, and Byte6-Byte9 describes 32 data.
10. software and hardware cooperating simulation/demo plant according to claim 9 is characterized in that: said communication type comprises reading and writing and interruption.
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