CN107766619A - The method and apparatus that FPGA prototype verification is carried out to chip - Google Patents
The method and apparatus that FPGA prototype verification is carried out to chip Download PDFInfo
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- CN107766619A CN107766619A CN201710883929.7A CN201710883929A CN107766619A CN 107766619 A CN107766619 A CN 107766619A CN 201710883929 A CN201710883929 A CN 201710883929A CN 107766619 A CN107766619 A CN 107766619A
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Abstract
The embodiment of the present invention provides a kind of method and apparatus that FPGA prototype verification is carried out to chip.The method that the present invention carries out FPGA prototype verification to chip, including：Extraction belongs to the first UPF instructions of the first power management Attribute class from the unified power management form UPF files of chip；The hierarchical structure designed according to the Method at Register Transfer Level RTL file construction logic of chip；The first UPF instructions are read one by one, are searched and the corresponding logic unit of the first UPF instructions in the hierarchical structure；The RTL code of logic unit described in the attribute modification instructed according to the first UPF, FPGA files are generated, and FPGA prototype verification is carried out to the chip using the FPGA files.The embodiment of the present invention can be on conventional FPGA in Analogous Integrated Electronic Circuits power management behavior so that FPGA logic behavior can be consistent with integrated circuit, and effective reference frame is provided to chip design.
Description
Technical field
The present embodiments relate to electronic technology, more particularly to a kind of method and dress that FPGA prototype verification is carried out to chip
Put.
Background technology
With developing rapidly for computer technology and microelectric technique, the application field of chip (chip) is more and more extensive.
Chip is the silicon chip for including integrated circuit (Integrated Circuit, abbreviation IC), its volume very little, often computer or
A part for other electronic equipments.Wherein, integrated circuit is exactly a number of conventional electronic component, such as resistance, electric capacity, crystalline substance
Line between body pipe etc., and above-mentioned electronic component, the electricity with specific function integrated by semiconductor technology
Road.With the rapid development of semiconductor technology and the raising of working frequency of chip, the power consumption of chip increases sharply, and the increasing of power consumption
The increase and the decline of reliability for adding and chip caloric value being caused.Therefore, power consumption has become one in IC design
Individual significant consideration.In order that product is more competitive, the requirement to chip design pursues high-performance, small area from simple
Switch to performance, area, power consumption composite request.
Chip designs the checking for generally including chip, and the checking of chip is exactly to verify whether designed logical code meets
Expected requirement, if meet the specification defined originally.With the increase of chip-scale, chip design in verify needs when
Between it is increasingly longer, the ratio for accounting for the whole design cycle is increasing.In order to improve verifying speed, there are a variety of verification methods.Than
Such as dynamic simulation, static check, dummy model, hardware-accelerated, field programmable gate array (Field-Programmable
Gate Array, abbreviation FPGA) prototype verification etc..Wherein due to the development of FPGA techniques and technology, its speed, capacity and density
All greatly increase, power consumption and cost are constantly reducing so that the prototype verification based on FPGA is widely used.Also,
FPGA prototype verification designs for the basic logic in ordinary numbers circuit, has and matches well, but FPGA prototype verification
The digital circuit for needing to carry out low power consumption control can not be verified well.
The content of the invention
The embodiment of the present invention provides a kind of method and apparatus that FPGA prototype verification is carried out to chip, to realize in routine
Power management behavior in the upper Analogous Integrated Electronic Circuits of FPGA so that FPGA logic behavior can be consistent with integrated circuit, right
Chip design provides effective reference frame.
In a first aspect, the embodiment of the present invention provides a kind of method that FPGA prototype verification is carried out to chip, including：
Extraction belongs to the first UPF of the first power management Attribute class from the unified power management form UPF files of chip
Instruction, the first power management Attribute class include shut-off controlled attribute, power switch attribute and holding register attribute；
The hierarchical structure designed according to the Method at Register Transfer Level RTL file construction logic of chip；
The first UPF instructions are read one by one, and patrol corresponding with the first UPF instructions is searched in the hierarchical structure
Collect unit；
The RTL code of logic unit described in the attribute modification instructed according to the first UPF, generate FPGA files, and profit
FPGA prototype verification is carried out to the chip with the FPGA files.
Second aspect, the embodiment of the present invention provide a kind of device that FPGA prototype verification is carried out to chip, including：
Memory, for storing computer program；
Processor, for performing the computer program, to realize the method as described in above-mentioned first aspect.
The third aspect, the embodiment of the present invention provide a kind of computer-readable storage medium, including：The computer-readable storage medium is used
In storage computer program, for realizing the method described in above-mentioned first aspect when the computer program performs.
The method and apparatus that the embodiment of the present invention carries out FPGA prototype verification to chip, by from the UPF files of chip
Extraction belong to the first power management Attribute class the first UPF instruction, the first power management Attribute class include shut-off controlled attribute,
Power switch attribute and holding register attribute, the hierarchical structure designed according to the RTL file construction logic of chip, read one by one
First UPF is instructed, and lookup and the first corresponding logic unit of UPF instructions, refer to according to the first UPF in the hierarchical structure
The RTL code of the attribute modification of the order logic unit, FPGA files are generated, and the chip is carried out using the FPGA files
FPGA prototype verification, so as to the power management behavior in the Analogous Integrated Electronic Circuits on conventional FPGA so that FPGA logic
Behavior can be consistent with integrated circuit, and effective reference frame is provided to chip design.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are this hairs
Some bright embodiments, for those of ordinary skill in the art, without having to pay creative labor, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is the flow chart for the embodiment of the method one that the present invention carries out FPGA prototype verification to chip；
Fig. 2 is the flow chart that the present invention applies example two to the method for chip progress FPGA prototype verification；
Fig. 3 is to realize the schematic diagram that FPGA prototype verification method is carried out to chip under a kind of compilation tool of the present invention；
Fig. 4 is the structural representation for the device embodiment one that the present invention carries out FPGA prototype verification to chip.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
Part of the embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
The low power dissipation design of the integrated circuit of chip, which is mainly reflected in, reduces quiescent dissipation and dynamic upset rate.Wherein,
Reducing quiescent dissipation can be by reducing supply voltage, closing power supply and realized using high-threshold transistors.Dynamic is reduced to turn over
Rate of rotation can be realized by collaboration optimization, the optimization of logic circuit and the closing inoperative clock of software and hardware.For the latter,
Directly it can be embodied in Method at Register Transfer Level (RegisterTransfer Level, abbreviation RTL) design.For preceding
Person, unified power management form (Unified Power Format, abbreviation UPF) standard can be used, describes integrated circuit
Power managed behavior.That is RTL is the description of the logic realization of circuit, and UPF is the description of the attribute behavior of power management, the two knot
The behaviour of integrated circuit can completely be described by closing.RTL design and UPF designs are passed through to the volume of integrated circuit design tool
Translate, obtain the netlist of integrated circuit and be accurate to the power supply description of module and gate, further carry out physics realization,
To obtain complete IC Layout.
Wherein, the power management attribute behavior of UPF descriptions can include：1st, power distribution structure：Power domain, power supply connect
Line, shut-off control；2nd, power policies：Power supply status table, supply voltage；3rd, line related management device：Isolating device, voltage turn
Parallel operation part, power switch, holding register.
The power management attribute behavior that above-mentioned UPF is described is divided into two classes by the embodiment of the present invention, is specifically included：First power supply
Management attribute class and second source management attribute class, wherein, the first power management Attribute class specifically includes shut-off controlled attribute, electricity
Source switch attribute and holding register attribute, second source management attribute category information include power supply Domain Properties, power supply line attribute,
Power supply status Table Properties, supply voltage attribute, isolating device attribute and voltage conversion device attribute.
FPGA simulated implementations can be used by belonging to the instruction of the first power management Attribute class in UPF files, be belonged in UPF files
It then can be generally directly realized by the instruction of second source management attribute class using FPGA, belong to second source management attribute class
Instruction can be as the auxiliary information of FPGA prototype verification method of the embodiment of the present invention.
Wherein, using the specific implementation for the instruction for belonging to the first power management Attribute class in FPGA simulated implementation UPF files
Mode may refer to table 1.
The power management attribute of table 1 first and FPGA implementation method corresponding table
By the extraction instructed to the UPF for belonging to the first power management Attribute class in table 1 in UPF files and changing
Corresponding RTL code, standard is realized with meet FPGA, so as to the power supply pipe in the Analogous Integrated Electronic Circuits on conventional FPGA
Reason behavior so that FPGA logic behavior can be consistent with integrated circuit.Checking is realized by the method for the embodiment of the present invention
Whether power consumption behavior influences the normal behaviour of integrated circuit, and effective reference frame is provided to chip design.
Fig. 1 is the flow chart for the embodiment of the method one that the present invention carries out FPGA prototype verification to chip, as shown in figure 1, this
The method of embodiment can include：
Step 101, extraction belongs to the first UPF instructions of the first power management Attribute class from the UPF files of chip, described
First power management Attribute class includes shut-off controlled attribute, power switch attribute and holding register attribute.
Wherein, UPF files are used for the behavior for describing the low-power dissipation power supply management of the chip, and the form of UPF files can be
.upf, UPF files include one or more of UPF instructions.
Specifically, the first UPF instructions for belonging to the first power management Attribute class are extracted from the UPF files.
Step 102, the hierarchical structure designed according to the RTL file construction logic of chip.
Wherein, RTL file is used for the logic realization for describing the integrated circuit of the chip, and the form of RTL file can be
.v.vhd, RTL file includes one or more of RTL instructions.
Specifically, the hierarchical structure of the RTL instruction construction logic designs in the RTL file, the hierarchical structure can be with
It is hierarchical tree.
Step 103, the first UPF instructions are read one by one, search in the hierarchical structure and instructed with the first UPF
Corresponding logic unit.
Step 104, according to the first UPF instruct attribute modification described in logic unit RTL code, generation FPGA text
Part, and FPGA prototype verification is carried out to the chip using the FPGA files.
Specifically, can according to extracted in step 101 belong to the first power management Attribute class the first UPF instruction and
The corresponding relation of table 1 changes the RTL generations with the corresponding logic unit of the first UPF instructions in the hierarchical structure of logical design
Code, generate FPGA files.
A kind of achievable mode, the first power management Attribute class can be belonged to what is extracted in every step 101 respectively
The first UPF instructions corresponding to the RTL code of logic unit modify, concrete modification mode can the first UPF according to
The attribute information of instruction finds corresponding FPGA implementation method in table 1, and changing the UPF using the FPGA implementation method refers to
The RTL code of logic unit corresponding to order.
The present embodiment, the first UPF that the first power management Attribute class is belonged to by being extracted from the UPF files of chip refer to
Order, the first power management Attribute class includes shut-off controlled attribute, power switch attribute and holding register attribute, according to chip
The design of RTL file construction logic hierarchical structure, read the first UPF instruction one by one, searched in the hierarchical structure
With the corresponding logic unit of the first UPF instructions, logic unit described in the attribute modification instructed according to the first UPF
RTL code, generate FPGA files, and using the FPGA files to the chip progress FPGA prototype verification, so as to
Power management behavior on conventional FPGA in Analogous Integrated Electronic Circuits so that FPGA logic behavior can be with integrated circuit phase one
Cause, effective reference frame is provided to chip design.
Several specific embodiments are used below, and the technical scheme of embodiment of the method shown in Fig. 1 is described in detail.
Fig. 2 is the flow chart for the embodiment of the method two that the present invention carries out FPGA prototype verification to chip, as shown in Fig. 2 this
The method of embodiment can include：
Step 201, meaning of a word parsing is carried out to all UPF instructions in UPF files, generate the language of every UPF instruction respectively
Justice tree.
Step 202, the power management Attribute class according to belonging to every UPF semantic trees instructed determine the UPF instructions.
Wherein, the specific explanations explanation of power management Attribute class may refer to above-described embodiment explanation, herein no longer
Repeat.
Step 203, extraction belong to the first UPF instructions of the first power management Attribute class.
Step 204, the hierarchical structure designed according to the RTL file construction logic of chip.
Step 205, the first UPF instructions are read one by one, search in the hierarchical structure and instructed with the first UPF
Corresponding logic unit.
Wherein, the specific explanations of step 204 to step 205 illustrate the step 102 and step that may refer to above-described embodiment
103 explanation, here is omitted.
Step 206, according to the first UPF instruct attribute modification described in logic unit RTL code, generation FPGA text
Part, and FPGA prototype verification is carried out to the chip using the FPGA files.
Optionally, the method for the embodiment of the present invention can also include：Belong to second source management from UPF files extraction
The 2nd UPF instructions of Attribute class, the second source management attribute class include power supply Domain Properties, power supply line attribute, power supply shape
State Table Properties, supply voltage attribute, isolating device attribute and voltage conversion device attribute, the 2nd UPF instructions are deposited
Storage.Wherein, belonging to the UPF instructions of second source management attribute class can be stored as auxiliary information, the second source pipe
Reason Attribute class UPF instruction can be directly realized by using FPGA, thereby using the second source management attribute class UPF instruction and
Using the FPGA files that generation is instructed according to the UPF of the first power management Attribute class, it is former that complete FPGA is carried out to the chip
Type is verified.
Optionally, above-mentioned the 2nd UPF instructions for belonging to second source management attribute class from UPF files extraction, specifically
It can include：Meaning of a word parsing is carried out to all UPF instructions in UPF files, generates the semantic tree of every UPF instruction, root respectively
The power management Attribute class belonging to the UPF instructions is determined according to the semantic tree of every UPF instruction, extraction belongs to second source management
The first UPF instructions of Attribute class.
It should be understood that after step 201 to step 202 is performed, can be instructed according to all UPF in the UPF files
Power management Attribute class extracts the first UPF instructions for belonging to the first power management Attribute class and belongs to second source management attribute
The 2nd UPF instructions of class.
Optionally, in above-mentioned steps 206 according to the first UPF instruct attribute modification described in logic unit RTL generations
Code, specific implementation can be：When the attribute of the first UPF instructions is the shut-off controlled attribute, according to the pass
Disconnected controlled attribute changes the RTL code of the logic unit；When the attribute of the first UPF instructions is the power switch attribute
When, according to it is described state power switch attribute modification described in logic unit RTL code；When the attribute of the first UPF instructions is
During the holding register attribute, according to the RTL code of logic unit described in the holding register attribute modification.
Wherein, the RTL code of the logic unit according to the power switch attribute modification, can specifically include：
The additional reset control that the power switch attribute instructed according to the first UPF increases the register in the logic unit is patrolled
Volume；The RTL code of the logic unit is changed according to the additional reset control logic, the amended logic unit
RTL code meets to reset the register in the logic unit in power-off.
Wherein, the RTL code that the logic unit is changed according to the shut-off controlled attribute, can specifically include：
The shut-off controlled attribute instructed according to the first UPF generates corresponding RTL code；By the RTL code of generation described in
In the RTL code of logic unit.
Wherein, the RTL code of the logic unit according to the holding register attribute modification, can specifically be wrapped
Include：The holding register attribute instructed according to the first UPF determines to keep control logic；Repaiied according to the holding control logic
Change the RTL code of the logic unit, the RTL code of the amended logic unit meets to reset institute in non-maintained status
State the register in logic unit.
Optionally, the chip involved by present example is specifically as follows SoC chip or BLE chips.
The present embodiment, by carrying out meaning of a word parsing to all UPF instructions in UPF files, every UPF instruction is generated respectively
Semantic tree, the power management Attribute class according to belonging to every UPF semantic tree instructed determines the UPF instructions, extraction belongs to
The first UPF instructions of first power management Attribute class, the hierarchical structure designed according to the RTL file construction logic of chip, one by one
The first UPF instructions are read, lookup and the corresponding logic unit of the first UPF instructions in the hierarchical structure, according to
The RTL code of logic unit described in the attribute modification of the first UPF instructions, generates FPGA files, and utilize FPGA texts
Part carries out FPGA prototype verification to the chip, so as to the power management row in the Analogous Integrated Electronic Circuits on conventional FPGA
For so that FPGA logic behavior can be consistent with integrated circuit, and effective reference frame is provided to chip design.
Also, by automatically analyzing the low-power consumption behavior of integrated circuit, classification extraction is carried out to respective behavior, so it is right
What RTL code modified to meet FPGA realizes standard, and manual amendment's code can be avoided to carry out what is introduced in verification process
Mistake.
Fig. 3 is that the schematic diagram that FPGA prototype verification method is carried out to chip is realized under a kind of compilation tool of the present invention, different
Realize that the specific implementation of each step included by the above method can be different under compilation tool, as shown in figure 3, this implementation
Above method embodiment is illustrated by taking a kind of compilation tool as an example for example：UPF morphological analyses (UPF can be used
Lexer) module and UPF syntactic analyses (UPF parser) module realize above-mentioned steps 201, use classification (classifier) mould
Block realizes above-mentioned steps 202 and step 203, and (HDL constructor) module and HDL design layerings (HDL are built using HDL
Design hierachy) module realizes above-mentioned steps 204, use power source features list (power feature list) module
The first UPF instructions are stored, and above-mentioned steps 205 and step 206 are realized using HDL generations (HDL generator) module.This
In with UPF files be specially * .upf, RTL file is specially to do for example, as shown in figure 3, * .upf are defeated exemplified by * .v*.vhd
Enter to UPF lexer modules, meaning of a word analysis carried out to the code in * .upf by the UPF lexer modules, generates token files,
The token files are inputted to UPF parser modules, syntactic analysis is carried out by the UPF parser modules, generates each
The semantic tree of UPF instructions, and export and give classifier modules, a plurality of UPF received is instructed by classifier modules
Semantic tree classified, classification here can be specially belong to the first power attributes management class according to semantic tree extraction the
One UPF instructs and belonged to the 2nd UPF instructions of second source management class, and its classification can also more refine, that is, extract and belong to
The first UPF instructions of controlled attribute are turned off, extract the first UPF instructions for belonging to power switch attribute, and extract and belong to
The first UPF instructions of holding register attribute, and in the corresponding form being saved in power feature list modules.
Another way, * .v*.vhd are inputted to HDL constructor modules, HDL constructor modules and are read in patrolling for * .v*.vhd
Function coded description is collected, and the hierarchical structure of construction logic design is stored into HDL design hierachy modules, afterwards,
Sorted power supply behavior is read one by one from power feature list modules by HDL generator modules, and is being patrolled
In the hierarchical structure of volume design corresponding logic unit is found, generation of being modified to the source RTL code of the logic unit is new
Code, i.e. HDL generator modules final output * .v*.vhd, the code in the * .v*.vhd are to contain power supply behavior
The FPGA code of the checking of description.
The present embodiment can be on conventional FPGA in Analogous Integrated Electronic Circuits power management behavior so that FPGA logical line
For can be consistent with integrated circuit, effective reference frame be provided to chip design.
Also, by automatically analyzing the low-power consumption behavior of integrated circuit, classification extraction is carried out to respective behavior, so it is right
What RTL code modified to meet FPGA realizes standard, and manual amendment's code can be avoided to carry out what is introduced in verification process
Mistake.
Below with have in UPF files the UFP of the behavior of power domain described below and power switch instruction：
create_power_domain PD_GPRS-elements{TOP/GPRS}
create_power_switch GPRS_sw-domain PD_GPRS
-output_supply_port{out SSGprs_switched.power}
-input_supply_port{in SSGprs_UnSwitched.power}
-control_port{NSleep TOP/PowerController/sleep}
-on_state{gprs_on_state in{！sleep}}
The UPF instructions in above-mentioned UPF files are handled using the method for embodiment illustrated in fig. 2, detailed process is as follows：
Carry out the semantic tree that meaning of a word parsing generates every UPF instruction, the semantic tree instructed according to every UPF respectively to above-mentioned UPF instructions
The power management Attribute class of the UPF instructions is determined, the power management Attribute class extraction instructed according to above-mentioned UPF belongs to the first electricity
The UPF instructions of source control Attribute class, and the UPF for belonging to the first power management Attribute class instructions are stored in power source features list
In, it can identify that power domain is PD_GPRS, control signal TOP/ by the processing instructed to above-mentioned UFP
PowerController/sleep, control polarity negate.And it can determine that the corresponding unit that power domain is PD_GPRS exists
TOP/GPRS modules.Corresponding to power switch behavior, instructed according to above-mentioned UPF and determine to need to carry out in FPGA code accordingly again
Bit manipulation, reset signal corresponding to TOP/GPRS is found in the hierarchical structure of logical design, and reset and patrol for this modification of signal
Volume so that the register in TOP/PowerController/sleep low level equally energy reseting module.The logical design
Hierarchical structure is determined according to RTL file.
Pass through the method that Function Prototypes checking is carried out using FPGA of the embodiment of the present invention, in that context it may be convenient to UPF will be carried
The integrated circuit of power supply behavior description, the checking of function original shape is carried out on FPGA, it is not necessary to manual amendment's code, avoid checking
During the mistake that is artificially introduced.
Fig. 4 is the structural representation for the device embodiment one that the present invention carries out FPGA prototype verification to chip, such as Fig. 4 institutes
Show, the device of the present embodiment can include：Memory 11 and processor 12, wherein, memory 11 is used to store computer program,
Processor 12, for performing the computer program, for performing the technical scheme of above method embodiment, its realization principle and
Technique effect is similar, and here is omitted.
When at least a portion function of the method for carrying out FPGA prototype verification to chip of the embodiment of the present invention passes through software
When realizing, the embodiment of the present invention also provides a kind of computer-readable storage medium, and computer-readable storage medium is above-mentioned to core for saving as
Piece carries out the computer software instructions of the device of FPGA prototype verification, when run on a computer so that computer can be with
Perform the various possible methods that FPGA prototype verification is carried out to chip in above method embodiment.Load and hold on computers
During the row computer executed instructions, it can produce whole or in part according to the flow or function described in the embodiment of the present invention.Institute
Stating computer instruction can be stored in computer-readable storage medium, or from a computer-readable storage medium to another computer
Storage medium is transmitted, the transmission can by wireless (such as cellular communication, infrared, short-distance wireless, microwave etc.) mode to
Another web-site, computer, server or data center are transmitted.The computer-readable storage medium can be computer
The data such as any usable medium that can be accessed or the server integrated comprising one or more usable mediums, data center
Storage device.The usable medium can be magnetic medium, (for example, floppy disk, hard disk, tape), optical medium (for example, DVD) or
Person's semiconductor medium (such as SSD) etc..
In addition, the embodiment of the present invention also provides a kind of computer program product for including instruction, i.e. software product, when its
When being run on computer so that computer performs various possible to chip progress FPGA prototype verification in above method embodiment
Method.Its implementing principle and technical effect is similar, and here is omitted.
One of ordinary skill in the art will appreciate that：Realizing all or part of step of above-mentioned each method embodiment can lead to
The related hardware of programmed instruction is crossed to complete.Foregoing program can be stored in a computer read/write memory medium.The journey
Sequence upon execution, execution the step of including above-mentioned each method embodiment；And foregoing storage medium includes：ROM, RAM, magnetic disc or
Person's CD etc. is various can be with the medium of store program codes.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than its limitations；To the greatest extent
The present invention is described in detail with reference to foregoing embodiments for pipe, it will be understood by those within the art that：Its according to
The technical scheme described in foregoing embodiments can so be modified, either which part or all technical characteristic are entered
Row equivalent substitution；And these modifications or replacement, the essence of appropriate technical solution is departed from various embodiments of the present invention technology
The scope of scheme.
Claims (10)
- A kind of 1. method that FPGA prototype verification is carried out to chip, it is characterised in that including：Extraction belongs to the first UPF instructions of the first power management Attribute class from the unified power management form UPF files of chip, The first power management Attribute class includes shut-off controlled attribute, power switch attribute and holding register attribute；The hierarchical structure designed according to the Method at Register Transfer Level RTL file construction logic of chip；The first UPF instructions are read one by one, and logic list corresponding with the first UPF instructions is searched in the hierarchical structure Member；The RTL code of logic unit described in the attribute modification instructed according to the first UPF, generates FPGA files, and utilize institute State FPGA files and FPGA prototype verification is carried out to the chip.
- 2. according to the method for claim 1, it is characterised in that extraction belongs to the first electricity in the UPF files from chip The first UPF instructions of source control Attribute class, including：Meaning of a word parsing is carried out to all UPF instructions in UPF files, generates the semantic tree of every UPF instruction respectively；Power management Attribute class according to belonging to every UPF semantic trees instructed determine the UPF instructions；Extraction belongs to the first UPF instructions of the first power management Attribute class.
- 3. method according to claim 1 or 2, it is characterised in that methods described also includes：Belong to the 2nd UPF instructions of second source management attribute class, the second source management attribute from UPF files extraction Class includes power supply Domain Properties, power supply line attribute, power supply status Table Properties, supply voltage attribute, isolating device attribute and voltage Switching device attribute；2nd UPF instructions are stored.
- 4. according to the method for claim 1, it is characterised in that the attribute modification institute instructed according to the first UPF The RTL code of logic unit is stated, including：When the attribute of the first UPF instructions is turns off controlled attribute, the logic is changed according to the shut-off controlled attribute The RTL code of unit；When the first UPF instruction attribute be power switch attribute when, according to it is described state power switch attribute modification described in patrol Collect the RTL code of unit；When the attribute of the first UPF instructions is holding register attribute, according to the holding register attribute modification The RTL code of logic unit.
- 5. according to the method for claim 4, it is characterised in that the logic according to the power switch attribute modification The RTL code of unit, including：The additional reset that the power switch attribute instructed according to the first UPF increases the register in the logic unit controls Logic；The RTL code of the logic unit is changed according to the additional reset control logic, the amended logic unit RTL code meets to reset the register in the logic unit in power-off.
- 6. according to the method for claim 4, it is characterised in that described that the logic is changed according to the shut-off controlled attribute The RTL code of unit, including：According to RTL code corresponding to the shut-off controlled attribute generation that the first UPF is instructed；The RTL code of generation is added in the RTL code of the logic unit.
- 7. according to the method for claim 4, it is characterised in that described to be patrolled according to the holding register attribute modification The RTL code of unit is collected, including：The holding register attribute instructed according to the first UPF determines to keep control logic；The RTL code of the logic unit, the RTL generations of the amended logic unit are changed according to the holding control logic Code meets to reset the register in the logic unit in non-maintained status.
- 8. according to the method described in any one of claim 1 to 7, it is characterised in that the chip is SoC chip or BLE chips.
- A kind of 9. device that FPGA prototype verification is carried out to chip, it is characterised in that including：Memory, for storing computer program；Processor, for performing the computer program, to realize the method as any one of claim 1-8.
- A kind of 10. computer-readable storage medium, it is characterised in that including：The computer-readable storage medium is used to store computer journey Sequence, for realizing the method as described in any one of claim 1 to 8 when the computer program performs.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109739705A (en) * | 2018-12-29 | 2019-05-10 | 西安智多晶微电子有限公司 | A kind of real-time debugging system of FPGA on piece and method |
| CN110399645A (en) * | 2019-06-28 | 2019-11-01 | 深圳忆联信息系统有限公司 | FPGA prototype verification acceleration system and implementation method based on solid state hard disk |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101233512A (en) * | 2005-07-29 | 2008-07-30 | 微软公司 | Intelligent SQL generation for persistent object retrieval |
| CN102521444A (en) * | 2011-12-08 | 2012-06-27 | 青岛海信信芯科技有限公司 | Cooperative simulation/verification method and device for software and hardware |
| US8954904B1 (en) * | 2013-04-30 | 2015-02-10 | Jasper Design Automation, Inc. | Veryifing low power functionality through RTL transformation |
| US9104824B1 (en) * | 2013-04-30 | 2015-08-11 | Jasper Design Automation, Inc. | Power aware retention flop list analysis and modification |
| US9141741B1 (en) * | 2013-10-29 | 2015-09-22 | Cadence Design Systems, Inc. | Methods, systems, and articles of manufacture for implementing mixed-signal electronic circuit designs with power data in standardized power formats |
| US9703921B1 (en) * | 2012-06-14 | 2017-07-11 | Cadence Design Systems, Inc. | Naturally connecting mixed-signal power networks in mixed-signal simulations |
-
2017
- 2017-09-26 CN CN201710883929.7A patent/CN107766619A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101233512A (en) * | 2005-07-29 | 2008-07-30 | 微软公司 | Intelligent SQL generation for persistent object retrieval |
| CN102521444A (en) * | 2011-12-08 | 2012-06-27 | 青岛海信信芯科技有限公司 | Cooperative simulation/verification method and device for software and hardware |
| US9703921B1 (en) * | 2012-06-14 | 2017-07-11 | Cadence Design Systems, Inc. | Naturally connecting mixed-signal power networks in mixed-signal simulations |
| US8954904B1 (en) * | 2013-04-30 | 2015-02-10 | Jasper Design Automation, Inc. | Veryifing low power functionality through RTL transformation |
| US9104824B1 (en) * | 2013-04-30 | 2015-08-11 | Jasper Design Automation, Inc. | Power aware retention flop list analysis and modification |
| US9141741B1 (en) * | 2013-10-29 | 2015-09-22 | Cadence Design Systems, Inc. | Methods, systems, and articles of manufacture for implementing mixed-signal electronic circuit designs with power data in standardized power formats |
Non-Patent Citations (1)
| Title |
|---|
| RANGEEN BASU ROY CHOWDHURY ET AL.: "AnyCore: A synthesizable RTL model for exploring and fabricating adaptive superscalar cores", 《2016 IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE (ISPASS)》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109739705A (en) * | 2018-12-29 | 2019-05-10 | 西安智多晶微电子有限公司 | A kind of real-time debugging system of FPGA on piece and method |
| CN110399645A (en) * | 2019-06-28 | 2019-11-01 | 深圳忆联信息系统有限公司 | FPGA prototype verification acceleration system and implementation method based on solid state hard disk |
| CN110399645B (en) * | 2019-06-28 | 2023-07-07 | 深圳忆联信息系统有限公司 | FPGA prototype verification acceleration system based on solid state disk and implementation method |
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