CN102201022A - Method and device for checking field programmable gate array (FPGA) - Google Patents
Method and device for checking field programmable gate array (FPGA) Download PDFInfo
- Publication number
- CN102201022A CN102201022A CN2011101092882A CN201110109288A CN102201022A CN 102201022 A CN102201022 A CN 102201022A CN 2011101092882 A CN2011101092882 A CN 2011101092882A CN 201110109288 A CN201110109288 A CN 201110109288A CN 102201022 A CN102201022 A CN 102201022A
- Authority
- CN
- China
- Prior art keywords
- module
- data
- detected
- address
- checking
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The embodiment of the invention discloses a method and a device for checking a field programmable gate array (FPGA) and relates to the field of integrated circuit design. Various intellectual property (IP) core checking requirements can be met and the universality is high. The method comprises the following steps of: compiling a preset exciting demand into a machine code, wherein the preset exciting demand is described by using a preset instruction set and the machine code can be identified by a processor; executing the machine code by the processor and generating exciting data; inputting the exciting data into a module to be detected; and checking whether the module to be detected is correct according to an output result of the module to be detected. The invention is mainly applied to checking the FPGA.
Description
Technical field
The present invention relates to the integrated circuit (IC) design field, relate in particular to the method and apparatus that is used for the FPGA checking.
Background technology
Along with the progress of integrated circuit processing technique and the raising of integrated circuit (IC) design level, increasing Memory Controller IP kernel (intellectual property core, Intellectual Property core) is integrated in the System on Chip/SoC (SoC).If will carry out the FPGA prototype verification to System on Chip/SoC, perhaps IP kernel is integrated on the System on Chip/SoC of realizing based on FPGA, can operate as normal on the FPGA platform for guaranteeing the Memory Controller IP kernel, need verify the Memory Controller IP kernel.
Because it is complicated to have the SoC of DDR/DDR2/DDR3SDRAM controller, NAND/NOR Flash ROM controller, 32 bit CPUs (central processing unit), so, when this SoC integral transplanting is carried out the FPGA prototype verification behind the FPGA platform, be difficult to the location for detected problem.
If with the SoC integral transplanting before the FPGA platform, can transplant and realize the FPGA checking to each Memory Controller IP kernel earlier, then can reduce the validation difficulty of SoC greatly, and easier problem to checking place positions.
Yet, in the prior art, when each IP kernel is verified, because the excitation requirement of every kind of IP kernel is realized by a cover specialized hardware, so when multiple IP kernel being verified for needs, then need to make up many relevant hardware structures, the IP kernel kind that same test platform can be handled has limitation, and versatility is relatively poor.
Summary of the invention
Embodiments of the invention provide a kind of method and apparatus of the FPGA of being used for checking, can satisfy multiple IP kernel checking needs, and versatility is better.
For achieving the above object, embodiments of the invention adopt following technical scheme:
A kind of method that is used for the FPGA checking comprises:
To preset excitation requirement and be compiled into machine code, described default excitation requirement is to use preset instruction set to describe, and described machine code can be discerned by processor;
Carry out described machine code by described processor, produce excited data;
Described excited data is imported module to be detected;
Whether correct according to the described module to be detected of the output result verification of described module to be detected.
A kind of device that is used for the FPGA checking comprises:
Compiler is used for default excitation requirement is compiled into machine code, and described default excitation requirement is to use preset instruction set to describe, and described machine code can be discerned by processor;
Processor is used to carry out described machine code, produces excited data;
Writing unit is used for described excited data is imported module to be detected;
Whether authentication unit is used for according to the described module to be detected of the output result verification of described module to be detected correct.
The method and apparatus that is used for the FPGA checking that the embodiment of the invention provides, adopt preset instruction set to describe excitation requirement, by compiler this excitation requirement is compiled into machine code, and carry out the machine code that converts to by excitation requirement by processor, and then generation excited data, height programmability in view of processor, and the dirigibility of preset instruction set description, overcome the problem of using a cover hardware circuit to realize the required excitation requirement of corresponding IP kernel in the prior art, can be applicable to the checking of multiple IP kernel flexibly, have good versatility.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
The process flow diagram of the method that is used for FPGA checking that Fig. 1 provides for the embodiment of the invention;
Fig. 2 provide for the embodiment of the invention another be used for the process flow diagram of the method for FPGA checking;
The structural drawing of the device that is used for FPGA checking that Fig. 3 provides for the embodiment of the invention;
Fig. 4 provide for the embodiment of the invention another be used for the structural drawing of the device of FPGA checking.
Fig. 5 provide for the embodiment of the invention another be used for the structural drawing of the device of FPGA checking
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that is obtained under the creative work prerequisite.
The embodiment of the invention provides a kind of method of the FPGA of being used for checking, as shown in Figure 1, may further comprise the steps:
101, will preset excitation requirement and be compiled into machine code, this default excitation requirement is to use preset instruction set to describe, and this machine code can be discerned by processor.
In order to produce excited data, at first, use compiler will adopt the excitation requirement of preset instruction set description to be compiled into the machine code that to be discerned by the processor in the present embodiment by processor.
102, carry out machine code by processor, produce excited data.
Processor is carried out the machine code after the compiler compiling, and produces the excited data that is used to verify module to be detected according to this machine code.
103, excited data is imported module to be detected.
In order to realize that treating detection module verifies, the excited data that processor produces is imported module to be detected, module to be detected is handled the data of input.
104, whether the output result verification module to be detected according to module to be detected is correct.
In module to be detected excited data is disposed, whether the output result is correct according to the output result verification module to be detected of module to be detected.
The method that is used for the FPGA checking that present embodiment provides, adopt preset instruction set to describe excitation requirement, by compiler this excitation requirement is compiled into machine code, and carry out the machine code that converts to by excitation requirement by processor, and then generation excited data, height programmability in view of processor, and the dirigibility of preset instruction set description, overcome the problem of using a cover hardware circuit to realize the required excitation requirement of corresponding IP kernel in the prior art, can be applicable to the checking of multiple IP kernel flexibly, have good versatility.
As a kind of improvement of present embodiment, the embodiment of the invention provides another kind to be used for the method for FPGA checking, as shown in Figure 2, may further comprise the steps:
201, read the source file that comprises excitation requirement that adopts preset instruction set to describe from program memory ROM (read-only memory, Read-Only Memory).
In order to make present embodiment can be applicable to the checking of multiple IP kernel flexibly, the embodiment of the invention adopts default instruction set to describe when excitation requirement is provided, and default instruction set can comprise:
Read instruction: be used for according to first burst-length from the first assigned address reading of data, form can be Read (first burst-length, first assigned address);
Write command: be used for first specific data being write second assigned address according to second burst-length, form can for Write (second burst-length, second assigned address, first specific data, 0, the first specific data 1 ...);
Read instruction continuously: be used for since the 3rd assigned address, get an address every default regular length, and from this address reading of data successively, form can be LoopRead (the 3rd assigned address is read number of times);
Continuous write command: be used for since second specific data, obtain data every first designated length, since first start address, get successively according to preset length and to write the address, form can be LoopWrite (first start address, second specific data, cycle index, first designated length, preset length);
Check instruction: be used for checking the 4th assigned address that form can be Check (the 4th assigned address, specific data) with specific data;
Continuous review instruction: be used for since second start address, obtain the address that equates with cycle index successively every the 3rd designated length,, obtain a plurality of data that increase progressively successively every second designated length since second initial data, with the data that get access to, since second initial data, write successively in each address that obtains, form can be LoopCheck (second start address, second initial data, cycle index, second designated length, the 3rd designated length).
Above-mentioned instruction set offers the function of user's form class like the C language, meets the style of C language, the man-machine interaction close friend.When IP kernel is verified, can write corresponding testing program according to the difference of checking IP kernel, thereby realize the versatility of this device when the different memory IP kernel is verified.
202, will preset excitation requirement and be compiled into machine code by compiler, this default excitation requirement is to use preset instruction set to describe, and this machine code can be discerned by processor.
In order to produce excited data by processor, at first, the program file that instruction set is formed is input to compiler, uses compiler will adopt the excitation requirement of preset instruction set description to be compiled into the machine code that can be discerned by the processor in the present embodiment.
Above-mentioned instruction set compiler can be compiled into the binary machine code of processor correspondence with the proving program that uses above-mentioned instruction set to form, and certain optimization ability is provided in transfer process.Compiler Optimization work on the ordinary meaning.Optimization is an important component part of compiler and since the work that compiler is translated into intermediate code with source program be mechanical, undertaken by fixed mode, therefore, the intermediate code of generation often has very big waste on time and space.When needs generate efficient object code, just must be optimized.
203,, produce excited data by the processor machine code.
Machine code by compiler output is stored among the ROM, the output terminal of this storer ROM and the input end of processor are connected, machine code after compiler will compile inputs to processor, processor is carried out the machine code after the compiler compiling, and produces the excited data that is used to verify module to be detected according to this machine code.This excited data comprises data message and address information.
204, excited data is converted to the read-write affairs that meet module interface consensus standard to be detected.
Processor is connected with protocol conversion module, after having obtained excited data, needing that this excited data is imported corresponding address handles, in order to determine the bus interface of this excited data correspondence, can excited data be converted to the read-write affairs that meet module interface consensus standard to be detected by protocol conversion module.
205, excited data is imported module to be detected.
After the bus interface of having obtained the excited data correspondence, can the excited data that processor produces be imported module to be detected according to this bus interface, module to be detected is handled the data of input.
206, whether the output result verification module to be detected according to module to be detected is correct.
In module to be detected excited data is disposed, whether the output result is correct according to the output result verification module to be detected of module to be detected.
Concrete, judge by authentication unit whether the output result of module to be detected and expected results satisfy the preset function relation, if the output result of module to be detected and expection knot satisfy the preset function relation, module then to be detected is correct, otherwise this module to be detected is incorrect.
The method that is used for the FPGA checking that present embodiment provides, adopt preset instruction set to describe excitation requirement, by compiler this excitation requirement is compiled into machine code, and carry out the machine code that converts to by excitation requirement by processor, and then generation excited data, height programmability in view of processor, and the dirigibility of preset instruction set description, overcome the problem of using a cover hardware circuit to realize the required excitation requirement of corresponding IP kernel in the prior art, can be applicable to the checking of multiple IP kernel flexibly, have good versatility.
The embodiment of the invention provides a kind of device of the FPGA of being used for checking, as shown in Figure 3, comprising: compiler 31, processor 32, writing unit 33, authentication unit 34.
Wherein, compiler 31 is used for default excitation requirement is compiled into machine code, and described default excitation requirement is to use preset instruction set to describe, and described machine code can be discerned by processor;
In order to produce excited data, at first, use compiler will adopt the excitation requirement of preset instruction set description to be compiled into the machine code that to be discerned by the processor in the present embodiment by processor.
Processor is carried out the machine code after the compiler compiling, and produces the excited data that is used to verify module to be detected according to this machine code.
In order to realize that treating detection module verifies, the excited data that processor produces is imported module to be detected, module to be detected is handled the data of input.
Whether authentication unit 34 is used for according to the described module to be detected of the output result verification of described module to be detected correct.
In module to be detected excited data is disposed, whether the output result is correct according to the output result verification module to be detected of module to be detected.
The device that is used for the FPGA checking that present embodiment provides, adopt preset instruction set to describe excitation requirement, by compiler this excitation requirement is compiled into machine code, and carry out the machine code that converts to by excitation requirement by processor, and then generation excited data, treating detection module by authentication module verifies, height programmability in view of processor, and the dirigibility of preset instruction set description, overcome the problem of using a cover hardware circuit to realize the required excitation requirement of corresponding IP kernel in the prior art, can be applicable to the checking of multiple IP kernel flexibly, have good versatility.
As a kind of improvement of present embodiment, the embodiment of the invention provides another kind to be used for the device of FPGA checking, as shown in Figure 4, comprising: reading unit 41, compiler 42, processor 43, protocol conversion module 44, writing unit 45, authentication unit 46.
Wherein, reading unit 41 is used to read the source file that comprises excitation requirement that adopts preset instruction set to describe.
Concrete, the default instruction set in the embodiment of the invention can comprise:
Read instruction: be used for according to first burst-length from the first assigned address reading of data, form can be Read (first burst-length, first assigned address);
Write command: be used for first specific data being write second assigned address according to second burst-length, form can for Write (second burst-length, second assigned address, first specific data, 0, the first specific data 1 ...);
Read instruction continuously: be used for since the 3rd assigned address, get an address every default regular length, and from this address reading of data successively, form can be LoopRead (the 3rd assigned address is read number of times);
Continuous write command: be used for since second specific data, obtain data every first designated length, since first start address, get successively according to preset length and to write the address, form can be LoopWrite (first start address, second specific data, cycle index, first designated length, preset length);
Check instruction: be used for checking the 4th assigned address that form can be Check (the 4th assigned address, specific data) with specific data;
Continuous review instruction: be used for since second start address, obtain the address that equates with cycle index successively every the 3rd designated length,, obtain a plurality of data that increase progressively successively every second designated length since second initial data, with the data that get access to, since second initial data, write successively in each address that obtains, form can be LoopCheck (second start address, second initial data, cycle index, second designated length, the 3rd designated length.
By the instruction of using function in the above-mentioned C of the being similar to language testing requirement to memory module can be described very easily.The machine code that the processor of the device that is used for the FPGA checking that compiler can provide the excitation requirement source file compile cost inventive embodiments of being write by above-mentioned instruction set can be carried out.
Every instruction in the above-mentioned instruction set can be compiled into 3 micro-orders: article one micro-order can comprise the type of this instruction and to the control information of external memory interface.The second micro-order can comprise address information; Article three, instruction can comprise data message.
In order to produce excited data, use compiler will adopt the excitation requirement of preset instruction set description to be compiled into the machine code that to be discerned by the processor in the present embodiment by processor.
Machine code by compiler output is stored among the ROM, the output terminal of this storer ROM and the input end of processor are connected, machine code after compiler will compile inputs to processor, processor is carried out the machine code after the compiler compiling, and produces the excited data that is used to verify module to be detected according to this machine code.
Machine code after the above-mentioned program memory ROM store compiled.It can use block RAM (random access memory, Random Access Memory) to realize in FPGA.Processor is from reading command wherein.
Above-mentioned processor is the part of comparatively core of the device of the whole FPGA of being used for checking.It carries out the machine code after the compiling, finishes the conversion of checking demand to memory I P kernel interface read-write affairs according to corresponding instruction control protocol modular converter, and then finishes the checking to memory I P nuclear.This processor relatively simple for structure, employed logical resource is less, can avoid improving because of the complexity of self whole debugging complexity.
Above-mentioned protocol conversion module can be converted to the read-write requests of processor the read-write affairs that meet memory I P kernel interface agreement.Comprise that the processor read-write requests is to AMBA (advanced microcontroller bus architecture, Advanced Microcontroller Bus Architecture) conversion of bus protocol, the processor read-write requests arrives OCP (in the chip agreement, On Chip Protocol) conversion of bus protocol, the processor read-write requests is to the conversion of WishBone bus protocol, and the processor read-write requests is to the conversion of Coreconnect (examining interconnected) bus protocol.Can be according to the corresponding conversion regime of different choice of actual storage IP kernel interface protocol.For simplified structure, when not needing protocol conversion function, can not be implemented among the FPGA.
In order to realize that treating detection module verifies, the excited data that processor produces is imported module to be detected, module to be detected is handled the data of input.
Whether authentication unit 46 is used for according to the described module to be detected of the output result verification of described module to be detected correct.
In module to be detected excited data is disposed, whether the output result is correct according to the output result verification module to be detected of module to be detected.
Concrete, authentication unit 46 judges whether the output result of module to be detected and expected results satisfy the preset function relation, if the output result of module to be detected and expection knot satisfy the preset function relation, module then to be detected is correct.
Processor in the embodiment of the invention can be CPU (central processing unit).
The device that is used for the FPGA checking that present embodiment provides, adopt preset instruction set to describe excitation requirement, by compiler this excitation requirement is compiled into machine code, and carry out the machine code that converts to by excitation requirement by processor, and then generation excited data, treating detection module by authentication module verifies, height programmability in view of processor, and the dirigibility of preset instruction set description, overcome the problem of using a cover hardware circuit to realize the required excitation requirement of corresponding IP kernel in the prior art, can be applicable to the checking of multiple IP kernel flexibly, have good versatility.
As an embodiment of the present embodiment, the embodiment of the invention provides the device of the following FPGA of being used for checking: comprising: reading unit 14, compiler 15, processor 16, CPU.
Wherein, CPU can comprise: programmable counter 1, program storage 2, first MUX 3, register file 4, address/data increase progressively module 8, bus interface module 9, second MUX 10, authentication unit 11, control module 12, status register 13.
Register file can comprise: control register 5, write data register 6, read data register 7.
As shown in Figure 5, the output terminal of reading unit 14 links to each other with the input end of compiler 15, and the output terminal of compiler 15 links to each other with the output terminal of program storage 2, and the output terminal of programmable counter 1 is connected to the input end of program storage 2; The output terminal of program storage 2 is connected to the input end of processor 16, one of them input end of the output terminal of processor 16 and first MUX 3 and the input end of control module 12; The output terminal of first MUX 3 is connected to the input end of register file 4; The output terminal of control register 5 is connected to the control input end of bus interface module 9 in the register file 4; The output terminal of address register is connected to the address input end that address/data increases progressively module 8 in the register file 4; The output terminal of write data register 6 is connected to address/data and increases progressively the data input pin of module 8 and an input end of authentication unit 11 in the register file 4; The output of read data register 7 is connected to an input end of authentication unit in the register file 4; Address input end, data output end that the address output end that address/data increases progressively module 8 is connected to bus interface module 9 are connected to the data input pin of bus interface module 8 and an input end of second MUX 10; Bus interface module 9 links to each other with the interface of outside IP kernel, and the read data output terminal of bus interface module 9 links to each other with an input end of second MUX 10 simultaneously; The output terminal of second MUX 10 links to each other with an input end of first MUX; The result of authentication unit outputs to status register 13; Control module 12 increases progressively module 8 with programmable counter 1, first MUX 3, register file 4, address/data, bus interface module 9 links to each other.
Concrete, programmable counter 1 is used for the variation of control program storage address.
Register file 4 inside comprise control register 5, address register, write data register 6 and read data register 7.Each register file data width is 32.Under the control of controller, register file can be saved in corresponding special function register with program storage or outside data of reading in.
Control register 5 is used to preserve the read-write control information to external memory storage, as information such as read/write operation information, data width information, burst-lengths.The degree of depth can be 1, and width can be 32bit.
Address register is used to preserve the address information of read-write operation.The degree of depth can be 1, and width can be 32bit.
Write data register 6 is used to preserve the data message of write operation.The degree of depth can be 1-16, can be according to the needs configuration of bus burst-length in the verification environment.Width can be 32bit.
Read data register 7 is used to preserve the data message of read operation.The degree of depth can be 1-16, can be according to the needs configuration of bus burst-length in the verification environment.Width can be 32bit.
Address when address/data increases progressively module 8 and is used to carry out continuous read/write instruction (LoopRead ()/LoopWrite ()/LoopCheck ()) and the increment operation of data.Address and data after this module increases progressively generation are delivered to external interface module. can select to export signal or the original signal that increases progressively dynamically according to the performed instruction of controller.
Bus interface module 9 is used for the control information of processor and reads and writes data being delivered to bus, carries out the mutual of data and control information with external bus interface.
The process that the device of the above-mentioned FPGA of being used for checking is carried out the IP kernel checking is:
1. reading unit 14 obtains the excitation requirement that adopts preset instruction set to describe from default excitation requirement source file.
2. compiler 15 instruction set that reading unit 14 is read is compiled into the machine code that processor can be discerned.
3. the machine code after will compiling downloads in the program storage 2.
4. under the effect of control module 13, the start address of instruction in the program storage 2 is pointed in programmable counter 1 address, and the instruction of program storage 2 output device sign indicating number forms is to control module 13.
5. control module 13 is obtained the instruction of machine code form from program storage 2, and controls the corresponding data path of first MUX, 3 selections according to the result of decoding, and decode results is stored in the register file 4.Fetched instruction comprises instruction type and external memory interface control information herein.First MUX, 3 option program storeies 2 are saved in control information in the control register 5 in the register file 4.
6. controller module 13 obtains the instruction of next bar machine code form.
7. control module 13 will be by the instruction decode of being got in the program storage 2, and controls first MUX 3 according to the result of decoding and select corresponding data path to store in the register file 4.Fetched instruction comprises address instruction herein, is used to specify the address that operation will be read and write.First MUX 3 selects to be connected to the path of program storage, and address information is stored in the address register 6 in the register file 4.
8. control module 13 is selected the content of execution according to fetched instruction decode results in the step 3.If be read operation, then processor is carried out machine code, generates the excited data stage.Otherwise continue to read next bar instruction, execution in step 7.
9. if decode results is not read operation (Read ()/LoopRead ()) in the step 3, controller module 13 control program counters 1 take off an instruction.Instruction is for comprising write data herein.Controller module 13 control first MUX 3 and register file 4 are put into data in the write data register 7.
10. according to the result of step 3 decoding,, then jump to step 6, reach the burst-length requirement until the data number if be burst write operations.
11. the beginning execute phase.If be read operation, then control information in the register file 4 and address information are passed to bus interface module 10, produce bus transaction.The data that controller module 13 controls second MUX 11 is selected from bus interface module 10, control MUX 3 is selected the data from MUX 11, and the read data that bus interface module 10 is received is delivered in the read data register 8 in the register file 4.If be continuous read operation (LoopRead ()), then address/data increases progressively the address after module 9 output increases progressively, otherwise exports the address in original and the address register 6.
If be write operation, then the control information in the register file 4, address information and data transfer are arrived bus interface module, begin a bus and write affairs.If be continuous write operation, then address/data increases progressively the address/data after module 9 output increases progressively, otherwise exports the address/data in original and address register 6 and the write data register 7.
If be verification operation, then controller module 13 at first carries out control information and data are sent to bus interface module 10, start a write operation, control second MUX 11 simultaneously and select to increase progressively the write data of module 9 from address/data, the data of selecting MUX 3 to select from second MUX 11 are saved in write data register in the register file 4 with write data.Then control information is sent to bus interface module 10, start a read operation, and 11 selections of control MUX are from the data of bus interface module 10, read data register 8. data review modules 12 that read data is saved in the register file 4 are finished comparison, the result is saved in status register 14.
12. programmable counter 1 address increases by 1, controller module 13 takes off an instruction.If instruction is not an end mark, then jump to step 3.
The embodiment of the invention has made up the general verification environment of storer class IP kernel on FPGA by a cover instruction set being provided, being used to carry out the better simply CPU of structure and the corresponding bus interface of this instruction set.Can finish the FPGA checking of IP kernel or subsystem comparatively quickly and easily, and different storer class IP kernels can general device, reduces the checking complexity.Realized when the FPGA of system transplanted the dividing and rule of go wrong (Bug), reduced the difficulty of system debug when Soc carried out prototype verification.Can finish the FPGA of IP kernel before the system integration quickly and easily and transplant, simplify positioning problems, and versatility be good, reusable.
When carrying out the FPGA prototype verification of SOC (system on a chip) SOC, the FPGA that the method and apparatus that is used for the FPGA checking that can use the embodiment of the invention to provide is finished the Memory Controller IP kernel transplants and checking, after device controller IP kernel to be stored is partly to a certain degree verified, again CPU part and other IP kernel of itself and high complexity are integrated, finish the integrated of total system and checking, thereby reduce the complexity of the whole debugging of SOC.
With the request of access to memory I P nuclear of bottom abstract be high-rise read, by the instruction set of using high-level class C diction function the checking demand that memory I P is examined is described; By using compiler compiling proving program to obtain the machine code of processor; By using processor, the checking request of complexity can be changed into read-write requests and be applied to Memory Controller IP kernel interface, and the read-write result is tested by protocol conversion module.
Through the above description of the embodiments, the those skilled in the art can be well understood to the present invention and can realize by the mode that software adds essential common hardware, can certainly pass through hardware, but the former is better embodiment under a lot of situation.Based on such understanding, the part that technical scheme of the present invention contributes to prior art in essence in other words can embody with the form of software product, this computer software product is stored in the storage medium that can read, floppy disk as computing machine, hard disk or CD etc., comprise some instructions with so that computer equipment (can be personal computer, server, the perhaps network equipment etc.) carry out the described method of each embodiment of the present invention.
The above; only be the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion by described protection domain with claim.
Claims (10)
1. a method that is used for the FPGA checking is characterized in that, comprising:
To preset excitation requirement and be compiled into machine code, described default excitation requirement is to use preset instruction set to describe, and described machine code can be discerned by processor;
Carry out described machine code by described processor, produce excited data;
Described excited data is imported module to be detected;
Whether correct according to the described module to be detected of the output result verification of described module to be detected.
2. the method that is used for the FPGA checking according to claim 1 is characterized in that described preset instruction set comprises:
Read instruction: be used for according to first burst-length from the first assigned address reading of data;
Write command: be used for specific data being write second assigned address according to second burst-length;
Read instruction continuously: be used for since the 3rd assigned address, get an address every default regular length, and from this address reading of data successively;
Continuous write command: be used for incremental data with first designated length and write and increase progressively the address;
Check instruction: be used for checking the 4th assigned address with specific data;
Continuous review instruction: be used for the address that increases progressively with incremental data continuous review second designated length of second designated length.
3. the method that is used for FPGA checking according to claim 1 is characterized in that, described described excited data is imported module to be detected before, described method also comprises:
Described excited data is converted to the read-write affairs that meet module interface consensus standard to be detected.
4. the method that is used for FPGA checking according to claim 1 is characterized in that, will preset before excitation requirement is compiled into machine code described, and described method also comprises:
Read the source file that comprises excitation requirement that adopts preset instruction set to describe.
5. the method that is used for the FPGA checking according to claim 1, it is characterized in that, whether the described module to be detected of described output result verification according to described module to be detected correctly is: judge whether the output result of described module to be detected and expected results satisfy the preset function relation, if the output result of described module to be detected and expection knot satisfy the preset function relation, then described module to be detected is correct.
6. a device that is used for the FPGA checking is characterized in that, comprising:
Compiler is used for default excitation requirement is compiled into machine code, and described default excitation requirement is to use preset instruction set to describe, and described machine code can be discerned by processor;
Processor is used to carry out described machine code, produces excited data;
Writing unit is used for described excited data is imported module to be detected;
Whether authentication unit is used for according to the described module to be detected of the output result verification of described module to be detected correct.
7. the device that is used for the FPGA checking according to claim 6 is characterized in that described preset instruction set comprises:
Read instruction: be used for according to first burst-length from the first assigned address reading of data;
Write command: be used for specific data being write the position that second assigned address begins according to second burst-length;
Read instruction continuously: be used for since the 3rd assigned address, get an address every default regular length, and from this address reading of data successively;
Continuous write command: be used for incremental data with first designated length and write and increase progressively the address;
Check instruction: be used for checking the 4th assigned address with specific data;
Continuous review instruction: be used for the address that increases progressively with incremental data continuous review second designated length of second designated length.
8. the device that is used for the FPGA checking according to claim 6 is characterized in that, the device of the described FPGA of being used for checking also comprises:
Protocol conversion module is used for converting described excited data to meet module interface consensus standard to be detected read-write affairs.
9. the device that is used for the FPGA checking according to claim 6 is characterized in that, the device of the described FPGA of being used for checking also comprises:
Reading unit is used to read the source file that comprises excitation requirement that adopts preset instruction set to describe.
10. the device that is used for the FPGA checking according to claim 6, it is characterized in that, whether described authentication unit according to the described module to be detected of the output result verification of described module to be detected correctly is: described authentication unit judges whether the output result of described module to be detected and expected results satisfy the preset function relation, if the output result of described module to be detected and expection knot satisfy the preset function relation, then described module to be detected is correct.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101092882A CN102201022A (en) | 2011-04-22 | 2011-04-22 | Method and device for checking field programmable gate array (FPGA) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101092882A CN102201022A (en) | 2011-04-22 | 2011-04-22 | Method and device for checking field programmable gate array (FPGA) |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102201022A true CN102201022A (en) | 2011-09-28 |
Family
ID=44661696
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011101092882A Pending CN102201022A (en) | 2011-04-22 | 2011-04-22 | Method and device for checking field programmable gate array (FPGA) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102201022A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102521444A (en) * | 2011-12-08 | 2012-06-27 | 青岛海信信芯科技有限公司 | Cooperative simulation/verification method and device for software and hardware |
| CN105447251A (en) * | 2015-12-01 | 2016-03-30 | 浪潮(北京)电子信息产业有限公司 | Transaction type excitation based verification method |
| CN106991213A (en) * | 2017-03-09 | 2017-07-28 | 记忆科技(深圳)有限公司 | A kind of method for the interaction mechanism for realizing SoC checkings |
| CN109101355A (en) * | 2018-06-26 | 2018-12-28 | 天津飞腾信息技术有限公司 | A kind of processor debugging method for extracting wrong presence feature test and excitation |
| CN110223618A (en) * | 2019-06-06 | 2019-09-10 | 深圳市福瑞达显示技术有限公司 | A kind of display based on fan screen |
| CN110232883A (en) * | 2019-06-06 | 2019-09-13 | 深圳市福瑞达显示技术有限公司 | A kind of fan screen display system of optical signal data transmission |
| CN111967209A (en) * | 2020-08-21 | 2020-11-20 | 广芯微电子（广州）股份有限公司 | SOC simulation verification method and device and storage medium |
| CN112906328A (en) * | 2021-02-05 | 2021-06-04 | 博流智能科技（南京）有限公司 | FPGA prototype verification system generation method and system and FPGA prototype verification method and system |
| CN117056151A (en) * | 2023-10-11 | 2023-11-14 | 深圳鲲云信息科技有限公司 | Method and computing device for chip verification |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030204388A1 (en) * | 2002-04-25 | 2003-10-30 | Lsi Logic Corporation | Automated random verification of complex and structurally-variable systems |
| CN1725188A (en) * | 2004-07-22 | 2006-01-25 | 华为技术有限公司 | Logic verification system and method |
| CN101042424A (en) * | 2007-04-26 | 2007-09-26 | 北京南山之桥信息技术有限公司 | Method and apparatus for detecting application-specific integrated circuits |
| CN101183406A (en) * | 2007-12-25 | 2008-05-21 | 盛科网络（苏州）有限公司 | Method for establishing network chip module level function checking testing platform |
| CN101504690A (en) * | 2009-03-26 | 2009-08-12 | 北京航空航天大学 | Real-time simulation validation system and method for communication system integrated circuit design |
| CN101694677A (en) * | 2009-10-19 | 2010-04-14 | 上海华为技术有限公司 | Logic verification method, device and system |
-
2011
- 2011-04-22 CN CN2011101092882A patent/CN102201022A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030204388A1 (en) * | 2002-04-25 | 2003-10-30 | Lsi Logic Corporation | Automated random verification of complex and structurally-variable systems |
| CN1725188A (en) * | 2004-07-22 | 2006-01-25 | 华为技术有限公司 | Logic verification system and method |
| CN101042424A (en) * | 2007-04-26 | 2007-09-26 | 北京南山之桥信息技术有限公司 | Method and apparatus for detecting application-specific integrated circuits |
| CN101183406A (en) * | 2007-12-25 | 2008-05-21 | 盛科网络（苏州）有限公司 | Method for establishing network chip module level function checking testing platform |
| CN101504690A (en) * | 2009-03-26 | 2009-08-12 | 北京航空航天大学 | Real-time simulation validation system and method for communication system integrated circuit design |
| CN101694677A (en) * | 2009-10-19 | 2010-04-14 | 上海华为技术有限公司 | Logic verification method, device and system |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102521444A (en) * | 2011-12-08 | 2012-06-27 | 青岛海信信芯科技有限公司 | Cooperative simulation/verification method and device for software and hardware |
| CN105447251A (en) * | 2015-12-01 | 2016-03-30 | 浪潮(北京)电子信息产业有限公司 | Transaction type excitation based verification method |
| CN105447251B (en) * | 2015-12-01 | 2018-12-07 | 浪潮(北京)电子信息产业有限公司 | A kind of verification method based on transaction types excitation |
| CN106991213A (en) * | 2017-03-09 | 2017-07-28 | 记忆科技(深圳)有限公司 | A kind of method for the interaction mechanism for realizing SoC checkings |
| CN109101355A (en) * | 2018-06-26 | 2018-12-28 | 天津飞腾信息技术有限公司 | A kind of processor debugging method for extracting wrong presence feature test and excitation |
| CN110223618A (en) * | 2019-06-06 | 2019-09-10 | 深圳市福瑞达显示技术有限公司 | A kind of display based on fan screen |
| CN110232883A (en) * | 2019-06-06 | 2019-09-13 | 深圳市福瑞达显示技术有限公司 | A kind of fan screen display system of optical signal data transmission |
| CN111967209A (en) * | 2020-08-21 | 2020-11-20 | 广芯微电子（广州）股份有限公司 | SOC simulation verification method and device and storage medium |
| CN112906328A (en) * | 2021-02-05 | 2021-06-04 | 博流智能科技（南京）有限公司 | FPGA prototype verification system generation method and system and FPGA prototype verification method and system |
| CN112906328B (en) * | 2021-02-05 | 2024-03-08 | 博流智能科技（南京）有限公司 | FPGA prototype verification system generation method and system, and FPGA prototype verification method and system |
| CN117056151A (en) * | 2023-10-11 | 2023-11-14 | 深圳鲲云信息科技有限公司 | Method and computing device for chip verification |
| CN117056151B (en) * | 2023-10-11 | 2024-01-19 | 深圳鲲云信息科技有限公司 | Method and computing device for chip verification |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102201022A (en) | Method and device for checking field programmable gate array (FPGA) | |
| US6536031B2 (en) | Method for generating behavior model description of circuit and apparatus for logic verification | |
| CN102623069B (en) | Random excitation flash model verification method | |
| CN105205249A (en) | SOC (System on Chip) debugging validation system and software/hardware collaboration method thereof | |
| US11514225B2 (en) | Verification platform for system on chip and verification method thereof | |
| JP4853312B2 (en) | Behavioral synthesis apparatus, method, and program having test bench generation function | |
| US11520968B2 (en) | Verification platform for system on chip and verification method thereof | |
| CN106462431A (en) | Extracting system architecture in high level synthesis | |
| JP2009230451A (en) | Equivalence verifying method, equivalence verification program and method for generating equivalence verification program | |
| EP2706459A1 (en) | Apparatus and method for validating a compiler for a reconfigurable processor | |
| CN103207771A (en) | IP (Intelligent property) core of PLC (programmable logic controller) program performer | |
| CN102147831A (en) | Logic verification method and device | |
| CN102789418B (en) | Functional processor realistic model generating apparatus, method and function verification method | |
| CN109683962A (en) | A kind of method and device of instruction set simulator pipeline modeling | |
| Gao et al. | Software and hardware co-verification technology based on virtual prototyping of RF SOC | |
| CN116341428A (en) | Method for constructing reference model, chip verification method and system | |
| CN113760751B (en) | Method for generating test case, electronic device and storage medium | |
| US20130054218A1 (en) | Method and Software Tool for Automatically Testing a Circuit Design | |
| US20090319986A1 (en) | Data processing apparatus, method therefor, and computer program | |
| CN113868046A (en) | Function verification method and system of PAD control unit and related components | |
| CN107330177B (en) | Clock tree fan-out default repairing method based on Tcl/Tk script | |
| CN111858218A (en) | FPGA AMBA bus interface debugging method and device and FPGA | |
| Bombieri et al. | Correct-by-construction generation of device drivers based on RTL testbenches | |
| CN114169287B (en) | Method for generating connection schematic diagram of verification environment, electronic equipment and storage medium | |
| CN116861829B (en) | Method for locating errors in logic system design and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20110928 |