CN117056151B - Method and computing device for chip verification - Google Patents
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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Abstract
The invention provides a method and computing equipment for chip verification. The method for chip verification comprises the following steps: sampling the port side bus of the master device by using a first embedded bus verification module, and sampling the port side bus of the slave device by using a second embedded bus verification module; and modeling a bus mapping relationship between the master device port and the slave device port according to bus protocol formats of the master device port and the slave device port and address mapping complexity between the master device port and the slave device port, so that the second embedded bus verification module outputs a second bus transaction according to the modeled bus mapping relationship. According to the technical scheme, the bus connection path can be automatically verified, and verification efficiency is higher.
Description
Technical Field
The invention relates to the technical field of chip verification, in particular to a method and computing equipment for chip verification.
Background
With the development of emerging technologies such as 5G, the Internet of things and artificial intelligence, the application scenes of the chip are more and more diversified, and the requirements on the performance, the reliability, the safety and the like of the chip are higher and higher. As chip sizes become larger and integration becomes higher, integrated systems on chip (system on chip SOC) have been widely used for chip design. Chip verification is an important element in the chip design and manufacturing process, and the demand for chip verification is also increasing.
Today, with continuous progress in chip manufacturing technology, requirements on more specialized and comprehensive skills and knowledge are put forward for chip verification, so as to meet the verification requirements on chips in different application scenes. Chip verification means verification of functions, performance, reliability and the like of a chip to ensure that the chip meets design requirements and can work normally. Authentication generally includes aspects of functional authentication, performance authentication, reliability authentication, security authentication, and the like. Functional verification is to verify whether each functional module of the chip meets design requirements, wherein chip bus verification is an essential ring in the chip design and manufacturing process, and plays an important role in ensuring the performance and stability of the chip.
Chip bus verification refers to verifying buses inside chips or among chips to ensure that functions and performances of the buses meet design requirements. The bus is a channel for data and control information transmission inside or between chips, and has an important influence on the performance and stability of the chips.
With the continuous development of chip technology and the continuous expansion of application scenes, the demand for chip bus verification is also increased, and meanwhile, the continuous emergence of new verification technology and tools is also pushing the development of the chip bus verification industry. At present, most of bus path verification adopts a method for verifying data correctness: writing data into different addresses, reading the data, and comparing the correctness of the read-write data; and then indirectly verifying the correctness of the connection relation. The waveform inspection is required to be performed manually to confirm the correctness of the connection relationship. Not only is double verification required, but also the manual waveform detection operation requires more time and is difficult to cover over the whole area.
Therefore, a technical scheme is needed, whether the bus access path is correct or not can be automatically checked, verification efficiency is higher, flexibility is better, and coverage is more comprehensive.
Disclosure of Invention
The invention aims to provide a method and computing equipment for chip verification, and verification efficiency is higher.
According to an aspect of the present invention, there is provided a method for chip authentication, the chip including a master device, a slave device, the master device and the slave device communicating through at least one level of bus, the method comprising:
determining a master port, a slave port associated with the master, and bus protocol formats of the master port and the slave port;
sampling the port side bus of the master device by using a first embedded bus verification module, and sampling the port side bus of the slave device by using a second embedded bus verification module;
and constructing a mapping model for the bus mapping relation between the master device port and the slave device port according to the bus protocol format of the master device port and the slave device port and the address mapping complexity between the master device port and the slave device port, so that the second embedded bus verification module outputs a second bus transaction according to the modeled bus mapping relation.
According to some embodiments, building a mapping model from bus protocol formats of the master port and the slave port includes:
if the master device port and the slave device port have the same bus protocol format, a mapping model is constructed between the second embedded bus verification module and the first embedded bus verification module by using protocol key information mapping;
if the master device port and the slave device port belong to different bus protocol types, the second embedded bus verification module performs transaction conversion by using address mapping, thereby constructing a mapping model, including:
judging the address mapping complexity between the master device port and the slave device port;
if the address mapping is complex address mapping, bus interconnection mapping is performed by using components outside the first embedded bus verification module and the second embedded bus verification module, and sampling interfaces of the first embedded bus verification module and the second embedded bus verification module are taken over, so that a mapping model is constructed.
According to some embodiments, determining the complexity of the address mapping between the master port and the slave port comprises:
If the address mapping involves only one-way address truncations or shifts and the mapped address is unique, the address mapping pertains to a simple address mapping;
otherwise the address map is a complex address map.
According to some embodiments, the method further comprises:
if the address mapping is simple, mapping modeling is implemented using functions in the first embedded bus validation module and the second embedded bus validation module, or mapping modeling is implemented in the same manner as complex address mapping.
According to some embodiments, using the first embedded bus validation module to perform bus interconnect mapping with components other than the second embedded bus validation module includes:
and modifying the connection of the interface component, connecting the register transmission level address signal with the first embedded bus verification module and the sampling interface of the first embedded bus verification module, and realizing address mapping modeling in a bit shifting, bit cutting and/or normal digit supplementing mode.
According to some embodiments, using the first embedded bus validation module to perform bus interconnect mapping with components other than the second embedded bus validation module includes:
Using a callback function, and after sampling is completed, carrying out corresponding mapping and rewriting on data before comparison;
in address remapping, context containers or callback function processing are used.
According to some embodiments, using the first embedded bus validation module to perform bus interconnect mapping with components other than the second embedded bus validation module includes:
for the situation of a plurality of slave ports in the same storage space, one slave port is used as a master port, and data is synchronized in an environment container in a mode of copying the data to other slave ports; and/or
For the case of multiple slave device ports in the same storage space, instantiating one storage space instance in an environment container, and pointing the instantiation handles of the multiple slave device ports to the storage space instance.
According to another aspect of the present invention, there is provided a method for chip authentication, the chip including a master device, a slave device, the master device and the slave device communicating via at least one level of bus, the method being applied to a mapping model modeled using the method of any one of the preceding claims, the method comprising:
initiating a first operation to the main equipment according to the test case;
Sampling a port side bus of the main equipment by using a first embedded bus verification module to obtain a first bus transaction;
sampling a slave device port side bus by using a second embedded bus verification module, and outputting a second bus transaction according to the mapping model;
and automatically verifying the correctness of the bus connection relation according to the comparison result of the first bus transaction and the second bus transaction.
According to some embodiments, the plurality of second embedded bus verification modules respectively sample the plurality of slave device port side buses, and automatically verify the correctness of the bus connection relationship according to the comparison results of the first bus transaction and the plurality of second bus transactions under the condition that the plurality of second bus transactions are respectively output according to the mapping model.
According to another aspect of the present invention, there is provided a computing device comprising:
a processor; and
a memory storing a computer program which, when executed by the processor, causes the processor to perform the method of any one of the preceding claims.
According to another aspect of the invention there is provided a non-transitory computer readable storage medium having stored thereon computer readable instructions which, when executed by a processor, cause the processor to perform the method of any of the above.
According to the embodiment of the invention, when chip verification is carried out, a master device port, a slave device port associated with the master device and bus protocol formats of the master device port and the slave device port are determined, a first embedded bus verification module is utilized to sample a first bus transaction of a bus at the side of the master device port, and a second embedded bus verification module is utilized to model a bus mapping relation according to the bus protocol formats of the master device port and the slave device port and address mapping complexity between the master device port and the slave device port, so that a second embedded bus verification module is utilized to sample the bus at the side of the slave device port and output a second bus transaction according to the modeled bus mapping relation, and a mapping model is constructed. Through realizing the mapping modeling of the bus connection relation, whether the bus access path is correct or not can be automatically checked in all use cases of the SOC, the correctness of the bus connection relation is automatically and directly verified, the verification efficiency is higher, and the coverage is more comprehensive. According to the embodiment of the invention, the bus transaction is converted, a mapping model is built for the converted bus transaction, automatic comparison is carried out in the mapping model, and the correctness of the bus channel is verified. By applying the embedded verification module, the related functions and the components, the high-efficiency verification bus passage is realized, and compared with the prior scheme, the method has more comprehensive coverage and better flexibility.
According to the embodiment, the embedded bus verification module is used for simplifying mapping modeling, and meanwhile, the customized mapping relation is realized through external expansion, so that the environment is built simply, and the flexibility is better. In addition, the extension can be performed for the customized portion, and chip-specific can be adapted.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the description of the embodiments will be briefly described below.
Fig. 1 shows a flow chart of a method for chip verification according to an example embodiment.
FIG. 2A illustrates a method sample mode flow diagram for chip verification according to an example embodiment.
Fig. 2B shows a method sampling pattern diagram for chip verification according to an example embodiment.
FIG. 3 illustrates a schematic diagram of a manner in which modeling is implemented using complex address mapping in a method for chip verification according to an example embodiment.
FIG. 4 illustrates a block diagram of a computing device in accordance with an exemplary embodiment.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
The block diagrams depicted in the figures are merely functional entities and do not necessarily correspond to physically separate entities. That is, the functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
The flow diagrams depicted in the figures are exemplary only, and do not necessarily include all of the elements and operations/steps, nor must they be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one element from another element. Accordingly, a first component discussed below could be termed a second component without departing from the teachings of the present inventive concept. As used herein, the term "and/or" includes any one of the associated listed items and all combinations of one or more.
The user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, presented data, etc.) related to the present invention are information and data authorized by the user or fully authorized by each party, and the collection, use and processing of related data is required to comply with the relevant laws and regulations and standards of the relevant country and region, and is provided with corresponding operation entries for the user to select authorization or rejection.
Those skilled in the art will appreciate that the drawings are schematic representations of example embodiments and that the modules or flows in the drawings are not necessarily required to practice the invention and therefore should not be taken to limit the scope of the invention.
With the continuous development of chip technology and the continuous expansion of application scenes, more professional and comprehensive skills and knowledge requirements are provided for chip verification so as to meet the verification requirements of chips in different application scenes.
With the increase of chip scale, on-chip bus interconnection is more and more complex, and verification work on bus interconnection is both key and difficult. Chip bus verification refers to verifying buses inside chips or among chips to ensure that functions and performances of the buses meet design requirements. The bus is a channel for data and control information transmission inside or between chips, and has an important influence on the performance and stability of the chips.
With the continuous emergence of new verification technologies and tools, the development of the chip bus verification industry is also gradually proceeding. At present, most of bus path verification adopts a method for verifying data correctness: writing data into different addresses, reading the data, and comparing the correctness of the read-write data; and then indirectly verifying the correctness of the connection relation. This requires a manual waveform inspection to confirm the correctness of the connection relationship. Not only is double verification required, but also the manual waveform detection operation requires more time and is difficult to cover over the whole area.
To automatically verify the path relationships, the bus needs to be modeled. The common bus protocols, such as AMBA bus, are complex in function and often have multiple levels of bus interconnect, such as AXI to AHB, AHB to APB. For bus validation, the bus assembly may be redeveloped. Taking the UVM methodology as an example, including defining an interface component from a bus interface; constructing drivers and drivers according to the bus timing and considering all possible timing situations; constructing an activated transaction class according to the required control; constructing sequences and sequencers according to operations to be transmitted; the above components are packaged into one agent, and the required environment configuration is written. The bus VIP can also be used, and the bus VIP of each manufacturer is designed according to the bus protocol, so that the bus access function and the monitoring on the protocol can be realized, and a certain expansion interface is reserved. However, modeling the bus can be complex, time consuming and labor intensive to re-build the environment assembly, and can be easily missed. The degree of scalability and customization is limited again using the vendor-supplied bus VIP.
To this end, the invention proposes a method of bus validation. Through the use of the embedded verification module, bus transaction conversion is carried out by matching with corresponding functions and components, mapping modeling is carried out on the converted bus transaction, and in the mapping model, automatic comparison is carried out on the converted bus transaction. Compared with the existing bus verification method, the method is quicker and more efficient, secondary manual verification is not needed, and the mapping model is high in automatic comparison flexibility and more reliable in accuracy judgment.
Before describing embodiments of the present invention, some terms or concepts related to the embodiments of the present invention are explained.
Handshaking: a "handshake protocol" refers to a high-speed and reliable addressing and data transfer between a master and a slave of a control bus in compliance with various agreements. The data transmission reliability is ensured mainly by controlling the start and end of data transmission in each bus cycle to realize coordination and cooperation between master/slave devices.
AMBA (Advanced Microcontroller Bus Architecture): a published, open, scalable microcontroller bus protocol developed by ARM corporation. It provides a standard bus interface for connecting various components inside the microcontroller, such as processors, peripherals, memory, etc. The AMBA protocol defines the physical interface and protocol of the bus, including bus timing, bus width, bus addressing scheme, bus control signals, etc. It also defines the communication protocols between the different components on the bus, including bus requests, bus responses, bus arbitration, bus protection, etc.
AHB (Advanced High-performance Bus): a high performance bus interface, which is one of AMBA protocols. The bus is a full duplex bus, supports a plurality of slave devices, and can realize high-speed and low-delay data transmission.
AXI (Advanced eXtensible Interface): a bus protocol, which is the most important part of the AMBA (Advanced Microcontroller Bus Architecture) 3.0 protocol proposed by the ARM company, is an on-chip bus for high performance, high bandwidth and low latency.
Exemplary embodiments of the present invention are described below with reference to the accompanying drawings.
Fig. 1 shows a flow chart of a method for chip verification according to an example embodiment.
Referring to fig. 1, the illustrated method is used for chip authentication modeling, the chip may include a master port, a slave device, and communication between the master device and the slave device is performed through at least one level of bus.
At S101, a master port, a slave port associated with the master, and bus protocol formats of the master port and the slave port are determined.
According to some embodiments, connection relation analysis is performed on each bus path in the chip to be verified, which is a master port (master), which is a slave port (slave), and a bus protocol format corresponding to each port are confirmed.
According to some embodiments, all master ports are found according to the chip bus frame pattern to be verified, and for each master port, all the most remote slave ports accessible to the master port are found. For each found slave port, the slave port and the master port form a bus access path, and the slave port and the master port are regarded as a group. Bus validation is to validate whether each set of the slave port and the master port in the chip issues and accepts bus transactions the same.
At S103, the master port side bus is sampled with the first embedded bus validation module and the slave port side bus is sampled with the second embedded bus validation module.
According to some embodiments, the bus is monitored in real time using an embedded bus validation module (e.g., VIP). Taking the bus protocol in axi format as an example, when valid data appears at the monitored bus port, i.e. a vld+ready handshake appears, the monitored port side bus is considered to appear valid data. At the moment, data information such as addr, data and the like of handshake information is recorded; the data information recorded according to the bus protocol format is also different. For example, the sampled record information in the axi bus protocol format includes a handshake of a write-once address channel, a handshake of n write-data channels corresponding to the handshake of a return channel, and a handshake of a return channel, so as to form a primary bus sampled information, and the data information recorded in the primary sampling is stored as a bus transaction.
According to some embodiments, the sampling position of the bus by the first embedded bus verification module is the interface bus of the main device port, and the collected data information may form the first bus transaction.
According to some embodiments, the second embedded bus verification module performs a sampling operation on the slave device port side bus, and the collected data information may form a second bus transaction.
At S105, a bus mapping relationship between the master device port and the slave device port is modeled according to a bus protocol format of the master device port and the slave device port and an address mapping complexity between the master device port and the slave device port, so that a second embedded bus verification module outputs a second bus transaction according to the modeled bus mapping relationship.
According to some embodiments, the slave port and the master port form a bus access path, and the slave port and the master port are considered as a "set". Checking whether the protocols of the slave port and the master port in the same group are in the same bus protocol format. For example, when the bus protocol formats of the slave port and the master port are axi, they are considered to belong to the same protocol; if the bus protocol format of the master port is axi and the bus protocol format of the slave port is apb, they are considered to belong to different protocols.
According to some embodiments, when the bus protocol formats of the slave port and the master port are different, address mapping is applied to map model bus transactions.
If the master port and the slave port have the same bus protocol format, a mapping model is constructed using a protocol critical information mapping between the second embedded bus validation module and the first embedded bus validation module at S107.
According to some embodiments, if the master port and the slave port have the same bus protocol format, the transactions sampled by the second embedded bus validation module and the first embedded bus validation module that contain the same critical information may be compared as a group, thereby constructing a mapping model.
According to some embodiments, the same protocol critical information includes, but is not limited to, address, ID, range, etc. The same key information is considered as a group, the master device port side samples a bus transaction containing key information access, the first bus transaction of the slave device port side is obtained through conversion, the slave device port side also needs to sample a second bus transaction containing access of the same key information, and the first bus transaction and the second bus transaction are compared.
According to some embodiments, the address, ID, range are all information in AMBA protocol, when the master device port and the slave device port use the same bus protocol to map the same key information, the second embedded authentication module can complete most of mapping, and the environment is simple. When the key protocol information is added, the second embedded verification module can identify more situations.
For example, a bus transaction is a 64-bit axi access, the id is 0, 2 32-bit axi operations are changed through the bus, and the ids of the two axi operations are also 0 without id mapping, so that the operations on both sides can be identified directly by id=0. If id cannot be used, only address can be used, address translation is required. The 64-bit access address may be 32' h20, but the two converted 32-bit operations, the addresses would be 32' h20, 32' h24, and the relationship between the two addresses and the original address needs to be identified for mapping.
According to some embodiments, modeling may be accomplished through a configuration environment for cases where the master and slave devices have the same bus protocol format.
For example, using the amba_systyem_agent component of svt (system verilog test platform), in its cfg file, configure master as axi of 64bit data, address line 32bit; the slave is configured to be 32bit axi, the address line is 32bit, the slave is configured to be 32' h1100, and the VIP can complete the association. If the master initiates an operation with an address of 32' h1100, it is checked whether there is an associated operation sampled on the slave side.
In S109, if the master device port and the slave device port belong to different bus protocol types, the second embedded bus verification module performs transaction conversion using address mapping, so as to construct a mapping model.
According to some embodiments, if the master port and the slave port interface are of different protocols, the first bus transaction is converted to the expected slave port side first bus transaction using address mapping, i.e. the same address is considered as 'set', the master port side samples bus transactions for access to one address, the slave port side also needs to sample a second bus task for access to the same address, and the first bus transaction and the second bus transaction are compared.
According to some embodiments, 'a group' refers to a corresponding group of the master port and the slave port, in which method the master port and the slave port, which by default have the same address, operate, should be mapped together.
In S111, the complexity of the address mapping is determined.
According to some embodiments, an address mapping complexity between the master port and the slave port is determined. When the address mapping is only one-way address bit cutting or shifting and the mapped address is unique, the address mapping is simple. If the addresses of the slave device ports after address conversion are the same, or one slave device port corresponds to a plurality of addresses, or the addresses of the slave device ports can be mapped dynamically, or the address alignment meanings of the slave device port end and the master device port end are different. For example, the slave ports are aligned by 32 bits, and the master ports are aligned by 8 bits, which is considered a complex address mapping.
In S113, if the address mapping is complex address mapping, bus interconnection mapping is performed by using components other than the first embedded bus verification module and the second embedded bus verification module, and sampling interfaces of the first embedded bus verification module and the second embedded bus verification module are taken over, so as to construct a mapping model.
According to some embodiments, for complex address mapping, components other than the first embedded bus verification module and the second embedded bus verification module, including an interface component, an environment container, or a callback function, are required to implement bus interconnection mapping modeling, and take over sampling interfaces of the first embedded bus verification module and the second embedded bus verification module, so that the first embedded bus verification module and the second embedded bus verification module also implement sampling output of the second bus transaction on the slave device port side according to a mapping relationship, so as to be consistent with the first bus transaction after sampling conversion on the master device port side.
According to some embodiments, the method for modeling the bus mapping relationship can be selected according to different situation requirements, wherein the environment container and the interface component are environment components, are relatively solidified processes, are relatively fixed relative to callback functions and the like, and can affect the whole environment through expansion and modification of the environment container and the interface component. The callback function is more flexible to apply, can be modified at any time, and can realize different functions on the same reserved interface. However, the callback function requires that a callback function interface is reserved in the environment container and can be used, so that the callback function has a certain difficulty in use. To sum up, if a relatively fixed flow is used, the transformation is usually performed using an environment container. If it is a potentially diverse flow, a callback function is typically used. The above modes can realize the function requirement, and the mode selection can be determined according to the actual scene requirement.
In S115, if the address mapping is a simple address mapping, mapping modeling is implemented using functions in the first embedded bus validation module and the second embedded bus validation module. Or mapping modeling is implemented in the same manner as complex address mapping.
According to some embodiments, for simple address relationships, a function in the first embedded bus validation module and the second embedded bus validation module is used. For example, two functions of get_dest_global_addr_from_addr () and translate_address () of the master device port are written, and mapping modeling of address relationships is implemented according to the bus line of the architecture scheme.
For example, addr () and translate_address () are both null functions, are interfaces that the first embedded bus validation module and the second embedded bus validation module have remained in the processing flow, and are executed in the fixed flow of the first embedded bus validation module and the second embedded bus validation module, similar to callback functions. For example, when using the extended transfer_address function, the content is added such that if addr=32 'h1000, addr=32' h1200 is modified. The slave port side samples a bus transaction with an address of 32'h1000 and when sent to the auditing component, the address is changed to 32' h1200. However, the method can uniformly process the addresses of all interfaces, and cannot distinguish different slave device port interfaces. So it is only suitable for simple address mapping.
According to some embodiments, for simple address relationships, the same manner as complex addresses may be adopted, and mapping modeling may be completed by using components other than the first embedded bus verification module and the second embedded bus verification module, so as to implement sampling output bus transactions according to the mapping relationships.
And repeating the steps to traverse the bus to access all the channels, and verifying the correctness of the connection relation of the whole channels of the chip.
And if the address mapping is simple address mapping, performing bus interconnection mapping by utilizing components outside the first embedded bus verification module and the second embedded bus verification module.
According to some embodiments, modeling is performed on the path connection relationship between each group of the master device ports and the slave device ports according to the method, and the steps are repeated to model each group of different master device ports and slave device ports until all paths are accessed through the traversing bus, so that the correctness of the multi-level bus connection relationship corresponding to all ports of the chip is verified.
FIG. 2A illustrates a method sample mode flow diagram for chip verification according to an example embodiment.
Fig. 2B shows a method sampling pattern diagram for chip verification according to an example embodiment.
Referring to fig. 2A, the chip includes a master device and a slave device, the master device and the slave device communicate with each other through at least one level of bus, and the method is applied to the mapping model modeled by the method.
At S201, a first operation is initiated to the master device according to the test case.
According to some embodiments, a bus transaction for testing is issued at a master port to be tested to the slave ports of the same group of tests.
At S203, the master port side bus is sampled using the first embedded bus validation module to obtain a first bus transaction.
According to some embodiments, at the port side of the master device, the first embedded bus validation module is used to sample the issued bus transaction to obtain a first bus transaction.
At S205, the slave port side bus is sampled using a second embedded bus validation module, and a second bus transaction is output according to the mapping model.
According to some embodiments, at the slave port side, a second embedded bus validation module is used to sample the bus transaction to be received, and the sampled bus transaction is converted according to the mapping method in the method to obtain a second bus transaction.
In S207, the correctness of the bus connection relationship is automatically verified according to the comparison result of the first bus transaction and the second bus transaction.
According to some embodiments, the mapping model is applied to automatically compare the first bus transaction with the second bus transaction, and automatically verify the correctness of the bus connection relationship.
According to some embodiments, the plurality of second embedded bus verification modules respectively sample the plurality of slave device port side buses, and apply the mapping model similarly under the condition that the plurality of second bus transactions are respectively output according to the mapping model, automatically compare the first bus transactions with the second bus transactions, and automatically verify the correctness of the bus connection relationship.
Referring to fig. 2A and 2B, in bus verification, not only the correctness of data but also the bus path connection relationship need to be verified according to an example embodiment.
According to some embodiments, verifying the correctness of the data of the bus, see fig. 2A and 2B, module a issues bus transaction write data to module B via the bus, and then reads the data from module B, verifying whether the written data and the read data are identical. If so, the bus data between modules A and B is correct. And repeating the steps to traverse the bus to access all the paths, and verifying the correctness of the whole data of the chip.
According to some embodiments, the bus path connection relationship is verified using the verification method of the present invention, determining a master port, a device port associated with the master, and bus protocol formats of the master port and the slave port. A first bus transaction of a port side bus of a host device is sampled using a first embedded bus validation module. And modeling a bus mapping relation by using the second embedded bus verification module according to the bus protocol format of the master device port and the slave device port and the address mapping complexity between the master device port and the slave device port, so as to sample a slave device port side bus by using the second embedded bus verification module and output a second bus transaction according to the modeled bus mapping relation, thereby constructing a mapping model. By using the mapping model, the correctness of the bus connection relation among all corresponding ports of the chip can be automatically and directly verified.
Referring to fig. 2A and 2B, the first embedded bus verification module is used to sample at the port side of the master device, so as to obtain a first bus transaction; and sampling the slave device port side by using a second embedded bus verification module to obtain a second bus transaction.
According to some embodiments, by associating the master port interface and the slave port interface of the bus such that data is sent out at the master port, the slave port side detects whether the data is sent out to the corresponding slave port. Or the slave port side receives the data and detects whether the master port side sends the data. This completes the automatic checking of the bus relationship. For example, the master port a issues an operation to the slave port B, and the result is issued to the slave port C, which can be discovered quickly because the mapping relationship is not satisfied. Or the master device port a sends an error operation to the slave device port B, and sends the error operation to the slave device port B and the slave device port C, so that the error operation can be discovered quickly because the mapping relation is not met.
FIG. 3 illustrates a schematic diagram of a manner in which modeling is implemented using complex address mapping in a method for chip verification according to an example embodiment.
If the address mapping involves only a single-direction address truncate or shift and the mapped address is unique, it is a simple address mapping. Otherwise, complex address mapping is performed.
According to some embodiments, the complexity of the address mapping is determined according to the chip architecture implementation, and the address mapping is a simple address mapping when the address mapping is only a single-direction address truncated or shifted and the mapped address is unique. And the other addresses are complex address mapping, for example, the addresses of a plurality of slave device ports after address conversion are the same, or one slave device port corresponds to a plurality of addresses, or the addresses of the slave device ports can be dynamically mapped, or the address alignment meanings of the slave device port end and the master device port end are different. Then it is considered a complex address mapping.
According to some embodiments, for complex address mapping, the connection of the interface component is modified, the register transmission level address signal is connected with the first embedded bus verification module and the sampling interface of the first embedded bus verification module, and address mapping modeling is realized by bit shifting, bit truncating and/or a supplementary normal digit mode of the connection.
According to some embodiments, the register transfer level address signal is connected to the first embedded bus verification module and the sampling interface of the first embedded bus verification module, and address mapping modeling is performed by means of truncating the signal on the interface component. For example, the register transfer stage outputs a 32bit address, only the lower 16 bits of which are connected to the first embedded bus validation module, through an interface component, and the higher 16 bits of which are output are connected to a control function, or a constant.
According to some example embodiments, the register transfer level address signal is coupled to the first embedded bus validation module and the sampling interface of the first embedded bus validation module, and address mapping modeling is performed by shifting the signal bit on the interface component.
According to some embodiments, the method of modifying connection completion address mapping modeling of an interface component may further comprise applying the interface component to perform additional address differentiation.
And (3) using a callback function, and after sampling is completed, carrying out corresponding mapping and rewriting on the data before comparison. According to some embodiments, for using callback functions, a callback function interface may be added and callback function content implemented before sampling bus transactions for the auditing component. For example, detect addr=32 'h1000 in the bus transaction, change addr to 32' h2000, and send to the auditing component. The variations here should be consistent with the bus behavior described in the architecture solution.
According to some embodiments, the processing for the case of ID compression and translation is similar to the processing of the same address signal, i.e. a part of the register transfer level ID signal is connected to the first and the second embedded bus verification modules via an interface component, and the other part of the value is given by the environment.
In address remapping, context containers or callback function processing are used.
According to some embodiments, for address remapping, context container or callback function processing is used. The signals of the register transmission stage can be sent to the environment container, and after conversion is carried out in the environment container according to the mapping relation, for example, the input is 32'h1000, the output is changed into 32' h2000, and then the signals are connected to the first embedded bus verification module and the second embedded bus verification module. The callback function can also be used for address modification, and the changing mode is consistent with the bus behavior described in the architecture scheme.
For the case of a plurality of slave ports in the same storage space, one slave port is used as a master port, and data is synchronized in a manner that the data is copied to other slave ports in an environment container. And/or instantiating a storage space instance in the environment container, directing instantiation handles of the plurality of slave device ports to the storage space instance.
According to some embodiments, for the case of multiple slave ports in the same storage space, that is, multiple addresses correspond to the same block of space, data synchronization needs to be performed, otherwise, a addresses are written in, B addresses are read out, the data are not uniform, and automatic mapping and comparison cannot be performed. The method includes, but is not limited to, synchronizing data by copying the data to other slave ports in the environment container using one of the slave ports as a master port; or instantiating a storage space instance in the environment container, and pointing the instantiation handles of a plurality of slave device ports to the storage space instance.
Two specific examples according to embodiments of the present invention are described below.
Example 1:
the port end of the main equipment is an AHB interface with 32bit data bit width and 18bit address bit width, and the addresses are aligned according to 8 bits; the slave port end is a 32bit data bit wide, 16bit address bit wide APB4 interface and accesses are aligned at 32 bits, address space 4KB, and addresses 18'h15000 and 18' h25000 both correspond to the slave port.
The bus enables 32bit aligned access to the slave port by shifting the address by 2 bits to the right. And configuring the address attribute of the second embedded bus verification module at the port side of the slave device to be 18'h15000-18'16000, 18'h 25000-18' h26000.
If the slave device port side samples bus transactions beyond the range, reporting an address mapping error; controlling address lines [17:2] of an interface component in a second embedded bus verification module at the port side of the slave device to be connected to a 16bit address [15:0] of the port side of the slave device, and enabling [1:0] of the interface component in a first embedded bus verification module to be connected to an address [1:0] at the port side of the master device; in the environment container, the data of the 'h15000 address field in the VIP is copied to the 18' h25000 address field in real time, and the synchronization of the data is kept.
Initiating a write operation with an address of 18' h15100 from the port end of the main device, wherein write data is a; the slave port side is expected to receive a write operation with an address of 16'h5440, the interface of the second bus verification module performs mapping modification on the write operation, the address is shifted through mapping to obtain a converted bus transaction address of 18' h15100, and the bus transaction address of the slave port side associated with the modification is consistent with the bus transaction address of the master port side.
Initiating a read operation with an address of 18'h25100 from the port end of the main equipment, wherein a bus transaction sampled by the first embedded bus verification module from the port side of the main equipment is an address of 18' h25100, and read data is a; the slave port side is expected to receive a 16' h9440 read operation, the read data being a; the bus transaction sampled by the second embedded bus validation module from the slave port side is address 18' h25100 and the read data is a.
The data and connection correctness are verified, so that the bus verification among the group of ports is completed.
Example 2:
the port end of the main equipment is an AXI4 interface with the data bit width of 128 bits and the address bit width of 32 bits; the slave device port end is an AHB interface with the width of 4 64bit data bits and the width of 24bit address bits. And the bus is decoded by the upper 8 bits of the address to the different slave ports, additional address discrimination is required using the interface component. And allocating 4 slave ports according to the address decoding of the architecture scheme, and respectively allocating the addresses of high 8 bits 0, 1, 2 and 3 to the 4 slave ports 0, 1, 2 and 3.
The different slave ports, namely VIP interface components [31:24] =0 of the slave port 0, VIP interface components [31:24] =1 of the slave port 1, and so on are distinguished by environment fixing the high order of the interface components of the 4 slave ports VIP.
The register transfer stage receives access to the 24bit address, and the first and second embedded bus verification modules sample bus transactions of the 32bit address.
Initiating an AXI write operation from the master port end with addresses 32' h1000_0000, 128 bits, expected to translate into 2 64bit AHB write operations at the slave port end with addresses 24' h000_0000 and 24' h 000_0008; and this operation is expected to occur at the slave port 1 if the second embedded bus validation module samples a corresponding operational bus transaction at the slave port 1 interface, and considers connection checking to be successful, otherwise reporting a check failure. FIG. 4 illustrates a block diagram of a computing device according to an example embodiment of the invention.
As shown in fig. 4, computing device 30 includes processor 12 and memory 14. Computing device 30 may also include a bus 22, a network interface 16, and an I/O interface 18. The processor 12, memory 14, network interface 16, and I/O interface 18 may communicate with each other via a bus 22.
The processor 12 may include one or more general purpose CPUs (Central Processing Unit, processors), microprocessors, or application specific integrated circuits, etc. for executing relevant program instructions. According to some embodiments, computing device 30 may also include a high performance display adapter (GPU) 20 that accelerates processor 12.
Memory 14 may include machine-system-readable media in the form of volatile memory, such as Random Access Memory (RAM), read Only Memory (ROM), and/or cache memory. Memory 14 is used to store one or more programs including instructions as well as data. The processor 12 may read instructions stored in the memory 14 to perform the methods according to embodiments of the invention described above.
Computing device 30 may also communicate with one or more networks through network interface 16. The network interface 16 may be a wireless network interface.
Bus 22 may be a bus including an address bus, a data bus, a control bus, etc. Bus 22 provides a path for exchanging information between the components.
It should be noted that, in the implementation, the computing device 30 may further include other components necessary to achieve normal operation. Furthermore, it will be understood by those skilled in the art that the above-described apparatus may include only the components necessary to implement the embodiments of the present description, and not all the components shown in the drawings.
The present invention also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of the above method. The computer readable storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, DVDs, CD-ROMs, micro-drives, and magneto-optical disks, ROM, RAM, EPROM, EEPROM, DRAM, VRAM, flash memory devices, magnetic or optical cards, nanosystems (including molecular memory ICs), network storage devices, cloud storage devices, or any type of media or device suitable for storing instructions and/or data.
Embodiments of the present invention also provide a computer program product comprising a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform part or all of the steps of any one of the methods described in the method embodiments above.
It will be clear to a person skilled in the art that the solution according to the invention can be implemented by means of software and/or hardware. "Unit" and "module" in this specification refer to software and/or hardware capable of performing a specific function, either alone or in combination with other components, where the hardware may be, for example, a field programmable gate array, an integrated circuit, or the like.
It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present invention is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present invention. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required for the present invention.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
In the several embodiments provided by the present invention, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, such as a division of units, merely a division of logic functions, and there may be additional divisions in actual implementation, such as multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some service interface, device or unit indirect coupling or communication connection, electrical or otherwise.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable memory. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in whole or in part in the form of a software product stored in a memory, comprising several instructions for causing a computer device (which may be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method of the various embodiments of the present invention.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
The exemplary embodiments of the present invention have been particularly shown and described above. It is to be understood that this invention is not limited to the precise arrangements, instrumentalities and instrumentalities described herein; on the contrary, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (9)
1. A method of constructing a mapping model for chip verification, the chip comprising a master device, a slave device, the master device and the slave device in communication over at least one level of bus, the method comprising:
determining a master port, a slave port associated with the master, and bus protocol formats of the master port and the slave port;
sampling the port side bus of the master device by using a first embedded bus verification module, and sampling the port side bus of the slave device by using a second embedded bus verification module;
constructing a mapping model for a bus mapping relationship between the master port and the slave port according to bus protocol formats of the master port and the slave port and address mapping complexity between the master port and the slave port, so that the second embedded bus verification module outputs a second bus transaction according to the modeled bus mapping relationship,
The complexity of the address mapping comprises simple address mapping and complex address mapping, if the address mapping only involves address bit cutting or shifting in a single direction and the mapped address is unique, the address mapping belongs to the simple address mapping, otherwise, the address mapping is complex address mapping.
2. The method of claim 1, wherein constructing a mapping model for the bus mapping relationship between the master port and the slave port based on the bus protocol format of the master port and the slave port and the address mapping complexity between the master port and the slave port comprises:
if the master device port and the slave device port have the same bus protocol format, a mapping model is constructed between the second embedded bus verification module and the first embedded bus verification module by using protocol key information mapping;
if the master device port and the slave device port belong to different bus protocol types, the second embedded bus verification module performs transaction conversion by using address mapping, thereby constructing a mapping model, including:
if the address mapping is complex address mapping, bus interconnection mapping is performed by using components outside the first embedded bus verification module and the second embedded bus verification module, and sampling interfaces of the first embedded bus verification module and the second embedded bus verification module are taken over, so that a mapping model is constructed.
3. The method according to claim 1, wherein the method further comprises:
if the address mapping is simple, mapping modeling is implemented using functions in the first embedded bus validation module and the second embedded bus validation module, or mapping modeling is implemented in the same manner as complex address mapping.
4. The method of claim 2, wherein bus interconnect mapping with components other than the first embedded bus validation module and the second embedded bus validation module comprises:
and modifying the connection of the interface component, connecting the register transmission level address signal with the first embedded bus verification module and the sampling interface of the first embedded bus verification module, and realizing address mapping modeling in a bit shifting, bit cutting and/or normal digit supplementing mode of a connection address.
5. The method of claim 2, wherein bus interconnect mapping with components other than the first embedded bus validation module and the second embedded bus validation module comprises:
using a callback function, and after sampling is completed, carrying out corresponding mapping and rewriting on data before comparison;
In address remapping, context containers or callback function processing are used.
6. The method of claim 2, wherein bus interconnect mapping with components other than the first embedded bus validation module and the second embedded bus validation module comprises:
for the situation of a plurality of slave ports in the same storage space, one slave port is used as a master port, and data is synchronized in an environment container in a mode of copying the data to other slave ports; and/or
For the case of multiple slave device ports in the same storage space, instantiating one storage space instance in an environment container, and pointing the instantiation handles of the multiple slave device ports to the storage space instance.
7. A method for chip authentication, the chip comprising a master device, a slave device, the master device and the slave device communicating via at least one level of bus, the method being applied to a mapping model modeled in the method according to any one of claims 1-6, the method comprising:
initiating a first operation to the main equipment according to the test case;
sampling a port side bus of the main equipment by using a first embedded bus verification module to obtain a first bus transaction;
Sampling a slave device port side bus by using a second embedded bus verification module, and outputting a second bus transaction according to the mapping model;
and automatically verifying the correctness of the bus connection relation according to the comparison result of the first bus transaction and the second bus transaction.
8. The method of claim 7, wherein the plurality of second embedded bus verification modules sample the plurality of slave port side buses respectively, and automatically verify the correctness of the bus connection relationship according to the comparison results of the first bus transaction and the plurality of second bus transactions when the plurality of second bus transactions are output respectively according to the mapping model.
9. A computing device, comprising:
a processor; and
a memory storing a computer program which, when executed by the processor, causes the processor to perform the method of any one of claims 1-8.
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