CN102053898A - Method for testing bus interface on PCIE (Peripheral Component Interface Express) slot of host and read-write test method thereof - Google Patents
Method for testing bus interface on PCIE (Peripheral Component Interface Express) slot of host and read-write test method thereof Download PDFInfo
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- CN102053898A CN102053898A CN2009102208179A CN200910220817A CN102053898A CN 102053898 A CN102053898 A CN 102053898A CN 2009102208179 A CN2009102208179 A CN 2009102208179A CN 200910220817 A CN200910220817 A CN 200910220817A CN 102053898 A CN102053898 A CN 102053898A
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Abstract
The invention discloses a method for testing a bus interface on a PCIE (Peripheral Component Interface Express) slot of a host, which is characterized in that a PCIE test tool is used for testing the bus interface on the PCIE slot of the host. The test method comprises the following steps of: setting the initiation of the PCIE test tool as a master equipment mode, and setting other equipment on a bus of the PCIE slot of the host as slave equipment; sequentially scanning the slave equipment on the bus of the PCIE slot of the host through the PCIE test tool; judging whether the slave equipment correctively responding to the visit of the PCIE test tool is present; if yes, ending the test; and if no slave equipment on the bus correctively responds to the visit of the PCIE test tool, reporting an error and quitting the test. The test method can enhance the accuracy, the stability and the reliability of the bus interface on the PCIE slot of the tested host remarkably.
Description
Technical field
The present invention relates to a kind of method of testing of bus interface, relate in particular to a kind of method of testing at bus interface on the host PC IE slot.
Background technology
Peripheral device assembly interconnect (Peripheral Component Interconnect is called for short PCI) is a kind of bus standard that connects computer main frame panel and interfacing equipment, is formulated by Intel Company and delivers.It can be connected with address bus, data bus, the most control bus pin of CPU (central processing unit) (Central Processing Unit is called for short CPU), but must be by the control chip tandem signal.The PCI standard code entity size of this bus (comprising live width), electricity characteristic, bus timing and agreement etc., advantages such as bus structure are simple, cost is low, simplicity of design that it has.
Fast peripheral device assembly interconnect (PCI Express is called for short PCIE) is a kind of up-to-date bus and interface standard, is the higher development of PCI, and it has continued to use existing P CI programming concept and communication standard, but builds based on serial communication system faster.The characteristics of PCIE maximum are its versatility, not only can allow it be used for being connected of south bridge and miscellaneous equipment, also can extend to the connection between chipset, even also can be used to connect graphic chips, like this, whole I/O (I/O) system reunifies, and will further simplify computer system, increases the portability and the modularization of computing machine.In addition, because PCIE has adopted at present popular in the industry point-to-point connected in series, shared parallel architecture compared with PCI and more early stage computer bus, its each equipment all has the special use of oneself to connect, do not need to whole bus request bandwidth, and can bring up to a very high frequency to data transmission rate, reach PCI the high bandwidth that can not provide.Can only realize one-way transmission with respect to existing P CI bus in the single time cycle, the advantage of PCIE is the transfer rate and the quality that can provide higher.
At present, bus interface type on the host PC IE slot (Slot) comprises: System Management Bus (System Management Bus, hereinafter to be referred as SMBus), IIC (Inter Integrated Circuit) bus and Intelligent Platform Management Bus (Intelligent Platform Management Bus is hereinafter to be referred as IPMB).When testing at these bus interface on the host PC IE slot, existing method of testing is for example by existing slave unit address (Slave Address) on the test procedure scanning SMBus bus, the method can only be carried out read operation, can not carry out write operation, therefore can not realize the test of SMBus interface truly.
Summary of the invention
In order to solve above-mentioned the problems of the prior art and defective, the objective of the invention is to propose a kind of method of testing at bus interface (Interface) on the host PC IE slot, this method of testing highly versatile, really realized robotization and intelligent test, and can significantly improve accuracy, stability and the reliability of test bus interface on the host PC IE slot.
Whether normal a kind of method of testing at bus interface on the host PC IE slot proposed by the invention comprise one in order to the method for bus interface on the Test Host PCIE slot, comprises following steps:
PCIE testing tool Initiation is set at main equipment (Master) pattern, and the miscellaneous equipment on the bus on the host PC IE slot is set at slave unit (Slave);
Scan slave unit on the bus on this host PC IE slot successively by the PCIE testing tool;
Judge whether that slave unit makes correct response to the visit of PCIE testing tool; And
If there is slave unit that correct response is made in the visit of PCIE testing tool, represent that then bus interface is normal, finish test subsequently; If without any slave unit correct response is made in the visit of PCIE testing tool on the bus, represent that then bus interface is undesired, report an error subsequently and withdraw from test.
Wherein, in a kind of method of testing at bus interface on the host PC IE slot that the invention described above proposed, described PCIE testing tool is the Himalia instrument based on MSP430 chip and PEX8632 chip; Bus on the described host PC IE slot is the SMBus/IIC/IPMB bus.
In a kind of method of testing at bus interface on the host PC IE slot proposed by the invention, described PCIE testing tool scans the slave unit on the bus on the host PC IE slot successively from address 0 to 127.
Method of testing of the present invention comprises that also this method of testing comprises following steps at the readwrite tests method of bus interface on the host PC IE slot:
Scan slave unit all in the tested main frame (Slave), so as to seeking idle slave unit address (Slave Address);
Give the PCIE testing tool with the slave unit address transfer of free time of finding, and the PCIE testing tool is set at slave unit (Slave) pattern;
Write data by the bus on the host PC IE slot from PCIE testing tool reading of data and to the PCIE testing tool; And
Whether the data read-write operation of judging the bus on the host PC IE slot is all correct, if, represent that then bus interface is normal, finish test subsequently; If not, represent that then bus interface is undesired, report an error subsequently and withdraw from test.
Wherein, in a kind of readwrite tests method at bus interface on the host PC IE slot that the invention described above went out, described PCIE testing tool is the Himalia instrument based on MSP430 chip and PEX8632 chip; Bus on the described host PC IE slot is the SMBus bus.
In addition, in a kind of readwrite tests method that the invention described above went out at bus interface on the host PC IE slot, be by an i/o controller center (I/O Controller Hub by the test application (Diag App) of tested main frame, ICH) SMBus controller scans slave units all in the tested main frame, and the bus on the described host PC IE slot is to carry out communication by SMBus controller and PCIE testing tool, so as to writing data from PCIE testing tool reading of data and to the PCIE testing tool.
In sum, method of testing at bus interface on the host PC IE slot provided by the present invention, owing to adopt based on the PCIE testing tool (Himalia instrument) of MSP430 chip and PEX8632 chip and realized full test at bus interface on the host PC IE slot with above-mentioned dual mode, therefore, highly versatile at the method for testing of bus interface on the host PC IE slot provided by the present invention, really realized robotization and intelligent test, and can significantly improve the accuracy of test bus interface on the host PC IE slot, stability and reliability.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Fig. 1 is the flow chart of steps at the method for testing of bus interface on the host PC IE slot of one embodiment of the invention;
Fig. 2 is the flow chart of steps at the readwrite tests method of bus interface on the host PC IE slot of another embodiment of the present invention;
Fig. 3 is the PCIE testing tool that adopted in the method for testing at bus interface on the host PC IE slot of the present invention and the syndeton block scheme of tested main frame; And
Fig. 4 is the block diagram of the PCIE testing tool that adopted in the method for testing at bus interface on the host PC IE slot of the present invention.
Wherein, Reference numeral
10 Himalia instruments
20 main frames
Embodiment
Relevant characteristics and implementation of the present invention cooperate diagram to be described in detail as follows do preferred embodiment now.
Please refer to Fig. 1, this figure is the flow chart of steps at the method for testing of bus interface on the host PC IE slot of one embodiment of the invention, as shown in the figure, a kind of method of testing provided by the present invention at bus interface on the host PC IE slot, be by the PCIE testing tool bus interface on the host PC IE slot to be tested, this method of testing comprises following steps:
PCIE testing tool Initiation is set at main equipment (Master) pattern, and the miscellaneous equipment on the bus on the host PC IE slot is set at slave unit (Slave) (step 101), wherein, described PCIE testing tool can be the Himalia instrument based on MSP430 chip and PEX8632 chip, and the bus on the described host PC IE slot can be the SMBus/IIC/IPMB bus;
Scan slave unit (step 102) on the bus on this host PC IE slot successively by the PCIE testing tool, wherein, described PCIE testing tool scans the slave unit on the bus on the host PC IE slot successively from address 0 to 127;
Judge whether that slave unit makes correct response (step 103) to the visit of PCIE testing tool; And
If there is slave unit that correct response is made in the visit of PCIE testing tool, represent that then bus interface is normal, finish test subsequently; If without any slave unit correct response is made in the visit of PCIE testing tool on the bus, represent that then bus interface is undesired, report an error subsequently and withdraw from test (step 104).
Method of testing of the present invention comprises that also the embodiment step of this method of testing comprises following steps as shown in Figure 2 at the readwrite tests method of bus interface on the host PC IE slot:
Scan slave unit all in the tested main frame (Slave), so as to seeking idle slave unit address (Slave Address) (step 201), wherein, can scan slave units all in the tested main frame by the test application (Diag App) of the tested main frame SMBus controller by an i/o controller center (ICH);
Give the PCIE testing tool with the slave unit address transfer of free time of finding, and the PCIE testing tool is set at slave unit (Slave) pattern (step 202), wherein, described PCIE testing tool can be the Himalia instrument based on MSP430 chip and PEX8632 chip;
Write data (step 203) by the bus on the host PC IE slot from PCIE testing tool reading of data and to the PCIE testing tool, wherein, bus on the described host PC IE slot can be the SMBus bus, and the bus on the described host PC IE slot can be carried out communication by SMBus controller and PCIE testing tool, so as to writing data from PCIE testing tool reading of data and to the PCIE testing tool; And
Whether the data read-write operation of judging the bus on the host PC IE slot all correct (step 204), if, represent that then bus interface is normal, finish test subsequently; If not, represent that then bus interface is undesired, report an error subsequently and withdraw from test (step 205).
Please refer to Fig. 3 and Fig. 4 now, Fig. 3 is the PCIE testing tool that adopted in the method for testing at bus interface on the host PC IE slot of the present invention and the syndeton block scheme of tested main frame, Fig. 4 is the block diagram of the PCIE testing tool that adopted in the method for testing at bus interface on the host PC IE slot of the present invention, as shown in Figures 3 and 4, the PCIE testing tool that is adopted in the method for testing of the present invention can be the Himalia instrument 10 based on MSP430 chip and PEX8632 chip, wherein, the MSP430 chip can be used as core micro controller unit (Core MCU), and the PEX8632 chip then can be used as PCIE switch (PCIE Switch).
Himalia instrument 10 links to each other with PCIE slot on the tested main frame 20, in order to detect the various signals of the PCIE slot on the main frame 20, comprises simultaneously the SMBus/IIC/IPMB bus described in the present invention is tested.
The test application of tested main frame 20 (Diag App) is by an i/o controller center (I/OController Hub, be called for short ICH, it is the South Bridge chip series title of Intel, South Bridge chip is the important component part of motherboard chipset, generally be positioned on the motherboard from CPU slot below far away, near the PCIE slot, responsible PCIE bus and the I/O equipment etc. of connecting) SMBus controller scans all slave units in the tested main frame 20, promptly, the scanning earlier of the test application of main frame 20 has the numbering of what slave units at present, again the numbering of free time is assigned to Himalia instrument 10, then can carry out the reading and writing data test, its testing process and details belong to prior art, do not repeat them here.
What also need here to specify a bit is exactly the means of communication of the test application and the core micro controller unit on the Himalia instrument 10 (that is: MSP430 chip) of main frame 20, test application is operated universal input and output (the General Purpose I/O of PCIE switch (that is: PEX8632 chip) by the PCIE configuration space of visit main frame 20, be called for short GPIO) buffer and utilize the GPIO buffer of PEX8632 chip to simulate serial interface devices interface (Serial Peripheral interface, be called for short SPI) agreement and then carry out communication with the core micro controller unit, that is, send test command and read corresponding test result to the core micro controller unit.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (9)
1. the method for testing at bus interface on the host PC IE slot is tested the bus interface on the host PC IE slot by a PCIE testing tool, it is characterized in that this method of testing comprises following steps:
This PCIE testing tool Initiation is set at the main equipment pattern, and the miscellaneous equipment on the bus on this host PC IE slot is set at slave unit;
Scan this slave unit on the bus on this host PC IE slot successively by this PCIE testing tool;
Judge whether that this slave unit makes correct response to the visit of this PCIE testing tool; And
If there is this slave unit that correct response is made in the visit of this PCIE testing tool, represent that then this bus interface is normal, finish this method of testing subsequently; If without any this slave unit correct response is made in the visit of this PCIE testing tool on this bus, represent that then this bus interface is undesired, report an error subsequently and withdraw from this method of testing.
2. method of testing according to claim 1 is characterized in that, this PCIE testing tool is the Himalia instrument based on MSP430 chip and PEX8632 chip.
3. method of testing according to claim 1 is characterized in that, the bus on this host PC IE slot is the SMBus/IIC/IPMB bus.
4. method of testing according to claim 1 is characterized in that, this PCIE testing tool scans this slave unit on the bus on this host PC IE slot successively from address 0 to 127.
5. the readwrite tests method at bus interface on the host PC IE slot is by a PCIE testing tool bus interface on the host PC IE slot to be carried out readwrite tests, it is characterized in that this readwrite tests method comprises following steps:
Scan slave units all in the tested main frame, so as to seeking idle slave unit address;
Give this PCIE testing tool with this slave unit address transfer of free time of finding, and this PCIE testing tool is set at the slave unit pattern;
Write data by the bus on this host PC IE slot from this PCIE testing tool reading of data and to this PCIE testing tool; And
Whether the data read-write operation of judging the bus on this host PC IE slot is all correct, if, represent that then this bus interface is normal, finish this readwrite tests subsequently; If not, represent that then this bus interface is undesired, report an error subsequently and withdraw from this readwrite tests.
6. readwrite tests method according to claim 5 is characterized in that, this PCIE testing tool is the Himalia instrument based on MSP430 chip and PEX8632 chip.
7. readwrite tests method according to claim 5 is characterized in that, the bus on this host PC IE slot is the SMBus bus.
8. readwrite tests method according to claim 7 is characterized in that, scans this all in tested main frame slave units by the test application of the tested main frame SMBus controller by an i/o controller center.
9. readwrite tests method according to claim 8, it is characterized in that, bus on this host PC IE slot is carried out communication by this SMBus controller and this PCIE testing tool, so as to writing data from this PCIE testing tool reading of data and to this PCIE testing tool.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2009102208179A CN102053898A (en) | 2009-11-06 | 2009-11-06 | Method for testing bus interface on PCIE (Peripheral Component Interface Express) slot of host and read-write test method thereof |
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| CN2009102208179A CN102053898A (en) | 2009-11-06 | 2009-11-06 | Method for testing bus interface on PCIE (Peripheral Component Interface Express) slot of host and read-write test method thereof |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102609344A (en) * | 2012-02-16 | 2012-07-25 | 杭州海康威视数字技术股份有限公司 | Method and device for detecting hot plug subboards of multi-subboard PCI-E (peripheral component interconnect express) system |
| CN102968362A (en) * | 2012-11-21 | 2013-03-13 | 浪潮电子信息产业股份有限公司 | Method for detecting integrity of PCIE (peripheral component interface express) equipment in system start-up process |
| CN103198001A (en) * | 2013-04-25 | 2013-07-10 | 加弘科技咨询(上海)有限公司 | Storage system capable of self-testing peripheral component interface express (PCIE) interface and test method |
| CN104778109A (en) * | 2015-04-28 | 2015-07-15 | 浪潮电子信息产业股份有限公司 | Program downloading system and method of PCIE/PCIX external plug-in card |
| CN107122277A (en) * | 2017-05-09 | 2017-09-01 | 郑州云海信息技术有限公司 | The wrong test system of PCIERAS notes and method based on PCIE protocol analyzers |
| CN108335722A (en) * | 2018-01-03 | 2018-07-27 | 郑州云海信息技术有限公司 | A kind of method of automatic test SSD interface rate |
| CN108595297A (en) * | 2018-05-09 | 2018-09-28 | 郑州云海信息技术有限公司 | A kind of detection method and device of UPI speed |
| CN112000533A (en) * | 2020-08-14 | 2020-11-27 | 北京浪潮数据技术有限公司 | PCIE equipment bus test method and test tool |
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2009
- 2009-11-06 CN CN2009102208179A patent/CN102053898A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102609344A (en) * | 2012-02-16 | 2012-07-25 | 杭州海康威视数字技术股份有限公司 | Method and device for detecting hot plug subboards of multi-subboard PCI-E (peripheral component interconnect express) system |
| CN102968362A (en) * | 2012-11-21 | 2013-03-13 | 浪潮电子信息产业股份有限公司 | Method for detecting integrity of PCIE (peripheral component interface express) equipment in system start-up process |
| CN103198001A (en) * | 2013-04-25 | 2013-07-10 | 加弘科技咨询(上海)有限公司 | Storage system capable of self-testing peripheral component interface express (PCIE) interface and test method |
| CN103198001B (en) * | 2013-04-25 | 2017-02-01 | 加弘科技咨询(上海)有限公司 | Storage system capable of self-testing peripheral component interface express (PCIE) interface and test method |
| CN104778109A (en) * | 2015-04-28 | 2015-07-15 | 浪潮电子信息产业股份有限公司 | Program downloading system and method of PCIE/PCIX external plug-in card |
| CN107122277A (en) * | 2017-05-09 | 2017-09-01 | 郑州云海信息技术有限公司 | The wrong test system of PCIERAS notes and method based on PCIE protocol analyzers |
| CN108335722A (en) * | 2018-01-03 | 2018-07-27 | 郑州云海信息技术有限公司 | A kind of method of automatic test SSD interface rate |
| CN108595297A (en) * | 2018-05-09 | 2018-09-28 | 郑州云海信息技术有限公司 | A kind of detection method and device of UPI speed |
| CN108595297B (en) * | 2018-05-09 | 2021-04-27 | 郑州云海信息技术有限公司 | UPI speed detection method and device |
| CN112000533A (en) * | 2020-08-14 | 2020-11-27 | 北京浪潮数据技术有限公司 | PCIE equipment bus test method and test tool |
| CN112000533B (en) * | 2020-08-14 | 2023-03-31 | 北京浪潮数据技术有限公司 | PCIE equipment bus test method and test tool |
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Application publication date: 20110511 |