KR101226389B1 - SYSTEM AND METHOD FOR CONTROLLING EXCLUSIVE ACCESS IN SoC - Google Patents

Abstract

The present invention relates to a method and system for access control in an on-chip system (SoC), and more particularly to a method and system for effectively arbitrating a plurality of masters in an on-chip bus system based on an open core protocol to prevent exclusive access failure. It is about.

The present invention includes a register file area for such an exclusive access in the interconnect to provide a method and system that can avoid failure when the master accesses the slave exclusively in the AMBA AXI protocol. That is, the master first checks the register file before performing exclusive access, checking whether another master is performing exclusive access, and if another master is already performing exclusive access, referring to the register file By not accessing the same memory area of the slave, it prevents the master from accessing exclusively.

AMBA 3.0, AXI, ARM, Bus System, SoC

Description

Proprietary access control method and system in system on chip {SYSTEM AND METHOD FOR CONTROLLING EXCLUSIVE ACCESS IN SoC}

1 is a block diagram of an AXI protocol structure bus system of the general AMBA 3.0 standard;

2 is a flowchart illustrating an exclusive access method according to a general AMBA 3.0 standard;

3 is a block diagram of an AXI protocol structure bus system of AMBA 3.0 according to an embodiment of the present invention;

4 is an operational flow diagram for a plurality of masters to perform an exclusive access according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and system for access control in a system on chip (SoC), and more particularly, to an on-chip bus system based on an open core protocol. It is directed to a method and system for effectively mediating the masters of an exclusive access to prevent failure.

Recently, the use of a system on chip that integrates a plurality of chips (Chips) with different functions on a single chip has become common. And in the design of system-on-chip, it is essential to reduce development time to meet rapidly changing market demands. To this end, the recycling of existing chip blocks, that is, IP Cores (Intellectual Property Core), is gradually expanding. The recycling of IP Cores not only shortens the time required for product development, but also improves the reliability of newly developed system on chips.

Meanwhile, in order to effectively design a system on a chip, the selection of a bus system for communication between a plurality of IP cores integrated on one chip is important. The most representative bus system in use today is the Advanced Microcontroller Bus Architecture (AMBA) bus from Advanced RISC Machine (ARM). AMBA bus 2.0 consists of the system bus Advanced High-Performance Bus (AHB) and the Advanced Peripheral Bus (APB) that connects the peripherals. AHB features include pipelined operations, multiple bus masters, burst transfers, and split transactions. However, when one master occupies a bus to access a slave through AHB, the other master cannot access the slave, so in a system with multiple masters at the same time, the bus latency ) Has the disadvantage of increasing.

To address these shortcomings and make efficient use of the bus structure, the AMBA 3.0 standard defines the AXI protocol as a system bus instead of the AHB defined in 2.0. The block configuration for a conventional AXI protocol structure is shown in FIG.

1 is a block diagram of an AXI protocol structure bus system of the general AMBA 3.0 standard.

Three masters 100, 101, 102 and four slaves 110, 111, 112, and 113 according to the AMBA 3.0 standard illustrated in FIG. 1 connect the plurality of masters and the plurality of slaves. A main interconnect (120), a first interface (130) connecting the masters (100, 101, 102) and the interconnect (120), the slaves (110, 111, 112, 113) and the The second interface 131 connects the interconnect 120. In FIG. 1, the interconnect 120 serves as an arbiter and a decoder of AMBA 2.0, and supports a multi-layer bus.

Here, each component shown in FIG. 1 is described in detail in the AMBA 3.0 standard, but will be briefly described for convenience of understanding.

First, the masters 100, 101, 102 are generally equipped with a central processing unit, a microcontroller, a microprocessor, and the like, and each of the masters 100, 101, 102 is connected to the slaves 110 through the interconnect 120. And outputs a request signal for accessing 111, 112, and 113. In addition, when a grant signal is received from the interconnect 120, the masters 100, 101, and 102 are determined to have bus ownership, and thus, the slaves 110, 111, 112, and 113. Information, namely, address information, control information, and the like, are transmitted to the interconnect 120. The master having the bus ownership performs a read or write operation with the selected slave.

The slaves 110, 111, 112, and 113 may be, for example, semiconductor devices, or devices that respond to requests from the masters. The slaves have a memory and a memory controller to control the memory.

Prior to the description of the interconnect 120, the arbiter and decoder described in detail in the AMBA 2.0 standard will be described first.

The Arbiter authorizes only one master to use the bus at a time, and assigns a fixed priority (bus) between the masters (100, 101, 102) and slaves (110, 111, 112, 113). Mediation of bus usage between the masters 100, 101, and 102 is performed using a fixed priority or round-robin method. The decoder decodes the address of the slave to be transmitted by the master.

The interconnect 120 performs the functions of an arbiter and a decoder as described above, and transmits address, data, and control information for mutual data transmission between a plurality of masters and slaves. .

That is, the interconnect 120 receives address information and control information (eg, write / read commands, bursts) from a bus master having bus ownership to access data from at least one of the slaves from the bus masters. It receives the driving information including the operation, data size, etc.) and selects one bus master through arbitration, and sends a data processing preparation request to the slave to process the data.

The access methods supported to the masters in the AXI protocol of the AMBA system having the system configuration as described above are three types of methods: normal access, exclusive access, and locked access. There is this.

Normal access and lockout access were also supported in AMBA 2.0, AHB, and the new approach in AMBA 3.0 is the proprietary approach.

Normal access is the basic operation used on existing AMBA 2.0 buses. When one master occupies a bus to access a slave, the other masters do not occupy the bus and the bus occupied by the master occupying the bus. It waits for release and then accesses the slave while occupying the bus sequentially. In this case, early termination can occur if the master occupies the bus for a long time. However, lock access does not allow early termination.

In lock access, when master 1 (100) requests slave 1 (110) for lock access, the bus will only have a connection between master 1 (100) and slave 1 (110) until the burst transmission ends. . In this case, the other masters cannot access the other slaves because they cannot occupy the bus and must wait until the access of the master 1 (100) is terminated. In this case, there is a disadvantage in that latency of other masters 101 and 102 is increased. So, to solve this problem, AMBA 3.0 is defined to support the above exclusive access.

The manner in which the master performs an exclusive access according to the standard of AMBA 3.0 is shown in FIG. 2.

FIG. 2 is a flowchart illustrating an exclusive access method according to a general AMBA 3.0 standard, which will be described with reference to FIG. 1.

First, in operation 200, the master 1 100 exclusively reads data of a specific memory address area of the slave 1 110. In step 202, the master 1 (100) performs the corresponding processing using the read data, and in step 204, the master 1 (100) writes the processed data in the same memory address area of the slave 1 (110). (Write)

In step 206, if the master reads successfully, the slave 1 110 proceeds to step 208 and transmits an exclusive access success signal (EXOKAY) to the master 1 (100). Otherwise, if the exclusive read has failed, the process proceeds to step 210 and the slave 1110 transmits an exclusive access failure (OK) signal to the master 1 (100).

The exclusive access failure as in step 210 of FIG. 2 is performed by another master (master 2 or master 3) while the master requesting the exclusive access, that is, master 1 (100) performs an exclusive access write / read operation. Occurs when 1 reads data from the same memory of the same slave performing an exclusive access.

That is, as described above, when a plurality of masters require exclusive access according to the general AMBA 3.0 standard, there is a problem in that failures occurring when masters access the same memory area of the same slave cannot be prevented.

The present invention provides a system and method for preventing proprietary access failures through arbitration between multiple masters and multiple slaves on a system bus.

The present invention provides a system and method for efficiently occupying a bus system of a plurality of masters in a system bus.

Method according to an embodiment of the present invention; In a method of controlling access to one slave by two or more masters from a System on Chip (SoC), when a master intends to access the slaves, interconnect registers are used. Checking a file (Resister File); Obtaining, by the master, driving information from the register file if the register file includes information indicating that another master is performing access to the slave; And acquiring information on the remaining area of the memory area of the slave except the memory accessed by the other master from the driving information, and accessing the remaining area by the master.
An apparatus according to an embodiment of the present invention is a system on chip (SoC) for controlling access to one slave (Slave) by two or more masters (Master), from one of the master to the slave When the access is made, Interconnect includes a register file that registers or updates driving information corresponding to the access.
According to another embodiment of the present invention; In a master controlling access to one slave by two or more masters from a System on Chip (SoC), when accessing the slave is performed, an interconnect register file ( A control unit for inspecting a Resister File, and if the register file includes information indicating that the other master is performing access to the slave according to the instruction of the control unit, the master reads from the register file. An access performer configured to obtain driving information, obtain information on the remaining areas of the slave memory area except the memory accessed by the other master from the driving information, and perform access to the remaining area by the master; do.

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Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the same components in the figures represent the same numerals wherever possible. Specific details are set forth below, which are provided to help a more general understanding of the present invention. In describing the present invention, when it is determined that description of related known functions or configurations may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

First, prior to the description of the present invention, the basic concept of the present invention will be described. The present invention includes a register file 350 area for such an exclusive access in interconnect 320 to provide a method and system that can avoid failure when the master accesses the slave exclusively in the AMBA AXI protocol. That is, before the master performs exclusive access, the register file 350 is checked first to check whether another master is performing exclusive access, and if another master is already performing exclusive access, the register file ( By not accessing the same memory area of the same slave with reference to 350, the master's exclusive access failure is prevented.

3 is a block diagram of an AXI protocol structure bus system of AMBA 3.0 according to an embodiment of the present invention.

In the embodiment of the present invention, for convenience of description, it will be assumed that there are two masters and two slaves. The master A 300 is currently performing exclusive access to the slave A 310, and the master B 301 has exclusive access. Assume that you have requested.

Referring to FIG. 3, in the AXI protocol structure bus system of AMBA 3.0 according to an embodiment of the present invention, two masters 300 and 301, two slaves 310 and 311, and the masters 300, 301 is largely composed of an interconnect 320 that connects. And interfaces 340 and 341 for connecting the masters 300 and 301 to the interconnect 320, and interfaces 342 and 343 for connecting the slaves 310 and 311 to the interconnect 320. do.

In the description of the configuration of FIG. 3, the same parts as in FIG. 1 will be omitted.

Reference numeral 330 denotes a port through which the master A 300 is connected to the interconnect 320 through the interface 340, and reference numeral 331 denotes a master B 301 connected to the interconnect 320 through the interface 341. The port to connect to. Reference numeral 332 denotes a port to which the slave A 310 is connected to the interconnect 320 through the interface 342, and reference numeral 333 denotes a port to which the slave B 310 is connected to the interconnect 320 through the interface 343. Indicates.

The interconnect 320 also has two buses for read / write operations between masters and slaves. As shown in FIG. 3, the bus provided in the interconnect 320 includes an address bus 360 and a data bus 370.

The address bus 360 decodes the addresses of the slaves 310 and 311 for the masters 300 and 301 to read / write data, so that the data bus 370 corresponds to the decoded address. The masters 300 and 301 transmit data to be read or written to a slave memory address. The address bus 360 and data bus 370 are provided in all bus systems such as SoCs.

In addition, the control signal 380 is a signal for checking the information of the register file 350 newly added in the present invention for the masters 300 and 301 to perform exclusive access to the slaves 310 and 311. to be.

The register file 350 stores predetermined information for preventing a collision between masters 300 and 301 to perform exclusive access according to an embodiment of the present invention. The contents of the register file 350 are shown in Table 1 below. Same as>

 Register  Allocated Bit  Explanation  Indicator Flag  1 Bit Flags for Exclusive Access
(Exclusive access occurs when Flag == 1)  Counter  4 Bit  Master access with exclusive access  Reserved bit  3 Bit  Reserved bits  Master ID  4 Bit  ID to identify the master  Master Port ID  4 Bit  ID to identify the master port  Slave Port ID  8 Bit  Port ID of the Slave, or Destination ID  Start Address  32 bit   Start address to access memory of slave  Data length  32 bit  Data length

In Table 1, an indicator flag is information indicating whether a master is performing exclusive access in the current bus system and is represented by 1 bit. If the indication flag is "1", the present flag is performing exclusive access. Indicates that a master exists.

Counter is a flag indicating the number of masters currently performing exclusive access, and if the number of masters currently performing exclusive access in the bus system is one, the counter is set to "1".

The reserved bit is a reserved bit for future use, the master ID is a bit indicating an ID for identifying a master in the interconnect 320, and the master port ID is a master. A bit indicating an ID for identifying a port, indicated by 4 bits. The slave port ID is a bit for representing the ID of a slave port, that is, a destination for a master to perform a read / write operation, and is represented by 8 bits. Start Address is a bit that indicates the start address of the memory of the slave for the master to perform read / write operation. It is represented as 32 bits. Data Length is the size of data for the master to perform read / write operation. A bit indicating a, which is represented by 32 bits. As such, the register file 350 according to the embodiment of the present invention includes a total of 88 bits including 3 bits of a reserved bit.

In Table 1, the indication flag, the counter, the master ID, and the master port ID are set by the master performing exclusive access, and the slave port ID, starting address, and data length are set by the slave receiving the exclusive access request. In Table 1, a counter, a master ID, a master port ID, a slave port ID, a starting address, and a data length are necessary information for the master to perform exclusive access, which will be collectively referred to as driving information.

4 is a flowchart illustrating an operation for a plurality of masters to perform an exclusive access according to an embodiment of the present invention.

4, the master A 300 is currently performing exclusive access to the slave A 310, and the master B 301 performs the exclusive access as in FIG. 3. do. If only master A 300 is currently performing exclusive access, master A 300 sets the indication flag, counter, master port ID, and master ID in register file 350 through control signal 380. The slave A 310, which the master A 300 requests for exclusive access, sets a slave port ID, a start address, and a data length in the register file 350 through the control signal 380.

If the master B 301 performs exclusive access in step 400, the process proceeds to step 402 and checks an indicator flag in the register file 350 through a control signal 380.

If the indication flag is "1" in step 404, the master B 301 proceeds to step 406 to read the drive information in the register file 350. Herein, the driving information means a counter, a master ID, a master port ID, a slave port ID, a start address, and a data length. In step 406, the master B 301 may determine which memory area of which slave the master A 300 is currently accessing based on the driving information, and thus, the master B 301 may determine the master A 300. ) Can perform exclusive access to other areas except the same memory area of the same slave that it is accessing. In operation 408, the master B 301 requests exclusive access to a slave to be exclusively accessed based on the driving information. In operation 410, the master B 301 sets driving information in the register file 350. Typically, the counter, which is the number of masters currently performing exclusive access among the driving information, is increased by "1".

In step 410 of FIG. 4, only the number of masters currently performing exclusive access (Counter) is described as being increased. In reality, information currently performing exclusive access is registered in the register file 350.

On the other hand, if the indication flag is not "1" in step 404, it means that there is no master currently performing exclusive access in the bus system, so the master B 301 immediately proceeds to step 408 to perform exclusive access to the slave to be exclusively accessed. request.

In step 412, the master B 301 performs a data read / write operation on the slave's memory, and in step 414, when the master B 301 receives the exclusive success signal EXOKAY from the slave to which the master B 301 exclusively accesses, the master B 301 proceeds to step 416. FIG. Proceed to reduce the number of masters currently performing exclusive access by "1". On the other hand, if the exclusive access success signal is not received from the slave in step 414, it means that the exclusive access has failed and the process proceeds to step 400 to start the exclusive access operation again.

In step 416, the master B 301 which reduces the number of masters performing exclusive access checks whether the number of masters currently performing exclusive access is "0". If it is "0", it means that there is no master currently performing exclusive access. In step 420, the indication flag in the register file 350 is set to "0".

As described above, by applying the present invention, the masters do not have access to the same memory of the same slave, thereby reducing failures when an exclusive access occurs. There is an advantage that the latency that masters cannot perform read / operation to slaves is reduced.

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Claims (12)

In a method for controlling access to one slave by two or more masters in a System on Chip (SoC), Checking a register file of an interconnect when a master intends to access the slave; Obtaining, by the master, driving information from the register file if the register file includes information indicating that another master is performing access to the slave; And  Obtaining information on the remaining area of the memory area of the slave except the memory accessed by the other master from the driving information, and performing access to the remaining area by the master. The access control method of claim 1, wherein the register file comprises an indication flag indicating whether a master performs access for each slave, a counter indicating a number of masters performing access to the slave, and a master identifier. The method of claim 2, The indication flag, the counter and the master identifier is set by the other master requesting access to the slave. delete The method of claim 1, The register file, A slave port identifier indicating an identifier of the slave to perform the read and write operations by the master, a memory start address of the slave to perform the read and write operations by the master, and data to perform the read and write operations by the master; Further comprising a data length indicative of the size; The slave port identifier, the memory start address and the data length is set when the slave receives the access request from the master. In a System on Chip (SoC) that controls access to one slave by two or more masters, And an interconnect having a register file in which driving information corresponding to the access is registered or updated when an access is made from any one master. The method of claim 6, Examine the register file to determine whether an exclusive access by another master is being performed, and when exclusive access by another master is being performed, obtain driving information from the register file, and based on the obtained drive information, And at least one master for requesting access to the remaining area of the memory area in which access by the other master is not performed. The method of claim 7, wherein the slave, And a memory in which data read / write operation is performed when the exclusive access by the master is performed. In a master for controlling access to one slave by two or more masters in a System on Chip (SoC), A controller for inspecting a register file of an interconnect when accessing the slave; If the register file includes information indicating that another master is performing access to the slave according to the instruction of the controller, the master obtains driving information from the register file, and the driving information. And an access execution unit for acquiring information on a remaining area of the slave memory area except the memory accessed by the other master, from which the master performs access to the remaining area. The method of claim 9, The register file includes an indication flag indicating whether there is a master performing access for each slave, a counter indicating a number of masters performing access to the slave, and a master identifier. 11. The method of claim 10, The indication flag, the counter and the master identifier is set by the other master requesting access to the slave. 12. The method of claim 11, The register file, A slave port identifier indicating an identifier of the slave to perform the read and write operations by the master, a memory start address of the slave to perform the read and write operations by the master, and data to perform the read and write operations by the master; Further comprising a data length indicative of the size; Wherein the slave port identifier, the memory start address and the data length are set when the slave receives an access request from the master.

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