CN115688654A - EFUSE model for FPGA verification and start and FPGA verification and start method - Google Patents

Abstract

The invention relates to the technical field of chip verification, in particular to an EFUSE (extensible firmware interface) model for FPGA (field programmable gate array) verification starting and an FPGA verification starting method. An EFUSE model for FPGA verification start and a method for FPGA verification start, wherein the model comprises a ROM model and a signal terminal; the ROM model is embedded in the FPGA; each signal terminal of the EFUSE model corresponds to each signal terminal of the EFUSE in the chip to be verified and is respectively connected to a terminal matched with the function of the EFUSE in the ROM model; the ROM model is used for storing an EFUSE value corresponding to the current starting mode of the chip to be verified. According to the invention, the EFUSE model is built on the basis of the ROM model, the compatibility with the FPGA is realized, and when the verification chip is started in different modes, multiple times of comprehensive FPGA engineering is not needed, so that the time is saved, and the efficiency is improved.

Description

EFUSE model for FPGA verification and start and FPGA verification and start method

Technical Field

The invention relates to the technical field of chip verification, in particular to an EFUSE (extensible firmware interface) model for FPGA (field programmable gate array) verification starting and an FPGA verification starting method.

Background

The design of the chip needs to be verified before chip flow, and an FPGA (Field Programmable Gate Array) can almost completely map the logic design of the chip, so that the chip verification has the advantages of high speed, multiple coverage scenes and the like, and is an essential important means in the chip verification at present.

An EFUSE (electronic fuse) is a one-time-programming non-volatile memory used for storing information related to chip startup. When the FPGA is adopted to verify the chip starting process, the value in the EFUSE is usually used, but EFUSE manufacturers often only provide a verilog (a hardware description language) model at the front end, wherein a large number of incomplex statements are contained, so that the EFUSE is incompatible with the FPGA.

In verification, the FPGA is an important verification means. The chip start has a plurality of different modes, and different EFUSE values are required to be adopted in different modes. Because the EFUSE is incompatible with the FPGA, when the FPGA verification chip is started in different modes, only the EFUSE value corresponding to the mode to be verified can be written into the FPGA in advance, and then the comprehensive FPGA engineering is carried out. And multiple times of comprehensive FPGA engineering is needed to verify different modes, so that the time consumption is high. Today, the chip scale is larger, the work time is more and more, and the efficiency of chip verification is affected.

Disclosure of Invention

The invention aims to solve the technical problems that an EFUSE model for FPGA verification starting and an FPGA verification starting method are provided aiming at the defects of the related technology, so that the problems that the verification starting needs to be carried out by integrating FPGA engineering for multiple times due to incompatibility of the EFUSE and the FPGA, the time consumption is long, and the efficiency is low are solved.

The technical scheme adopted by the invention for solving the technical problems is as follows: providing an EFUSE model for FPGA verification start, wherein the EFUSE model comprises a ROM model and signal terminals comprising the ROM model and the signal terminals; the ROM model is embedded in the FPGA; the signal terminal of the EFUSE model corresponds to the signal terminal of the EFUSE in the chip to be verified; each signal terminal of the EFUSE model is respectively connected to a terminal which is matched with each signal terminal in the ROM model in function; the ROM model is used for storing the EFUSE value corresponding to the current starting mode of the chip to be verified.

Wherein, the preferred scheme is: the EFUSE model comprises a read-write control signal terminal, the ROM model comprises a clock signal terminal, and the read-write control signal terminal is connected with the clock signal terminal.

Wherein, the preferred scheme is: the EFUSE model comprises a main power switch signal terminal, the ROM model comprises a reset signal terminal, and the main power switch signal terminal is connected with the reset signal terminal.

Wherein, the preferred scheme is: the EFUSE model comprises a burning power switch signal terminal and a mode selection signal terminal; the ROM model includes a read enable signal terminal;

the EFUSE model further comprises a combinational logic model, and the burning power switch signal terminal and the mode selection signal terminal are connected with the reading enabling signal terminal through the combinational logic model.

Wherein, the preferred scheme is: and the combinational logic model is used for judging whether the EFUSE model is in a read mode currently according to the burning power supply switch signal and the mode selection signal.

Wherein, the preferred scheme is: the EFUSE model and the ROM model both comprise address signal terminals, and the address signal terminals of the EFUSE model and the address signal terminals of the ROM model are correspondingly connected.

Wherein, the preferred scheme is: the EFUSE model and the ROM model both comprise data signal terminals, and the data signal terminals of the EFUSE model and the data signal terminals of the ROM model are correspondingly connected.

The technical scheme adopted by the invention for solving the technical problems is as follows: a method for verifying and starting FPGA is provided, which comprises the following steps:

integrating the EFUSE model into FPGA engineering;

storing the EFUSE value corresponding to the current starting mode of the chip to be verified to the ROM model;

and electrifying the FPGA to read the current EFUSE value in the EFUSE model, and performing the start verification of the chip to be verified in the current start mode.

Preferably, the step of integrating the EFUSE model into the FPGA engineering includes:

when the FPGA is compiled, replacing the original EFUSE model of the chip to be verified by the EFUSE model;

and integrating the replaced EFUSE model into filelist of the FPGA.

Preferably, the step of storing the EFUSE value corresponding to the current startup mode of the chip to be verified in the ROM model includes:

designing a current starting mode of the chip to be verified and an EFUSE value corresponding to the current starting mode;

and programming the corresponding EFUSE value into the ROM model.

Compared with the prior art, the invention has the beneficial effects that the EFUSE model is built on the basis of the ROM model compatible with the FPGA, and the EFUSE model is connected with the signal terminal of the ROM model in a matching way, so that the EFUSE model can realize normal communication with the FPGA through the ROM model. After the EFSUSE model is used for carrying out comprehensive FPGA engineering, before different modes are verified to be started each time, the EFUSE value corresponding to the mode is stored into the ROM model and can be read by the FPGA for use during verification, the comprehensive FPGA engineering is not needed to be carried out in each mode, the verification time is saved, and the verification efficiency is improved.

Drawings

The invention will be further described with reference to the accompanying drawings and examples, in which:

FIG. 1 is a schematic diagram of an EFUSE model according to an embodiment of the present invention;

FIG. 2 is a timing diagram of the reading of the EFUSE model in an embodiment of the present invention.

Detailed Description

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

The following is explained with respect to possible English nouns involved in the examples:

FPGA: field Programmable Gate Array, field Programmable Gate Array;

EFUSE: electronic Fuse, one-time programmable memory;

verilog: a hardware description language;

ROM: read-Only Memory, read-Only Memory;

SRAM: static Random-Access Memory (SRAM);

fililist: and (5) simulating the file.

The FPGA designs a hardware description language, namely programming, according to the functions of the hardware circuit, and then maps the circuit description in the form to an actual circuit, namely synthesis, so as to form the hardware circuit with the set functions. The FPGA is adopted to verify the chip, namely, the simulation of the chip function is realized by utilizing the characteristics of the FPGA, and the simulation of EFUSE in the chip needs to be carried out by means of a verilog model provided by an EFUSE manufacturer. However, verilog model is not compatible with FPGA, so it is a common practice to directly write the value of EFUSE in constant form into configuration file of FPGA during programming, and perform comprehensive FPGA engineering on the basis of the value. The chip is started in different modes, the corresponding EFUSE functions are different, the required EFUSE values are also different, and the FPGA needs to cover all the modes, so that the EFUSE values corresponding to the modes can be rewritten before the starting of different modes is simulated, and then the combination is carried out again to form a hardware circuit corresponding to the modes. This undoubtedly burdens developers and it is desirable to have an EFUSE model that is both compatible with FPGAs and simulates the EFUSE functions.

The FPGA has a corresponding ROM (Read-Only Memory) model, internal values can be quickly re-burned without recompiling FPGA engineering, and the FPGA model is completely compatible with the logic design of the FPGA. And is non-volatile, i.e., power is not lost to the contents stored therein; the chip can not be programmed by itself; its ports typically include clock, reset, read enable, read address, and read data.

In addition, the burning work of the EFUSE can be not considered in the starting process of the FPGA verification chip. The work is generally finished when an ATE machine station tests or a user just takes a chip, and meanwhile, in a starting scene, the burning function of the EFUSE does not need to be verified, and the EFUSE burning time sequence is not easy to verify on the FPGA, so the verification is generally not carried out on the FPGA. The burning of the EFUSE needs another method for verification, which is not described herein again. Therefore, only the read function of EFUSE needs to be verified when the FPGA verification chip is adopted for starting.

The ROM has a ready FPGA model and has the characteristic of being capable of modifying an initial value without recompiling engineering, and the requirement of a reading function can be completely met. Therefore, the FPGA model of the EFUSE can be built on the basis of the FPGA model of the ROM.

Further, ROM has signals that function similarly to EFUSE. Such as: the ROM has a clock and a reset signal, while the EFUSE does not have the signal, the EFUSE generally has a PD (power down) signal and can be used as the reset of the ROM; there is also a direct enable signal such as STROBE or others, and pulling up the signal after selecting the read mode can read the data of the corresponding address, and can be used as a clock. The address can be directly used as the address, and other mode selection signals can jointly generate a chip selection signal of the ROM.

Specifically, referring to fig. 1, the present invention provides a preferred embodiment of an EFUSE model 100 for FPGA validation boot.

The EFUSE model 100 comprises a ROM model 200 embedded in an FPGA and a signal terminal corresponding to an EFUSE signal terminal in a chip to be verified; each signal terminal of the EFUSE model 100 is connected to a terminal of the ROM model 200 that is functionally matched to the signal terminal; the ROM model 200 may be used to store the EFUSE value corresponding to the current boot mode of the chip to be verified. Since the EFUSE model 100 needs to replace the original EFUSE of the chip to be verified to realize its function, the EFUSE model 100 has various signal terminals corresponding to the EFUSE in the chip to be verified. The ROM model 200 then has the various signal terminals needed to communicate with the FPGA. The signal terminals of the EFUSE model 100 are respectively connected to terminals functionally matched with the signal terminals in the ROM model 200, so that the EFUSE model 100 can realize communication with the FPGA based on the ROM model 200.

The logic design of the ROM model 200 is compatible with that of the FPGA, which can read the data in the ROM model 200 at any time. Therefore, after the entity circuit with the chip to be verified and the EFUSE function thereof is formed by integrating FPGA engineering mapping, the data can be directly read by the FPGA when the chip is verified as long as the EFUSE value corresponding to the current mode to be verified is stored in the ROM model 200 before verification, and the starting process under the mode is simulated. The start-up under different modes is verified, and only the corresponding EFUSE value needs to be rewritten before verification every time, and the comprehensive FPGA engineering is not needed to be performed again, so that the time required by verification is saved, and the efficiency is improved.

And an FPGA verification chip is adopted, and the simulated content is required to be consistent with the actual product as much as possible so as to ensure the accuracy of the verification result. Based on this, the embodiment adopts the ROM model embedded in the FPGA to build the EFUSE model.

The FPGA has various Memory models, and besides the ROM model, other Memory models are usually an SRAM (Static Random-Access Memory) model, which is volatile storage and cannot achieve the effect of storing expected data when the FPGA is powered on. The data in the ROM model can be quickly rewritten and cannot be rewritten by the chip, and the data is nonvolatile, namely, cannot be lost when power is off, and is closest to the EFUSE working mode. Similarly, because the chip to be verified is embedded with the EFUSE, the ROM model 200 is embedded and is closest to an actual product, so that the real process is restored as much as possible during verification.

In a preferred embodiment, the signal terminals required for the ROM model 200 to communicate with the FPGA include clock, reset, read enable, read address, and read data. The signal terminals of EFUSE generally include: the EFUSE model 100 corresponds to the EFUSE of the chip to be verified and also has the signal terminals described above.

Referring to fig. 2, EFUSE model 100 has no clock and reset signals, and thus the EFUSE model 100 is built using ROM model 200 as follows:

in the read mode, EFUSE model 100 reads data a period of time after the rising edge of read/write control signal STROBE, and ROM model 200 reads data at the rising edge of the clock, so that read/write control signal STROBE of EFUSE model 100 is connected to the clock signal of ROM model 200. When the read/write control signal STROBE of the EFUSE model 100 is pulled high, the ROM model 200 obtains a clock signal to start reading the data corresponding to the specific address.

EFUSE model 100 does not work at all when total power switch signal PD is off, so total power switch signal PD of EFUSE model 100 is connected to the reset terminal of ROM model 200. When the total power switch signal PD of the EFUSE model 100 is turned off, the ROM model 200 is in a reset state.

The EFUSE model 100 is in a programming mode when the programming power switch signal PS is turned on, and is in a reading mode when the programming power switch signal PS is turned off, and the mode selection signal includes a plurality of signal terminals. The burst power switch signal PS and the mode selection signal of the EFUSE model 100 are connected to the read enable signal of the ROM model 200 through the combinational logic model 300.

The mode selection logic for EFUSE provided by different vendors differs, but is the result of a combination of multiple signals. For example, in the simplest case, when the chip select enable signal CEN, the write mode control signal WEN, and the read mode control signal REN CEN are not selected, neither the WEN nor REN signals are asserted; when the CEN chip selection signal is selected and WEN is selected, the write mode is selected; when CEN is selected and WEN is not selected, read mode, there may also be a TEST mode enable signal TEST.

The combinational logic model 300 has different specific implementations for different mode selection logics of different EFUSEs, but basically is an and-or-nor logic or a combination thereof, and is used for judging whether the EFUSE model is currently in a read mode according to the burning power switch signal PS and the mode selection signal, that is, controlling the read-write enable of the ROM model according to different read-write mode requirements. For example, when the power switch signal PS is turned off, if CEN is selected, WEN is unselected, REN is selected, and TEST is unselected, the current mode is determined to be the read mode, and a read enable signal is given, that is: the read enable signal of the ROM is the result of the logical combination of the above signals. Thereby enabling reading of the ROM model 200 data.

The EFUSE model 100 and the ROM model 200 further include an address signal terminal and a data signal terminal, the address signal terminal of the EFUSE model 100 and the address signal terminal of the ROM model 200 are correspondingly connected, the data signal terminal of the EFUSE model 100 and the data signal terminal of the ROM model 200 are correspondingly connected, and when a read command is received, the synchronization of the address and the data of the EFUSE model 100 and the ROM model 200 can be realized.

As described above, when the signal terminals of the EFUSE model 100 and the ROM model 200 are functionally matched, the communication between the command and the data can be realized. After receiving the read command, EFUSE model 100 reads data according to its timing, and EFUSE model 100 actually reads data from ROM model 200 according to its timing since EFUSE model 100 and ROM model 200 have established a connection.

For example, the secure boot mode belongs to a chip boot mode, and a hash value of a key needs to be read from a specific bit in EFUSE during the secure boot process of the chip as verification, so that the information needs to be read from EFUSE during the boot stage. This value is stored at an address corresponding to ROM model 200, and when FPGA verification starts, this information is read from a specific bit of EFUSE model 100, that is, from the address corresponding to ROM model 200.

In conclusion, the EFUSE model 100 is adopted to replace the EFUSE of the chip to be verified, the behavior and the real situation are completely consistent in the starting process, and the replaced EFUSE model 100 is completely compatible with the FPGA.

Based on the EFUSE model 100, another preferred embodiment of the present invention provides a method for verifying and starting an FPGA, the method comprising:

integrating the EFUSE model 100 into FPGA engineering;

storing the chip EFUSE value corresponding to the current starting of the chip to be verified to the ROM model 200;

and electrifying the FPGA to read the current EFUSE value in the EFUSE model 100, and performing start verification on the chip to be verified in the current start mode.

Namely, when compiling the FPGA, the original EFUSE model 100 of the chip to be verified is replaced with the built EFUSE model 100 based on the ROM model 200, that is, the EFUSE model 100 of the present invention is used to replace a verilog model provided by an EFUSE manufacturer, a filelist (simulation file) of the FPGA is incorporated, on the basis, the FPGA engineering is synthesized, and the entity circuit including the EFUSE model 100 of the present invention is formed by mapping.

Next, a verification stage may be entered, a desired EFUSE value is designed before verification starts, that is, a current mode to be verified is designed, and a corresponding EFUSE value needs to be used in the mode, for example, a specific bit of the EFUSE indicates an initial configuration of PCIe (peripheral component interconnect express), and the bit needs to be a value corresponding to different configuration options before power up in the FPGA verification process. This value is programmed into ROM model 200.

When the verification starts, the FPGA is electrified, and the value is read from the EFUSE model 100, so that the starting of the corresponding mode can be simulated, and the verification of the starting of the chip in the mode is realized.

Based on the EFUSE model 100 of the invention, the chip is verified to be started, the EFUSE value required by the current to-be-verified mode is written in the ROM model 200 before verification, and the FPGA can read the relevant information after being electrified. Therefore, different modes are verified, the comprehensive FPGA engineering is not needed to be carried out again, and the efficiency is obviously improved.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention.

Claims (10)

1. An EFUSE model for FPGA verification start, which is characterized in that: the EFUSE model comprises a ROM model and a signal terminal;

the ROM model is embedded in the FPGA;

the signal terminal of the EFUSE model corresponds to the signal terminal of the EFUSE in the chip to be verified;

each signal terminal of the EFUSE model is respectively connected to a terminal which is matched with each signal terminal in the ROM model in function;

the ROM model is used for storing the EFUSE value corresponding to the current starting mode of the chip to be verified.

2. The EFUSE model of claim 1, wherein: the EFUSE model comprises a read-write control signal terminal, the ROM model comprises a clock signal terminal, and the read-write control signal terminal is connected with the clock signal terminal.

3. The EFUSE model of claim 1, wherein: the EFUSE model comprises a main power switch signal terminal, the ROM model comprises a reset signal terminal, and the main power switch signal terminal is connected with the reset signal terminal.

4. The EFUSE model of claim 1, wherein: the EFUSE model comprises a burning power switch signal terminal and a mode selection signal terminal; the ROM model includes a read enable signal terminal;

the EFUSE model further comprises a combinational logic model, and the burning power switch signal terminal and the mode selection signal terminal are connected with the read enabling signal terminal through the combinational logic model.

5. The EFUSE model of claim 4, wherein: and the combinational logic model is used for judging whether the EFUSE model is in a read mode currently according to the burning power supply switch signal and the mode selection signal.

6. The EFUSE model of claim 1, wherein: the EFUSE model and the ROM model both comprise address signal terminals, and the address signal terminals of the EFUSE model and the address signal terminals of the ROM model are correspondingly connected.

7. The EFUSE model of claim 1, wherein: the EFUSE model and the ROM model both comprise data signal terminals, and the data signal terminals of the EFUSE model and the data signal terminals of the ROM model are correspondingly connected.

8. A method for verifying starting of an FPGA (field programmable gate array) is characterized by comprising the following steps:

integrating the EFUSE model of any one of claims 1-7 into FPGA engineering;

storing the EFUSE value corresponding to the current starting mode of the chip to be verified to the ROM model;

and electrifying the FPGA to read the current EFUSE value in the EFUSE model, and performing the start verification of the chip to be verified in the current start mode.

9. The method of claim 8, wherein the step of integrating the EFUSE model into FPGA engineering comprises:

when the FPGA is compiled, replacing the original EFUSE model of the chip to be verified by the EFUSE model;

and integrating the replaced EFUSE model into the filelist of the FPGA.

10. The method according to claim 8, wherein the step of storing the EFUSE value corresponding to the current startup mode of the chip to be verified in a ROM model comprises:

designing a current starting mode of the chip to be verified and an EFUSE value corresponding to the current starting mode;

and programming the corresponding EFUSE value into the ROM model.

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