CN114327516A - Circuit and method for modifying chip system memory to burn - Google Patents
Circuit and method for modifying chip system memory to burn Download PDFInfo
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- CN114327516A CN114327516A CN202111631843.8A CN202111631843A CN114327516A CN 114327516 A CN114327516 A CN 114327516A CN 202111631843 A CN202111631843 A CN 202111631843A CN 114327516 A CN114327516 A CN 114327516A
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Abstract
The invention discloses a circuit and a method for modifying a chip system memory to burn, which comprises the following steps: (1) compiling an FPGA engineering file; (2) burning the engineering file into the FPGA; (3) completing the circuit connection; (4) starting a burning program, and outputting a control instruction to the flash by the engineering file by means of the bistpad so as to modify the data of the system memory; (5) and detecting whether the program is burned successfully. The invention utilizes the best test pad of the flash in the chip to enter the best mode, the chip to be tested is connected through the fpga board, corresponding erasing instructions and contents are sent to the best serial interface, the contents of the system memory can be modified after the chip leaves the factory, the BootLoader program can be conveniently tested, and the debugging and the testing of the flash by the chip are convenient.
Description
Technical Field
The invention relates to a circuit and a method for modifying a chip system memory to burn, belonging to the technical field of chip testing.
Background
flash is a kind of memory chip, and the data in it can be modified by a specific program. Flash generally means a Flash Memory in the field of electronics and semiconductors, that is, a Flash Memory in general. The flash memory is also called as flash memory, combines the advantages of ROM and RAM, not only has the performance of Electrically Erasable Programmable (EEPROM), but also can quickly read data (the advantage of NVRAM), so that the data can not be lost due to power failure.
flash has 3 boot modes, one of which is booted by means of BootLoader in a system memory. The system memory contains a BootLoader program that can be used to reprogram the flash memory using the USART1 serial interface. The system memory is typically only capable of writing content at the time of chip manufacture and the user is not able to modify the content. In order to test the written BootLoader program and facilitate debugging and testing of the flash, the content of a system memory needs to be modified after the chip leaves a factory.
At this time, a circuit and a method for modifying a system-on-chip memory for burning are provided, and a bist circuit of the flash is intended to solve the problems of testing the physical fault and the yield of a flash area. A factory enters a test mode through a test PAD, different signals are sent according to a list signal sequence to enter different test modes so as to test whether a flash storage area is damaged or not, a bad area address is recorded, and a redundant sector is used for replacement. According to the principle, when the chip is tested after leaving the factory, the bist test pad is used for entering a bist mode, the chip is connected through the FPGA board, corresponding erasing instructions and contents are sent to a bist serial interface, the contents in a system memory can be changed, and the BootLoader test is carried out.
Disclosure of Invention
The invention aims to provide a circuit and a method for modifying a chip system memory for burning, aiming at modifying the content in the system memory and facilitating the subsequent BootLoader test.
In order to achieve the purpose, the invention provides the following technical scheme: the utility model provides a modify chip system memory and carry out circuit of burning record, including FPGA, MCU surveys the board, the chip that awaits measuring, downloader and host computer, the chip that awaits measuring is installed on MCU surveys the board, make flash be connected with MCU survey the corresponding pin of board, FPGA and MCU survey board power pin access power, FPGA and MCU survey board GND pin ground connection, downloader one end passes through serial ports with FPGA, the downloader other end is connected with the host computer, FPGA surveys the board with MCU and is connected, make FPGA's TDI, TCK, TDO, STROBE pin and flash's TDI, TCK, TDO, STROBE pin corresponds the connection, flash's TESTING pin is the high level.
The invention also discloses a method for modifying the chip system memory for burning, which adopts the circuit for modifying the chip system memory for burning and comprises the following steps:
(1) writing an FPGA engineering file required by burning;
(2) burning the engineering file into the FPGA;
(3) completing the circuit connection;
(4) pressing a reset key of the FPGA to start burning a program, communicating the FPGA and the flash through a bistpad, and outputting a control instruction to the flash by the engineering file through the bistpad so as to modify the data of a system memory;
(5) and (4) detecting whether the program is burnt successfully, if so, finishing the program burning, and if not, repeating the step (4) and then continuing to execute the program.
Further, the method for modifying the chip system memory for burning includes: the FPGA engineering file written in the step (1) follows a flash IP bist protocol, and the content in the engineering file comprises: the high level of the flash interface signal ERASE is used for erasing the original system memory in the flash, the high level of the flash interface signal PROG is used for burning programs, and addresses and data are respectively written in the flash interface signal A and the flash interface signal DIN, so that the modification of the system memory is realized.
Further, the method for modifying the chip system memory for burning includes: the step (4) of outputting the control instruction to the flash by the engineering file of the FPGA by means of the bistpad so as to modify the data of the system memory specifically comprises the following steps: 1.1, outputting a password, and entering a test mode test _ mode; 1.2, outputting an erase instruction, and erasing the content of a system memory in the chip; 1.3, outputting program finger and prog address and data.
Further, the method for modifying the chip system memory for burning includes: the step (5) specifically comprises the following steps: 5.1, powering off the chip to be tested and then powering on again; 5.2, connecting the upper computer and the MCU test board by using a data line; 5.3, opening a serial port tool to connect a serial port; 5.4, reading the device information and the option bytes, checking whether the device information and the option bytes are correct, if so, executing the next step, and if not, returning to the step (4) to burn the program again; 5.5, downloading a program; 5.6 checking whether the MCU test board executes the corresponding function, if so, successfully detecting to indicate that the system memory is successfully modified, and if not, returning to the step (4) to re-burn the program.
Further, the method for modifying the chip system memory for burning includes: and 5.5, the downloading program is a horse race lamp or water lamp program.
The invention has the beneficial effects that: the invention enters the best mode by using the best test pad of the flash in the chip, is connected with the chip to be tested by the fpga board, sends corresponding erasing instructions and contents to the best serial interface, and can modify the contents of the system memory after the chip leaves the factory, thereby being convenient for testing the BootLoader program and debugging and testing the flash by the chip.
Drawings
FIG. 1 is a schematic diagram of a connection circuit between an FPGA and a flash pin according to the present invention;
FIG. 2 is a flowchart of program burning;
FIG. 3 is a flowchart of the project file outputting control instructions to the flash via the bistpad;
FIG. 4 is a diagram of the flash IP best protocol;
FIG. 5 is a flowchart illustrating the verification process after the program is burned.
Detailed Description
For further understanding of the contents, features and effects of the present invention, the following detailed description is given in conjunction with the accompanying drawings.
Referring to fig. 1 to 5, a circuit and a method for modifying a system-on-chip memory for burning will be described in detail with reference to the drawings.
As shown in figure 1, the circuit for modifying the system-in-chip memory to burn by means of the flash bist test mechanism comprises an FPGA, an MCU test board, a chip to be tested, a downloader and an upper computer, wherein the chip to be tested is installed on the MCU test board, so that the flash is connected with corresponding pins of the MCU test board, power pins of the FPGA and the MCU test board are connected with a power supply, GND pins of the FPGA and the MCU test board are grounded, one end of the downloader is connected with the FPGA through a serial port, the other end of the downloader is connected with the upper computer, the FPGA is connected with the MCU test board, so that TDI, TCK, TDO and STROBE pins of the FPGA are correspondingly connected with TDI, TCK, TDO and STROBE pins of the flash, and the TESTING pin of the flash is at a high level.
Specifically, TESTING is a test mode enable signal and enters test mode when it is high. TCK is the test clock, TDI is the test input, TDO is the test output, STROBE is the control signal whether the input signal is valid or not. The control signal STROBE is active low and if STROBE is low, the test stimulus signal at the serial input pin TDI will be input. When STROBE is set high, data in TDI will be ignored.
As shown in fig. 2, the present invention also discloses a method for modifying a circuit for burning in an on-chip system memory by means of a flash bist test mechanism, which comprises the following steps:
(1) writing an FPGA engineering file required by burning; (2) burning the engineering file into the FPGA; (3) completing the circuit connection; (4) pressing a reset key of the FPGA to start burning a program, communicating the FPGA and the flash through a bistpad, and outputting a control instruction to the flash by the engineering file through the bistpad so as to modify the data of a system memory; (5) and (4) detecting whether the program is burnt successfully, if so, finishing the program burning, and if not, repeating the step (4) and then continuing to execute the program. And (4) waiting for 20-40 seconds of response time after the program is burned in the step (4), and preferably waiting for 30 seconds.
The FPGA engineering file written in the step (1) follows a flash IP bist protocol, and the content in the engineering file comprises: the high level of the flash interface signal ERASE is used for erasing the original system memory in the flash, the high level of the flash interface signal PROG is used for burning programs, and addresses and data are respectively written in the flash interface signal A and the flash interface signal DIN, so that the modification of the system memory is realized.
As shown in fig. 3, the step (4) of outputting a control instruction to the flash by the engineering file of the FPGA through the bistpad to modify the system memory data specifically includes the following steps: 1.1, outputting a password, and entering a test mode test _ mode; 1.2, outputting an erase instruction, and erasing the content of a system memory in the chip; 1.3, outputting program finger and prog address and data. A response time is waited between step 1.2 and step 1.3.
The communication between the FPGA and the flash, the instruction sent by the serial interface follows the flash IP bist protocol, specifically referring to fig. 4, fig. 4 shows the input timing and the input sequence of the protocol serial input pin TDI, wherein the general test frequency of the test clock TCK may be set to 1MHz, 10MHz, or 20 MHz.
The method comprises the following steps that a test output pin TDI of the FPGA sends a serial input signal to a test input pin TDI of the flash in the following sequence: CEb, DEEPPD, OEb, WEb, PROG, PROG2, ERASE, CHIP, NVR, TMEN, CONFEN, VREAD0, VREAD1, BYTE, A, DIN, msa, msb, msc, msd, freq0, freq1, Tprog _ conf0, Tprog _ conf1, Terase _ conf0, Terase _ conf 1; the CEb to DIN are flash IP interface signals, including enable signals, program erase control, address and data signals, for controlling the flash operation. Signals msa, msb, msc, msd, freq0, and freq1 in the serial input data stream are used to define the test mode and operating frequency. The Tprog _ conf0, Tprog _ conf1 signals are used to set the word program time Tprog, Terase _ conf0, Terase _ conf1 signals are used to set the sector/block erase time Terase.
As shown in fig. 4, the step (5) specifically includes the following steps: 5.1, powering off the chip to be tested and then powering on again; 5.2, connecting the upper computer and the MCU test board by using a data line; 5.3, opening a serial port tool to connect a serial port; 5.4, reading the device information and the option bytes, checking whether the device information and the option bytes are correct, if so, executing the next step, and if not, returning to the step (4) to burn the program again; 5.5, downloading a program; 5.6 checking whether the MCU test board executes the corresponding function, if so, successfully detecting to indicate that the system memory is successfully modified, and if not, returning to the step (4) to re-burn the program. The step 5.5 downloading program is a horse race lamp or water lamp program, and whether the LED of the MCU test board can correspondingly emit light or extinguish according to the program is checked in the step 5.6.
It can be seen from the above description that the invention enters the best mode by using the best test pad of the flash in the chip, connects the chip to be tested through the fpga board, sends the corresponding erasing and writing instructions and contents to the best serial interface, and can modify the system memory contents after the chip leaves the factory, thereby facilitating the test of the BootLoader program and the debugging and testing of the flash by the chip.
The above are only typical examples of the present invention, and besides, the present invention may have other embodiments, and all the technical solutions formed by equivalent substitutions or equivalent changes are within the scope of the present invention as claimed.
Claims (6)
1. A circuit for modifying a system-on-chip memory for burning, comprising: including FPGA, MCU surveys the board, the chip that awaits measuring, downloader and host computer, the chip that awaits measuring is installed on MCU surveys the board, make flash be connected with MCU survey the corresponding pin of board, FPGA and MCU survey board power pin and insert the power, FPGA and MCU survey board GND pin ground connection, downloader one end passes through serial ports with FPGA, the downloader other end is connected with the host computer, FPGA surveys the board with MCU and is connected, make FPGA's TDI, TCK, TDO, STROBE pin and flash's TDI, TCK, TDO, STROBE pin corresponds the connection, flash's TESTING pin is the high level.
2. A method for modifying a system-on-chip memory for programming, wherein the circuit for modifying a system-on-chip memory for programming as claimed in claim 1 comprises the steps of:
(1) writing an FPGA engineering file required by burning; (2) burning the engineering file into the FPGA; (3) completing the circuit connection; (4) pressing a reset key of the FPGA to start burning a program, communicating the FPGA and the flash through a bistpad, and outputting a control instruction to the flash by the engineering file through the bistpad so as to modify the data of a system memory; (5) and (4) detecting whether the program is burnt successfully, if so, finishing the program burning, and if not, repeating the step (4) and then continuing to execute the program.
3. The method of claim 2, wherein the method further comprises: the FPGA engineering file written in the step (1) follows a flash IP bist protocol, and the content in the engineering file comprises: the high level of the flash interface signal ERASE is used for erasing the original system memory in the flash, the high level of the flash interface signal PROG is used for burning programs, and addresses and data are respectively written in the flash interface signal A and the flash interface signal DIN, so that the modification of the system memory is realized.
4. The method of claim 2, wherein the method further comprises: the step (4) of outputting the control instruction to the flash by the engineering file of the FPGA by means of the bistpad so as to modify the data of the system memory specifically comprises the following steps: 1.1, outputting a password, and entering a test mode test _ mode; 1.2, outputting an erase instruction, and erasing the content of a system memory in the chip; 1.3, outputting program finger and prog address and data.
5. The method of claim 2, wherein the method further comprises: the step (5) specifically comprises the following steps: 5.1, powering off the chip to be tested and then powering on again; 5.2, connecting the upper computer and the MCU test board by using a data line; 5.3, opening a serial port tool to connect a serial port; 5.4, reading the device information and the option bytes, checking whether the device information and the option bytes are correct, if so, executing the next step, and if not, returning to the step (4) to burn the program again; 5.5, downloading a program; 5.6 checking whether the MCU test board executes the corresponding function, if so, successfully detecting to indicate that the system memory is successfully modified, and if not, returning to the step (4) to re-burn the program.
6. The method of claim 5, wherein the method further comprises: and 5.5, the downloading program is a horse race lamp or water lamp program.
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| CN115767818A (en) * | 2022-12-13 | 2023-03-07 | 深圳市美矽微半导体有限公司 | Control method for LED lighting mode |
| CN117194346A (en) * | 2023-11-06 | 2023-12-08 | 上海合见工业软件集团有限公司 | Download file clearing method, electronic equipment and storage medium |
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| CN115220978A (en) * | 2022-09-19 | 2022-10-21 | 瀚博半导体(上海)有限公司 | Chip starting method and device including online debugging mode, chip and equipment |
| CN115767818A (en) * | 2022-12-13 | 2023-03-07 | 深圳市美矽微半导体有限公司 | Control method for LED lighting mode |
| CN115767818B (en) * | 2022-12-13 | 2023-11-17 | 深圳市美矽微半导体股份有限公司 | Control method for LED lighting mode |
| CN117194346A (en) * | 2023-11-06 | 2023-12-08 | 上海合见工业软件集团有限公司 | Download file clearing method, electronic equipment and storage medium |
| CN117194346B (en) * | 2023-11-06 | 2024-01-23 | 上海合见工业软件集团有限公司 | Download file clearing method, electronic equipment and storage medium |
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