CN114692540A - FLASH application verification system based on FPGA - Google Patents
FLASH application verification system based on FPGA Download PDFInfo
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Abstract
The invention discloses a FLASH application verification system based on FPGA, comprising a PC, an FPGA application verification board and a FLASH daughter board. The FPGA application verification board is provided with two FPGA chips; each FPGA chip is connected with the FLASH, and can independently access the FLASH to carry out verification operation on the FLASH; each FPGA is externally connected with a large-capacity 160 MbSRAM; the replacement of the FLASH daughter board can verify the NOR _ FLASH and the SPI _ FLASH. The invention also discloses a verification method based on the system, which firstly determines the power-on sequence, the JTAG function verification, the digital logic verification and the read-write function verification. The invention has comprehensive verification function and strong universality and has important significance for the application verification of a series of FLASH.
Description
Technical Field
The invention belongs to the field of chip application verification, relates to application verification in the field of nonvolatile memories, and particularly relates to a FLASH application verification system based on an FPGA.
Background
With the development of science and technology, the storage and processing of data become more and more important; the nonvolatile memory has the characteristic that power-off data cannot be lost, so the application field is very wide.
At present, manufacturers for designing and producing FLASH for aerospace in China are relatively few, FLASH verification projects are not sufficient enough, and the FLASH is not compatible with different models, wherein most of application verification systems and verification methods mainly verify the time sequence matching of the FLASH and have no universality. Therefore, a FLASH application verification system needs to be developed, which can be used for various FLASH memories in general, so as to meet the application verification requirements of the nonvolatile memory.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the defects of the prior art are overcome, and a set of FLASH application verification system with strong universality and comprehensive verification functions is provided for the application verification of various FLASH.
In order to achieve the purpose, the invention adopts the following technical scheme to realize the purpose:
a FLASH application verification system based on FPGA comprises a PC, a FLASH application verification board and a program-controlled power supply;
the FLASH application verification board comprises two FPGAs, a serial port module, a power supply module, a configuration memory connector, a JTAG and an SRAM; the two FPGAs are respectively marked as FPGA _ A and FPGA _ B;
when the erasing and reading functions of the tested FLASH are verified, the tested FLASH is connected with the IO port of the FPGA _ A; when the JTAG function and the memory configuration function of the tested FLASH are verified, the tested FLASH is connected with a configuration memory connector, and the configuration memory connector is a configuration interface of the FPGA;
the serial port module is used for connecting the PC and the FPGA _ A, sending erasing, writing and reading instructions of the PC to the FPGA _ A and feeding back a result fed back by the FPGA _ A to the PC;
the FPGA _ A carries out erasing, writing and reading tests on the tested FLASH according to the erasing, writing and reading instructions of the PC, acquires the output data of the tested FLASH, judges whether the tested FLASH works normally according to the output data, and feeds back the judgment result to the serial port module;
the FPGA _ B collects all input and output data of the FLASH to be tested which is working, and sends the data to the PC through the configuration memory connector and the JTAG;
a PC machine: when the erasing and reading functions of the tested FLASH are verified, an erasing, writing and reading instruction is sent to the serial port module, and a result fed back by the FPGA _ A is received and displayed; when the JTAG function of the tested FLASH is verified, an erasing, writing and reading instruction is sent to the tested FLASH through the JTAG, and a result fed back by the tested FLASH is read and displayed through the JTAG; sending a program configuration instruction to the tested FLASH through a JTAG to verify the memory configuration function of the tested FLASH; displaying all input and output data of the FLASH to be tested, which are acquired by the FPGA _ B, in real time;
the power module is used for supplying power for the FLASH application verification board, and the program-controlled power supply supplies power for the power module.
Preferably, the FPGA _ A is internally integrated with a FLASH controller and a controllable clock unit, the FLASH controller receives erasing, writing and reading instructions sent by the PC, the erasing and reading functions of the tested FLASH are verified accordingly, the output data of the tested FLASH is collected, whether the tested FLASH works normally or not is judged, and the judgment result is fed back to the serial port module; the controllable clock unit is an internal PLL of the FPGA _ A and is used for generating two clock frequencies, wherein one clock frequency is used for maintaining the normal work of the FPGA _ A, and the other clock frequency is used as the input clock frequency of the tested FLASH.
Preferably, the method for verifying the erasing and writing read function of the FLASH controller to the tested FLASH is as follows:
after receiving an erasing instruction sent by a PC (personal computer), the FLASH controller sends an erasing control signal and an address to a tested FLASH, and the tested FLASH executes the erasing instruction; after the execution is finished, the FLASH controller collects the data of all addresses of the tested FLASH, if the data is FF, the erasing is successful, otherwise, the erasing is failed;
after receiving a write instruction sent by a PC (personal computer), the FLASH controller sends a write control signal, input data and an address to the FLASH to be tested until all the addresses are written;
and after receiving a reading instruction sent by the PC, the FLASH controller acquires output data of a corresponding address of the tested FLASH, compares the input data with the output data, and when the reading operation is finished, if the input data and the output data are always the same, the read-write function of the tested FLASH is normal, and if the input data and the output data are not consistent, the read-write function of the tested FLASH is indicated to be abnormal.
Preferably, the implementation manner of the JTAG function of the PC verifying the tested FLASH is as follows:
the PC machine reads the pre-loaded data;
the PC reads the ID of the FLASH to be tested through the JTAG;
the PC sends an erasing instruction to the tested FLASH through the JTAG, after the tested FLASH executes the erasing instruction, the PC checks and checks the data of the corresponding address of the tested FLASH through the JTAG, if the data check is successful, the erasing is successful, otherwise, the erasing is failed;
the PC sends a write instruction to the tested FLASH through a JTAG, and the preloaded data is written into the specified address of the tested FLASH;
and the PC sends a read instruction to the tested FLASH through the JTAG, reads data from the specified address, verifies the read data and the preloaded data, and if the read data and the preloaded data are consistent, the writing and the reading are considered to be successful.
Preferably, the implementation method for verifying the memory configuration function of the tested FLASH is as follows:
the PC sends a program configuration instruction and configuration code pattern data to the tested FLASH through a JTAG, and the tested FLASH loads the configuration code pattern data; the FPGA _ A is provided with an LED lamp, and the configuration code type data is used for controlling the LED lamp to realize the marquee function;
after the tested FLASH is loaded, observing an LED lamp on the FPGA _ A to see whether the LED lamp can realize the marquee function or not, and if not, judging that the memory configuration function of the tested FLASH is abnormal; if the detected FLASH is in a power-off state, the detected FLASH is powered on again, at the moment, if the ticker function cannot be realized, the memory configuration function of the detected FLASH is abnormal, and if the ticker function can still be realized, the detected FLASH is subjected to soft reset;
after the soft reset, if the marquee function can not be realized, the memory configuration function of the tested FLASH is abnormal; if the marquee function can still be realized, the configuration function of the tested memory is normal.
Preferably, the FPGA _ B is internally integrated with a FLASH controller and a controllable clock unit, and is externally connected with the SRAM, and can send control signals, clocks, addresses and data to the SRAM and collect output data of the SRAM.
Preferably, FPGA _ B can also be used as FLASH, and the JTAG of FPGA _ A is connected with the IO port of FPGA _ B at the moment;
the PC accesses the FPGA _ B through a JTAG instruction, and downloads a test program into the FPGA _ B, and the FPGA _ B becomes a tested FLASH at the moment;
and the PC accesses the FPGA _ A through the JTAG instruction and verifies the FPGA _ B as the erasing, writing and reading functions of the tested FLASH.
Preferably, the digital logic verification of the tested FLASH can be carried out by the following method:
JTAG of FPGA _ A is connected with IO port of FPGA _ B, and FLASH to be tested is connected with IO port of FPGA _ A; marking the FPGA _ B as a false FLASH at the moment;
the PC sends an operation instruction to the FPGA _ A through the serial port module, the FPGA _ A controls the tested FLASH to execute corresponding operation according to the operation instruction, and collects real-time data of the tested FLASH and feeds the real-time data back to the PC through the serial port module;
meanwhile, the PC sends an operation instruction to the FPGA _ A through the JTAG, the FPGA _ A controls the false FLASH to execute corresponding operation according to the operation instruction, and collects real-time data of the false FLASH and feeds the real-time data back to the PC through the JTAG;
the PC machine simultaneously monitors the working states of the data end of the tested FLASH and the false FLASH in real time when working, so as to judge whether the digital logic of the tested FLASH is accurate.
Preferably, the power supply module comprises a first power supply module and a second power supply module, the first power supply module supplies power for the FPGA _ A, the serial port module and the tested FLASH, and the second power supply module supplies power for the FPGA _ B and the plug-in SRAM.
Preferably, the tested FLASH is an SPI daughter board, a NOR _ FLASH daughter board, or a PROM daughter board.
Compared with the prior art, the invention has the following beneficial effects:
the FLASH application verification board can cover the application verification of nonvolatile memories such as SPI _ FLASH, NOR _ FLASH, PROM and the like, including function verification, configuration verification and the like, solves the defect that the existing FLASH application verification board can only verify a single FLASH, and greatly improves the coverage of application verification.
The FLASH application verification board is provided with two independent FPGAs, one of the FPGA can be used as a controller, the other FPGA can be used as a processor, the working state is monitored in real time and fed back to a PC (personal computer), digital logic can be verified, and compared with a real calibration device, the FLASH application verification board is convenient for finding the design problem of a device to be verified, and the debugging process and the device maturation are accelerated.
Drawings
FIG. 1 is a schematic block diagram of a FLASH application system;
FIG. 2 is a schematic diagram of FLASH and FPGA _ A signal connection;
FIG. 3 is a schematic diagram of the connection of a FLASH daughter board to a configuration memory connector;
Detailed Description
Referring to fig. 1, the FLASH application verification system of the present invention includes a PC, a FLASH application verification board and a programmable power supply.
The FLASH application verification board comprises two FPGAs, a serial port module, a power supply module, a configuration memory connector, a JTAG, a 160Mb capacity SRAM and a tested FLASH.
The serial port module is used for connecting the PC and the FPGA _ A, sending the instruction of the PC to the FPGA _ A and feeding back the result fed back by the FPGA _ A to the PC.
The FPGA _ A is internally integrated with a FLASH controller and a controllable clock unit, the FLASH controller is connected with a tested FLASH, receives a PC instruction, sends a control signal, a clock, an address and data to the tested FLASH and acquires output data of the tested FLASH; the controllable clock unit is a PLL inside the FPGA and is used for generating two clock frequencies, and one clock frequency is used for maintaining the normal work of the FPGA. The other clock frequency is used as the input clock frequency of the tested FLASH; and judging whether the FLASH works normally according to the output data of the tested FLASH, and feeding the result back to the serial port module.
The FPGA _ B integrates a FLASH controller and a controllable clock unit, the functions all cover the FPGA _ A function, in addition, the FPGA _ B is externally connected with a 160Mb capacity SRAM, can send control signals, clocks, addresses and data to the SRAM, and can collect output data of the SRAM.
The power module takes the LTM4644 as a core device to supply power to the FPGA and the serial port module, the power supply is divided into two sets, the FPGA _ A and the FPGA _ B supply power independently and are electrified independently without mutual influence, the electrification time sequence is controlled independently, and the requirements of the electrification time sequence of the FPGA and the electrification time sequence of the FLASH to be tested are met.
The connector of the configuration memory is a configuration interface of the FPGA, an FMC connector is adopted, the connector is packaged by BGA, the characteristics of multiple interfaces, high-speed interfaces and the like are met, and the connector is used for connecting the FLASH to be tested and is used as the configuration memory.
And the PC machine uses the iMPACT software to send a JTAG instruction through a JTAG port, executes various operations on the tested FLASH and feeds back the result to the PC machine.
A PC machine: sending an instruction to the serial port module, receiving a result through the serial port, and displaying the result; sending a JTAG instruction to a JTAG, executing operation on a tested object and recording a result; and the FPGA-B uses CHIPSCOP software to perform real-time data monitoring on the working tested FLASH.
The programmable power supply supplies power to the power supply module.
According to the JTAG function of the tested FLASH, the PC sends an access instruction to the tested FLASH through the JTAG on the iMPCT software, and performs various functional operations on the tested FLASH through the JTAG. After the erasing instruction is carried out, data is verified, null checking is carried out, data null checking is successful, the successful erasing is indicated, and otherwise, the failure is carried out; and after the write operation is executed, a verification function is executed on the pre-loaded data so as to judge whether the write and the read are successful. All the execution operation results are displayed to the PC through JTAG. After the erasing and writing read functions of the tested FLASH are completed, the normal functions of the tested FLASH can be indicated only if the tested FLASH is successful. The tested data is in an MCS file format, and in order to ensure the comprehensive function of the tested FLASH, the tested data comprises special code type files such as an incremental code type, a 55AA code type, a 00 code type and the like; the tested code pattern capacity size includes a full capacity code pattern, an 1/2 capacity code pattern, a 1/4 code pattern and the like, and all JTAG functional verification is completed.
According to the configuration function verification of the tested FLASH, the PC sends an access instruction to the tested FLASH through the JTAG, configuration code type data are loaded, the data can realize the ticker function, and the tested FLASH finishes the loading of preloaded data. The working mode of the FPGA is correctly selected, the FPGA system verification board is observed, whether the marquee function can be realized or not is judged, the marquee function is powered on again after power failure, whether the marquee function can be loaded successfully or not is judged, the marquee function can still be loaded after soft reset, the configuration frequency of the tested FLASH is changed, the time for successful data loading is changed, and the configuration function verification is completed.
According to the digital logic prototype verification method, the FPGA _ A is used as a controller of the verification system to operate all the performances of the FLASH. The FPGA _ B is used as a processor of the verification system, can be used as a tested FLASH, and can also process data in real time and monitor the working state of a port.
The 160Mb SRAM is externally connected with the FPGA _ B, so that the verified data capacity can be expanded to 160Mbit, the capacity of the FPGA is not enough to support large-capacity data verification, a large-capacity memory is additionally arranged, the operation instruction of the SRAM is simple and easy to use, and therefore the 128M data can be verified by using the large-capacity SRAM, and the data can be directly expanded to a larger capacity of 256Mbit and the like in the future.
When the iMPACT software executes the function verification, the PC accesses the FPGA _ B through the JTAG instruction and downloads the test program into the FPGA _ B, the FPGA at the moment is changed into a tested FLASH, then the PC accesses the FPGA _ A through the JTAG instruction and carries out various operations on the FLASH, and the system can verify whether the erasing, writing and reading character logic functions of the FLASH are correct or not. JTAG of FPGA _ A is connected with IO port of FPGA _ B, and can monitor working state of data end of true FLASH and false FLASH in real time.
The FPGA _ B adds a control signal, can be used as a false FLASH, can also monitor various instruction operations of the FPGA _ A on the detected FLASH, observes data by using CHIPSCOP, and when a PC executes the instruction operations on the FPGA _ A, gives an instruction to a true FLASH, namely the detected FLASH is configured by adding the FPGA _ B, and simultaneously gives the instruction to the false FLASH, namely the FPGA _ B is used as the false FLASH, observes the data in real time, compares whether the digital logic of each instruction is different from a standard device or not so as to judge the accuracy of the digital logic, is convenient to find the design problem of a device to be verified, accelerates the debugging process and accelerates the maturation of the device.
FPGA _ B uses CHIPSCOP to observe data in real time, JTAG accesses instructions of Program, Erase, Blank Check, Verify and the like of FPGA _ A, uses CHIPSCOP to complete data capture of each instruction, does not ensure data integrity captured by each instruction, can add a counter in a Program, completes storage of all data in the CHIPSCOP, can trigger positioning data exception points, realizes capture error instructions and completes data storage.
Referring to fig. 2, according to the working mode of the tested FLASH, the PC sends the corresponding functional instruction to the FPGA through the serial module:
the FPGA sends a control signal, data and an address to the FLASH to be tested through the FLASH controller, and executes an erasing instruction; after the execution, the FPGA compares the data stored in all the addresses to determine whether the data is FF, if the output data is FF, the erasure is successful, and the result is fed back to the FPGA;
the FPGA sets the input clock frequency of the FLASH to be tested through the controllable clock unit, and sends a control signal, data and an address to the FLASH to be tested through the FLASH controller, wherein the input data can be an incremental code type, a 00 code type, a 55AA code type and the like until all addresses are written in;
the FPGA executes a read operation, compares input data with output data, continues to execute a program if the input data and the output data are the same, indicates that the read-write function of the tested FLASH is normal if the input data and the output data are the same all the time when the program execution is finished, and indicates that the read-write function of the tested FLASH is abnormal if the input data and the output data are inconsistent;
and the FPGA transmits the final erasing, writing and reading result to the PC through the serial port module, and the PC records and displays the result.
Referring to fig. 3, the FLASH daughter board is used to connect with the connector of the configuration memory, as the configuration memory, the FLASH daughter board has SPI, NOR _ FLASH daughter board, and there are more demands later, different types of FLASH daughter boards can be added to replace the daughter boards, different types of FLASH are verified, the universality is extremely strong, and the cost is saved.
On one hand, the tested FLASH adopts a connector mode, so that the functions of different types of FLASH can be verified, and on the other hand, the two FPGAs are adopted, each system works independently, and meanwhile, the working state of the other FPAG can be monitored in real time.
In conclusion, the invention provides a set of application verification system and method for FLASH with comprehensive verification items and strong universality.
Those skilled in the art will appreciate that the invention may be practiced without these specific details.
Claims (10)
1. A FLASH application verification system based on FPGA is characterized in that: comprises a PC, a FLASH application verification board and a program-controlled power supply;
the FLASH application verification board comprises two FPGAs, a serial port module, a power supply module, a configuration memory connector, a JTAG and an SRAM; the two FPGAs are respectively marked as FPGA _ A and FPGA _ B;
when the erasing and reading functions of the tested FLASH are verified, the tested FLASH is connected with the IO port of the FPGA _ A; when the JTAG function and the memory configuration function of the tested FLASH are verified, the tested FLASH is connected with a configuration memory connector, and the configuration memory connector is a configuration interface of the FPGA;
the serial port module is used for connecting the PC and the FPGA _ A, sending erasing, writing and reading instructions of the PC to the FPGA _ A and feeding back a result fed back by the FPGA _ A to the PC;
the FPGA _ A carries out erasing, writing and reading tests on the tested FLASH according to the erasing, writing and reading instructions of the PC, acquires the output data of the tested FLASH, judges whether the tested FLASH works normally according to the output data, and feeds back the judgment result to the serial port module;
the FPGA _ B collects all input and output data of the FLASH to be tested which is working, and sends the data to the PC through the configuration memory connector and the JTAG;
a PC machine: when the erasing and reading functions of the tested FLASH are verified, an erasing, writing and reading instruction is sent to the serial port module, and a result fed back by the FPGA _ A is received and displayed; when the JTAG function of the tested FLASH is verified, an erasing, writing and reading instruction is sent to the tested FLASH through the JTAG, and a result fed back by the tested FLASH is read and displayed through the JTAG; sending a program configuration instruction to the tested FLASH through a JTAG to verify the memory configuration function of the tested FLASH; all input and output data of the FLASH to be tested, which are acquired by the FPGA _ B, are displayed in real time;
the power module is used for supplying power for the FLASH application verification board, and the program-controlled power supply supplies power for the power module.
2. The FPGA-based FLASH application authentication system of claim 1, wherein: the FPGA _ A is internally integrated with a FLASH controller and a controllable clock unit, the FLASH controller receives erasing, writing and reading instructions sent by a PC, the erasing and reading functions of the tested FLASH are verified according to the instructions, the output data of the tested FLASH is collected, whether the tested FLASH works normally or not is judged, and the judgment result is fed back to a serial port module; the controllable clock unit is an internal PLL of the FPGA _ A and is used for generating two clock frequencies, wherein one clock frequency is used for maintaining the normal work of the FPGA _ A, and the other clock frequency is used as the input clock frequency of the tested FLASH.
3. The FPGA-based FLASH application verification system according to claim 2, wherein the method for verifying the erasing and reading functions of the FLASH controller on the tested FLASH is as follows:
after receiving an erasing instruction sent by a PC, the FLASH controller sends an erasing control signal and an address to the tested FLASH, and the tested FLASH executes the erasing instruction; after the execution is finished, the FLASH controller collects the data of all addresses of the tested FLASH, if the data is FF, the erasing is successful, otherwise, the erasing is failed;
after receiving a write instruction sent by a PC (personal computer), the FLASH controller sends a write control signal, input data and an address to the FLASH to be tested until all the addresses are written;
and after receiving a reading instruction sent by the PC, the FLASH controller acquires output data of a corresponding address of the tested FLASH, compares the input data with the output data, and when the reading operation is finished, if the input data and the output data are always the same, the read-write function of the tested FLASH is normal, and if the input data and the output data are not consistent, the read-write function of the tested FLASH is indicated to be abnormal.
4. The FPGA-based FLASH application verification system according to claim 2, wherein the implementation manner of the JTAG function of the PC for verifying the tested FLASH is as follows:
the PC machine reads the pre-loaded data;
the PC reads the ID of the FLASH to be tested through the JTAG;
the PC sends an erasing instruction to the tested FLASH through the JTAG, after the tested FLASH executes the erasing instruction, the PC checks and checks the data of the corresponding address of the tested FLASH through the JTAG, if the data check is successful, the erasing is successful, otherwise, the erasing is failed;
the PC sends a write instruction to the tested FLASH through the JTAG, and the pre-loaded data is written into the specified address of the tested FLASH;
and the PC sends a read instruction to the tested FLASH through the JTAG, reads data from the specified address, verifies the read data and the preloaded data, and if the read data and the preloaded data are consistent, the writing and the reading are considered to be successful.
5. The verification method according to claim 2, wherein the implementation method for verifying the memory configuration function of the tested FLASH is as follows:
the PC sends a program configuration instruction and configuration code pattern data to the tested FLASH through a JTAG, and the tested FLASH loads the configuration code pattern data; the FPGA _ A is provided with an LED lamp, and the configuration code type data is used for controlling the LED lamp to realize the marquee function;
after loading of the tested FLASH is finished, observing an LED lamp on the FPGA _ A to see whether the tested FLASH can realize the marquee function or not, and if not, determining that the memory configuration function of the tested FLASH is abnormal; if the detected FLASH is in a power-off state, the detected FLASH is powered on again, at the moment, if the ticker function cannot be realized, the memory configuration function of the detected FLASH is abnormal, and if the ticker function can still be realized, the detected FLASH is subjected to soft reset;
after the soft reset, if the marquee function can not be realized, the memory configuration function of the tested FLASH is abnormal; if the marquee function can still be realized, the configuration function of the tested memory is normal.
6. The FPGA-based FLASH application authentication system of claim 1, wherein: the FPGA _ B is internally integrated with a FLASH controller and a controllable clock unit, and is externally connected with the SRAM, can send control signals, clocks, addresses and data to the SRAM and can collect output data of the SRAM.
7. The FPGA-based FLASH application authentication system according to claim 6, wherein FPGA _ B can also be used as FLASH, at which time JTAG of FPGA _ A is connected to IO port of FPGA _ B;
the PC accesses the FPGA _ B through a JTAG instruction, and downloads a test program into the FPGA _ B, and the FPGA _ B becomes a tested FLASH at the moment;
and the PC accesses the FPGA _ A through the JTAG instruction and verifies the FPGA _ B as the erasing, writing and reading functions of the tested FLASH.
8. The FPGA-based FLASH application verification system of claim 7, further capable of performing tested FLASH digital logic verification, the method comprising:
JTAG of FPGA _ A is connected with IO port of FPGA _ B, and FLASH to be tested is connected with IO port of FPGA _ A; marking the FPGA _ B as a false FLASH at the moment;
the PC sends an operation instruction to the FPGA _ A through the serial port module, the FPGA _ A controls the tested FLASH to execute corresponding operation according to the operation instruction, and collects real-time data of the tested FLASH and feeds the real-time data back to the PC through the serial port module;
meanwhile, the PC sends an operation instruction to the FPGA _ A through the JTAG, the FPGA _ A controls the false FLASH to execute corresponding operation according to the operation instruction, and collects real-time data of the false FLASH and feeds the real-time data back to the PC through the JTAG;
the PC machine simultaneously monitors the working states of the data end of the tested FLASH and the false FLASH in real time when working, so as to judge whether the digital logic of the tested FLASH is accurate.
9. The FPGA-based FLASH application authentication system of claim 6, wherein: the power supply module comprises a first power supply module and a second power supply module, the first power supply module supplies power for the FPGA _ A, the serial port module and the tested FLASH, and the second power supply module supplies power for the FPGA _ B and the plug-in SRAM.
10. The FPGA-based FLASH application verification system according to claim 1, wherein: the tested FLASH is an SPI daughter board, an NOR _ FLASH daughter board or a PROM daughter board.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116520754A (en) * | 2023-06-27 | 2023-08-01 | 厦门芯泰达集成电路有限公司 | DPS module control method and system based on preloading mode |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116520754A (en) * | 2023-06-27 | 2023-08-01 | 厦门芯泰达集成电路有限公司 | DPS module control method and system based on preloading mode |
| CN116520754B (en) * | 2023-06-27 | 2023-09-22 | 厦门芯泰达集成电路有限公司 | DPS module control method and system based on preloading mode |
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