CN114664369A - Memory chip testing method and device - Google Patents
Memory chip testing method and device Download PDFInfo
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- CN114664369A CN114664369A CN202210134462.7A CN202210134462A CN114664369A CN 114664369 A CN114664369 A CN 114664369A CN 202210134462 A CN202210134462 A CN 202210134462A CN 114664369 A CN114664369 A CN 114664369A
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
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- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56008—Error analysis, representation of errors
Abstract
The invention discloses a method and a device for testing a memory chip, wherein the method comprises the following steps: acquiring an upper computer instruction, reading the type of each memory chip, respectively carrying out a first test on each first type memory chip, and respectively carrying out a second test on each second type memory chip; the first test writes test data into each address space of the memory chip and verifies the test data, reads all stored data of the memory chip after the verification is passed and compares the stored data with the test data, and if the comparison results are consistent, the test is passed; and the second test firstly erases the target memory chip, then writes test data into each address space of the memory chip and verifies the test data, reads all stored data of the memory chip after the verification is passed and compares the stored data with the test data, and if the comparison results are consistent, the test is passed. The invention can automatically complete the full-disk test of the memory chip, adopts a double judgment mechanism to improve the reliability of the test result, and can report the test progress and the test result in real time.
Description
Technical Field
The invention relates to the field of memory chip detection, in particular to a memory chip testing method and device.
Background
The memory chip is used for storing important information such as user programs, data and even keys. The existing manufacturing process can not ensure that all produced memory chips can work normally, a part of defective memory chips also flow into the market, and the application of the defective memory chips in the working production can cause serious consequences such as abnormal program operation, data failure and even system paralysis. Therefore, before using the memory chips, it is necessary to perform a full disk test to ensure that the memory chips to be used can operate normally.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides a method and a device for testing memory chips, which can test various types of memory chips, can effectively locate and report fault points, and provide reliable basis for solving the faults in the later period.
In order to solve the technical problems, the technical scheme provided by the invention is as follows:
a memory chip testing method is applied to a memory chip testing device, the memory chip testing device comprises an upper computer and a DSP unit which are connected with each other, the DSP unit is connected with at least two tested memory chips, the method comprises the step of testing the memory chips by the DSP unit, and specifically comprises the following steps:
acquiring and analyzing an upper computer instruction, and reading hardware information of each storage chip to obtain the type of each storage chip if the upper computer instruction is used for starting a test;
if the first type of memory chips exist, respectively performing a first test on each first type of memory chip, wherein the first test comprises the following steps: sequentially writing test data into the space of each address of a target storage chip and verifying the test data, if the address which fails to pass the verification exists, generating a test result of a test error by the information of the address, reporting the test result to an upper computer, if each address passes the verification, reading all stored data of the target storage chip and comparing the stored data with the corresponding test data, if the stored data is inconsistent with the corresponding test data, generating the test result of the test error by the information of the address corresponding to the stored data, reporting the test result to the upper computer, and if all the stored data is consistent with the corresponding test data, reporting the test result which passes the test to the upper computer;
if the second type of memory chip exists, respectively performing a second test on each second type of memory chip, wherein the second test comprises the following steps: and erasing the target memory chip, writing test data into the space of each address of the target memory chip in sequence and verifying, if the address which fails to pass the verification exists, generating a test result with a test error according to the information of the address, reporting the test result to the upper computer, if each address passes the verification, reading all stored data of the target memory chip and comparing the stored data with the corresponding test data, if the stored data is inconsistent with the corresponding test data, generating the test result with the test error according to the information of the address corresponding to the stored data, reporting the test result to the upper computer, and if all the stored data are consistent with the corresponding test data, reporting the test result which passes the test to the upper computer.
Further, the step of writing test data into the space of each address of the target memory chip in sequence and verifying specifically includes:
selecting current data as test data, and taking the space of the current address of the target memory chip as the space of the target address;
writing the test data into the space of the target address, reading the stored data in the space of the target address within preset time, if the stored data is the same as the test data, passing the verification, executing the next step, if the stored data is different from the test data, failing the verification, recording the target address, generating a test result of a test error by using the information of the address, and reporting the test result to an upper computer;
and taking the next data as test data, taking the space of the next address of the target memory chip as the space of the target address when the next data is different from the current data, and returning to the previous step until the space of the address of the target memory chip is traversed completely.
Further, before the next data is used as the test data, the method includes a step of obtaining the next data, which specifically includes: and self-adding one to the value of the current data to obtain the next data.
Further, if the stored data is the same as the test data, the test data is also stored in the first data set; the step of reading all stored data of the memory chip and comparing the stored data with corresponding written data specifically comprises:
reading corresponding saved data from the space of all the addresses of the target memory chip and saving the corresponding saved data to a second data set;
selecting stored data from the second data set, and matching corresponding test data from the first data set according to the address corresponding to the stored data;
comparing the stored data with the corresponding test data, and if the stored data is the same as the corresponding test data, executing the step of selecting the stored data from the second data set until the stored data in the second data set is selected; and if the stored data is different from the corresponding test data, generating a test result of a test error by using the information of the address corresponding to the stored data, and reporting the test result to the upper computer.
Further, the method also comprises the following steps after the target memory chip is erased: if the erasure is successful, the steps of writing test data into the space of each address of the memory chip in sequence and verifying are executed, and if the erasure is failed, the test result of the erasure failure is reported to the upper computer.
Further, the method also comprises the step of interaction between the upper computer and the DSP unit, and specifically comprises the following steps:
generating an upper computer instruction for starting a test, and sending the upper computer instruction to a DSP unit;
waiting and acquiring a test result reported by the DSP unit, and marking that the corresponding memory chip passes the test if the test result is passed; if the test result is a test error, marking that the corresponding memory chip fails to pass the test, and recording address information in the test result; and if the information is the notice of the erasure failure, marking the erasure failure of the corresponding memory chip.
Further, the step of host computer and DSP unit interaction still includes: generating an upper computer instruction for stopping testing and sending the upper computer instruction to the DSP unit;
the step of testing the memory chip by the DSP unit further comprises: and acquiring and analyzing the instruction of the upper computer, and if the instruction is to stop the test, ending and exiting.
The invention also provides a memory chip testing device, which comprises a DSP unit, a bridging unit, a communication unit and an upper computer which are connected in sequence, wherein the DSP unit is also connected with at least two tested memory chips, and the testing device comprises:
the upper computer is used for generating an upper computer instruction for starting a test, sending the upper computer instruction to the DSP unit through the communication unit, waiting for and acquiring a test result reported by the DSP unit through the communication unit, and marking that the corresponding memory chip passes the test if the test result is passed; if the test result is a test error, marking that the corresponding memory chip fails to pass the test, and recording address information in the test result; if the memory chip is notified of the erasure failure, marking the erasure failure of the corresponding memory chip;
the communication unit is used for issuing the instruction of the upper computer to the DSP unit through the bridge unit, acquiring the test result reported by the DSP unit through the bridge unit and reporting the test result reported by the DSP unit to the upper computer;
the DSP unit is used for acquiring and analyzing an upper computer instruction through the communication unit, if the test is started, corresponding tests are respectively carried out according to the types of the storage chips, if the type of the storage chip is a first type, test data are written into the space of each address of the storage chip in sequence and verified, if the type of the storage chip is a second type, after the storage chip is erased, if the erasure is successful, the step of writing the test data into the space of each address of the storage chip in sequence and verified is carried out, and if the erasure is failed, the test result of the erasure failure is reported to the upper computer through the bridging unit and the communication unit in sequence; after test data are written into the space of each address of the memory chip in sequence and verified, if an address which cannot be verified exists, generating a test result of a test error by the information of the address, and reporting the test result to an upper computer through a bridging unit and a communication unit in sequence; if each address passes the verification, reading all stored data of the memory chip and comparing the stored data with corresponding test data, if the stored data is inconsistent with the corresponding test data, generating a test result of a test error by the information of the address corresponding to the stored data, and reporting the test result to the upper computer through the bridging unit and the communication unit in sequence; and if all the stored data are consistent with the corresponding test data, reporting the test result passing the test to the upper computer through the bridging unit and the communication unit in sequence.
Further, when the test data is written into the space of each address of the target memory chip in sequence and verified, the DSP unit is specifically configured to:
selecting current data as test data, and taking the space of the current address of the memory chip as the space of a target address;
writing the test data into the space of the target address, reading the stored data in the space of the target address within preset time, if the stored data is the same as the test data, passing the verification, selecting the next data as the test data, and if the next data is different from the current data, taking the space of the next address of the target memory chip as the space of the target address, executing the step of writing the test data into the space of the target address until the space traversal of the address of the target memory chip is finished, if the stored data is different from the test data, failing the verification, recording the target address, executing the step of generating a test result with the address information to be a test error, and reporting the test result to an upper computer.
Further, the DSP unit is further configured to store the test data to the first data set when the stored data and the test data are the same, and when all stored data of the memory chip are read and compared with corresponding write data, the DSP unit is specifically configured to:
reading corresponding saved data from the space of all the addresses of the memory chip and saving the corresponding saved data to a second data set;
selecting stored data from the second data set, and matching corresponding test data from the first data set according to the address corresponding to the stored data;
comparing the stored data with the corresponding test data, and if the stored data is the same as the corresponding test data, executing the step of selecting the stored data from the second data set until the stored data in the second data set is selected; and if the stored data is different from the corresponding test data, generating a test result of a test error by using the information of the address corresponding to the stored data, and reporting the test result to the upper computer.
Compared with the prior art, the invention has the advantages that:
the invention can automatically complete the full-disk test of the memory chip, adopts a double judgment mechanism, verifies after writing data into the space of each address of the target memory chip for the first time to determine whether the write operation is normal, reads all data of the target memory chip for the second time and compares the data with the corresponding write data to determine whether the read operation is normal, thereby improving the reliability of the test result. In addition, the invention can report the test progress and the test result of each memory chip in real time, thereby facilitating a user to know the test progress and accurately knowing the fault reason and the fault position of the memory chip which fails to be tested.
Drawings
Fig. 1 is a functional logic relationship block diagram of a memory chip testing apparatus according to a first embodiment of the present invention.
Fig. 2 is a functional diagram of a DSP unit according to a first embodiment of the present invention.
Fig. 3 is an overall flowchart of testing the memory chip by the DSP unit according to an embodiment of the present invention.
FIG. 4 is a flowchart illustrating the testing of the EEPROM chip by the DSP unit according to an embodiment of the present invention.
Fig. 5 is a flowchart of testing a Flash chip by the DSP unit in the first embodiment of the present invention.
Fig. 6 is an overall flowchart of testing the memory chip by the DSP unit according to the third embodiment of the present invention.
Detailed Description
The invention is further described below with reference to the drawings and specific preferred embodiments of the description, without thereby limiting the scope of protection of the invention.
Example one
As shown in fig. 1, the present embodiment provides a memory chip testing apparatus, which includes a DSP unit, a bridging unit, a communication unit, and an upper computer, which are sequentially connected, where the DSP unit is further connected with at least two tested memory chips, where the tested memory chips may be the same type of memory chip, such as all EEPROM memory chips or all Flash memory chips, or different types of memory chips, such as part of the EEPROM memory chips and another part of the Flash memory chips, the DSP unit provides corresponding data read/write interfaces for each tested memory chip, and considers that the tested memory chips are mounted on other devices later, therefore, in this embodiment, each tested memory chip is configured with a corresponding chip socket, so that the tested memory chips can be mounted on the chip socket in a detachable connection manner such as a plug-in connection, and each read-write interface of the DSP unit is connected with the corresponding chip holder, and data read-write is carried out through each chip holder and the corresponding storage chip.
In the DSP unit in this embodiment, the DSP chip employs an FT-C6416 processor and is configured to perform a test function, a drive configuration function, and a serial port communication function, where the test function mainly includes testing an EEPROM memory chip and a Flash memory chip, respectively, as shown in fig. 2, the drive configuration function mainly includes configuring interfaces provided by the EEPROM memory chip and the Flash memory chip, and the serial port communication function mainly includes receiving an instruction of an upper computer and reporting a detection result, and a configuration process of the drive configuration function and the serial port communication function is not an important point in the scheme of this embodiment, and is not described herein again.
The bridge unit of the present embodiment employs a CPLD, the communication unit employs an ST16C554QFP64 chip, the CPLD communicates with the DSP unit via the EMIF bus, and communicates with ST16C554QFP64 via the bus defined by ST16C554QFP64, thereby bridging the DSP unit and ST16C554QFP 64. ST16C554QFP64 communicates with the upper computer through RS232-C interface, communicates with DSP unit through the bridge connection of CPLD, thus issue the upper computer order to DSP unit through CPLD, still obtain the test result that DSP unit reports through CPLD, and report the test result that DSP unit reports to the upper computer.
In the implementation, the upper computer is used for generating an upper computer instruction for starting the test, sending the upper computer instruction to the DSP unit through the communication unit, waiting for the test result reported by the DSP unit and acquiring the test result through the communication unit, and marking that the corresponding memory chip passes the test if the test result is passed; if the test result is a test error, marking that the corresponding memory chip fails to pass the test, and recording address information in the test result; if the memory chip is notified of the erasure failure, marking the erasure failure of the corresponding memory chip;
in this embodiment, the DSP unit is configured to obtain and analyze an instruction of the upper computer through the communication unit, perform a corresponding test according to a type of each memory chip if the test is a start test, perform a test on the EEPROM memory chip if the type of the memory chip is the EEPROM memory chip (hereinafter referred to as a first type), perform a test on the Flash memory chip if the type of the memory chip is the Flash memory chip (hereinafter referred to as a second type), and report a corresponding test result to the upper computer after testing each memory chip sequentially through the bridge unit and the communication unit, so as to report a test progress and a test result of each memory chip in real time, and a user can know a test progress conveniently.
In this embodiment, the scheme for testing the EEPROM memory chip is as follows: writing single byte data into the address space appointed by the EEPROM memory chip in sequence, reading data from the appointed address space within the appointed number of read operations, judging whether the read-write data of each address space are the same to determine whether the write operations of the memory chip are normal, if the read data and the corresponding write data are the same within the appointed number of read operations, reading the data in all the appointed address spaces, and comparing the data with the corresponding write data one by one to determine whether the read operations of the memory chip are normal.
In this embodiment, the scheme for testing the Flash memory chip is as follows: erasing the Flash memory chip, then sequentially writing single byte data into the address space designated by the Flash memory chip, reading data from the designated address space within the specified read operation times, judging whether the read-write data of each address space are the same, so as to determine whether the write operation of the memory chip is normal, if the read-out data and the corresponding write-in data of each address space are the same within the specified read operation times, reading the data in all the designated address spaces, and comparing the data with the corresponding write-in data one by one, so as to determine whether the read operation of the memory chip is normal.
The scheme for testing the EEPROM memory chip is basically the same as that for testing the Flash memory chip, but the difference is that the Flash memory chip needs to be erased when the test is started.
Thus, in this embodiment, the DSP unit is configured to perform:
if the type of the memory chip is a first type, sequentially executing a step of verifying within preset times after writing test data into the space of the address aiming at each address of the memory chip, if the type of the memory chip is a second type, erasing the memory chip, and then sequentially executing a step of verifying within preset times after writing test data into the space of the address aiming at each address of the memory chip if the erasing is successful, and if the erasing is failed, reporting a test result of the erasing failure to an upper computer sequentially through a bridging unit and a communication unit;
for each address of the memory chip, after the step of verifying the space of the address after writing test data into the space of the address within preset times is sequentially executed, if an address which fails to be verified exists, generating a test result of a test error by the information of the address which fails to be verified, and reporting the test result to an upper computer through a bridging unit and a communication unit in sequence;
if each address passes the verification, reading all stored data of the memory chip and comparing the stored data with corresponding test data, if the stored data is inconsistent with the corresponding test data, generating a test result of a test error by the information of the address corresponding to the stored data, and reporting the test result to the upper computer through the bridging unit and the communication unit in sequence;
and if all the stored data are consistent with the corresponding test data, reporting the test result passing the test to the upper computer sequentially through the bridging unit and the communication unit.
In this embodiment, when the step of verifying the space of the address within the preset number of times after writing the test data into the space of the address is sequentially performed for each address of the memory chip, the DSP unit is specifically configured to:
selecting current data as test data, and taking the space of the current address of the memory chip as the space of a target address;
writing the test data into the space of the target address, reading the stored data in the space of the target address within a preset time, if the stored data is the same as the test data, passing the verification, selecting the next data as the test data, and the next data is different from the current data, using the space of the next address of the target memory chip as the space of the target address, executing the step of writing the test data into the space of the target address until the space traversal of the address of the target memory chip is completed, if the stored data is different from the test data and the space reading frequency of the corresponding target address does not reach a preset threshold value, executing the step of reading the stored data in the space of the target address within the preset time, if the space reading frequency of the corresponding target address reaches the preset threshold value, failing the verification, and using the corresponding target address as the address which does not pass the verification, and executing the step of generating a test result of the test error by the information of the address which fails to pass the verification, and reporting the test result to the upper computer.
In this embodiment, the DSP unit is further configured to store the test data to the first data set when the stored data and the test data are the same, and when all stored data of the memory chip are read and compared with corresponding write data, the DSP unit is specifically configured to:
reading corresponding stored data from the space of all the addresses of the memory chip and storing the corresponding stored data in a second data set;
selecting stored data from the second data set, and matching corresponding test data from the first data set according to the address corresponding to the stored data;
comparing the stored data with the corresponding test data, and if the stored data is the same as the corresponding test data, executing the step of selecting the stored data from the second data set until the stored data in the second data set is selected; and if the stored data is different from the corresponding test data, generating a test result of a test error by using the information of the address corresponding to the stored data, and reporting the test result to the upper computer.
As shown in fig. 3, based on the memory chip testing apparatus of this embodiment, this embodiment further provides a memory chip testing method, including a step of testing a memory chip by a DSP unit, which specifically includes:
s1) acquiring and analyzing the upper computer instruction, and reading the hardware information of each storage chip to obtain the type of each storage chip if the upper computer instruction is used for starting the test;
s2) if there are first type memory chips, respectively performing an EEPROM memory chip test for each first type memory chip, the EEPROM memory chip test including: for each address of a target storage chip, sequentially writing test data into the space of the address, verifying the test data within preset times, if the address fails to pass the verification, generating a test result of a test error by using information of the address which fails the verification, reporting the test result to an upper computer, if each address passes the verification, reading all stored data of the target storage chip, comparing the stored data with corresponding test data, if the stored data is inconsistent with the corresponding test data, generating a test result of the test error by using the information of the address corresponding to the stored data, reporting the test result of the test error to the upper computer, and if all the stored data is consistent with the corresponding test data, reporting the test result of the test passing to the upper computer;
s3) if the second type of memory chip exists, respectively testing the Flash memory chip aiming at each second type of memory chip, wherein the testing of the Flash memory chip comprises the following steps: erasing a target memory chip, writing test data into the space of the address in sequence aiming at each address of the target memory chip, then verifying the test data within preset times, if the address which fails to pass the verification exists, generating a test result of a test error according to the information of the address which fails to pass the verification, reporting the test result to an upper computer, if each address passes the verification, reading all stored data of the target memory chip and comparing the stored data with the corresponding test data, if the stored data is inconsistent with the corresponding test data, generating the test result of the test error according to the information of the address which corresponds to the stored data, reporting the test result to the upper computer, and if all the stored data are consistent with the corresponding test data, reporting the test result which passes the test to the upper computer.
Through the steps, the DSP unit performs unified test on the same type of memory chips, the memory chip test adopts a dual judgment mechanism, test data is written into the space of each address of the target memory chip for the first time and then verified within preset times to determine whether the write operation is normal, all stored data of the target memory chip are read for the second time and compared with the corresponding test data to determine whether the read operation is normal, the embodiment verifies the write operation and the read operation respectively, and therefore the reliability of the test result is improved. In addition, the test progress and the test result of each memory chip are reported in real time, so that a user can know the test progress conveniently, and the fault reason and the fault position of the memory chip which fails in the test can be accurately known.
As shown in fig. 4, in this embodiment, the target memory chip of the first type, i.e. the EEPROM memory chip, is tested by taking a domestic chip JM28LV256 as an example, and the capacity is 256Kb, and 8-bit data to be written into the EEPROM is initialized before the test, and the data is an integer starting from 0 and stepping by 1. The DSP unit accesses the corresponding EEPROM through an EMIF bus, and the logic address range allocated to the EEPROM is 0x 60000000-0 x 60040000. Firstly, writing a digital 0 in 0x60000000, reading data from 0x60000000 within a specified reading operation frequency, judging whether the data is 0, if not, judging that the address space 0x60000000 has a writing test error, reporting a test result of the test error to an upper computer, and then finishing the test of the EEPROM; if the number is 0, writing a number 1 in 0x60000001, then performing read-write judgment according to the same method, and repeating the steps until all the space write tests of 0x 60000000-0 x60040000 pass or the address with the write test error occurs, if all the space write tests pass, reading the data of all the spaces of 0x 60000000-0 x60040000 at one time, judging whether the read data and the corresponding written data are equal one by one, and if the read data and the corresponding written data are equal, judging that the EEPROM test passes. Otherwise, the corresponding address space of the EEPROM is considered to be read and tested wrongly.
As shown in fig. 5, in this embodiment, the target memory chip of the second type, i.e. the Flash memory chip, is tested with a capacity of 16Mb, taking a domestic chip CX29LV160 as an example. Before testing, the Flash chip needs to be erased, and then 8-bit data to be written into Flash is initialized, wherein the data are integers starting from 0 and taking 1 as a step. The DSP unit accesses the corresponding Flash through the EMIF bus, and the logic address range allocated to the Flash is 0x 64000000-0 x 65000000. Firstly, writing a number 0 in 0x64000000, then reading data from 0x64000000 within the specified read operation times, judging whether the data is 0, if not, judging that the address space is 0x64000000 write test errors, reporting the test results of the test errors to an upper computer, and then finishing the test on the Flash; if the number is 0, writing a number 1 in 0x64000001, then performing read-write judgment according to the same method, and repeating the steps until all the space write tests of 0x 64000000-0 x65000000 pass or the address with the write test error occurs, if all the space write tests pass, reading the data of all the spaces 0x 64000000-0 x65000000 at one time, judging whether the read data and the corresponding written data are equal one by one, and if the read data and the corresponding written data are equal, judging that the Flash test passes. Otherwise, the corresponding address space of Flash is considered as a read test error.
Therefore, the step of verifying within the preset number of times after writing the test data to the space of the address in sequence for each address of the target memory chip in the step S2) and the step S3) specifically includes:
selecting current data as test data, and taking the space of the current address of the target memory chip as the space of the target address;
writing the test data into the space of the target address, reading the stored data in the space of the target address within preset time, if the stored data is the same as the test data, passing the verification, and executing the following steps:
the method comprises the steps of obtaining next data by adding one to the value of the current data to enable the next data to be different from the current data, selecting the next data as test data, taking the space of the next address of a target memory chip as the space of a target address, and executing the step of writing the test data into the space of the target address until the space traversal of the address of the target memory chip is completed;
if the stored data is different from the test data, executing the following steps:
if the space reading times of the corresponding target address do not reach a preset threshold value, a step of reading the stored data in the space of the target address within preset time is executed, if the space reading times of the corresponding target address reach the preset threshold value, the verification is failed, the corresponding target address is used as the address which does not pass the verification, a test result of a test error is generated by the information of the address which does not pass the verification, and the test result is reported to an upper computer.
In this embodiment, if the stored data is the same as the test data, the test data is also stored in the first data set; the step of reading all the stored data of the memory chip and comparing the stored data with the corresponding written data specifically comprises:
reading corresponding saved data from all address spaces of the target memory chip and saving the corresponding saved data to a second data set;
selecting stored data from the second data set, and matching corresponding test data from the first data set according to the address corresponding to the stored data;
comparing the stored data with the corresponding test data, and if the stored data is the same as the corresponding test data, executing the step of selecting the stored data from the second data set until the stored data in the second data set is selected; and if the stored data is different from the corresponding test data, generating a test result of a test error by using the information of the address corresponding to the stored data, and reporting the test result to the upper computer.
Step S3) of this embodiment, after erasing the target memory chip, the method further includes the following steps: if the erasure is successful, the steps of writing test data into the space of each address of the memory chip in sequence and verifying are executed, if the erasure is failed, the test result of the erasure failure is reported to the upper computer, and because the Flash memory chip of the erasure failure is bound to the memory chip with defects, the detection of the Flash memory chip of the erasure failure is skipped, so that the test time is saved.
The memory chip testing method of the embodiment further comprises the step of interaction between the upper computer and the DSP unit, and specifically comprises the following steps:
1) generating an upper computer instruction for starting a test, and sending the upper computer instruction to a DSP unit;
2) waiting and obtaining a test result reported by the DSP unit, and marking that the corresponding memory chip passes the test if the test result is passed; if the test result is a test error, marking that the corresponding memory chip fails to pass the test, and recording address information in the test result; and if the information is the notice of the erasure failure, marking the erasure failure of the corresponding memory chip.
In this embodiment, in order to control the start and stop of the memory chip test, the step of the interaction between the upper computer and the DSP unit further includes: generating an upper computer instruction for stopping testing and sending the upper computer instruction to the DSP unit;
the step of testing the memory chip by the DSP unit further comprises: and acquiring and analyzing the instruction of the upper computer, and if the instruction is to stop the test, ending and exiting.
Example two
The present embodiment is basically the same as the first embodiment, except that in the method for testing a memory chip of the present embodiment, the upper computer instruction generated by the upper computer may further include types of the memory chips to be tested, which are input by an operator, so that when the DSP unit tests the memory chips, the memory chips of the same type may be uniformly processed under the condition that the types of the memory chips are determined, so as to save the testing time, where the step of testing the memory chips by the DSP unit specifically includes:
A1) acquiring and analyzing an upper computer instruction, and if the upper computer instruction is a starting test, acquiring the type of each storage chip in the upper computer instruction;
A2) if the first type of memory chips exist, respectively testing the EEPROM memory chips aiming at all the first type of memory chips;
A3) and if the second type of memory chip exists, respectively testing the Flash memory chips aiming at all the second type of memory chips.
The test of the EEPROM memory chip in the embodiment is the same as that of the first embodiment, namely, for each address of a target memory chip, test data is written into the space of the address in sequence and then verified within preset times, if the address which fails to be verified exists, the information of the address which fails to be verified is generated into a test result with a test error and reported to an upper computer, if each address passes verification, all stored data of the target memory chip are read and compared with corresponding test data, if the stored data is inconsistent with the corresponding test data, the information of the address corresponding to the stored data is generated into the test result with the test error and reported to the upper computer, and if all the stored data are consistent with the corresponding test data, the test result which passes the test is reported to the upper computer.
The Flash memory chip test in this embodiment is the same as the first embodiment, that is, a target memory chip is erased, test data is sequentially written into a space of the address for each address of the target memory chip and then verified within a preset number of times, if an address which fails to be verified exists, information of the address which fails to be verified is generated into a test result of a test error and reported to an upper computer, if each address passes verification, all stored data of the target memory chip are read and compared with corresponding test data, if the stored data are inconsistent with the corresponding test data, the information of the address corresponding to the stored data are generated into a test result of the test error and reported to the upper computer, and if all the stored data are consistent with the corresponding test data, the test result which passes the test is reported to the upper computer.
EXAMPLE III
The embodiment is basically the same as the first embodiment, except that in order to improve the real-time reporting of the test result, in the method for testing a memory chip of the embodiment, the step of testing the memory chip by the DSP unit does not need to determine the test sequence according to the type of the memory chip to be tested, and as shown in fig. 6, the method specifically includes the following steps:
B1) acquiring and analyzing an upper computer instruction, and if the upper computer instruction is a starting test, executing a step B2);
B2) selecting a target memory chip from each memory chip, reading the hardware parameter of the target memory chip to obtain the type of the target memory chip, if the type of the target memory chip is a first type, executing the step B3), and if the type of the target memory chip is a second type, erasing the target memory chip and then executing the step B3);
B3) for each address of a target memory chip, sequentially writing test data into the space of the address, verifying the test data within preset times, if the address fails to pass the verification, generating a test result of a test error according to the information of the address which fails the verification, reporting the test result to an upper computer, and then executing a step B4), if each address passes the verification, reading all stored data of the target memory chip and comparing the stored data with the corresponding test data, if the stored data is inconsistent with the corresponding test data, generating a test result of the test error according to the information of the address corresponding to the stored data, reporting the test result to the upper computer, and then executing a step B4), if all the data pass the verification, reporting the test result of the test to the upper computer;
B4) and returning to the step B2) until all the memory chips are selected.
The steps are suitable for the condition that the number of the tested memory chips is small and the types of the tested memory chips are different, for example, only one EEPROM memory chip and one Flash memory chip are used, in the condition, the test of each memory chip is executed in sequence, the test result is reported in real time, the test sequence is not required to be determined according to the types of the memory chips, the real-time performance of the test is improved, and the complexity of the test program is also reduced.
In step B2), the method further includes the following steps after erasing the target memory chip: and if the erasure is successful, executing the step B3), if the erasure is failed, reporting the test result of the erasure failure to the upper computer, and executing the step B4), thereby skipping over the Flash memory chip of the erasure failure and detecting the next target memory chip so as to save the test time.
The foregoing is considered as illustrative of the preferred embodiments of the invention and is not to be construed as limiting the invention in any way. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention should fall within the protection scope of the technical scheme of the present invention, unless the technical spirit of the present invention departs from the content of the technical scheme of the present invention.
Claims (10)
1. The memory chip testing method is characterized by being applied to a memory chip testing device, wherein the memory chip testing device comprises an upper computer and a DSP unit which are connected with each other, the DSP unit is connected with at least two tested memory chips, the method comprises the step of testing the memory chips by the DSP unit, and the method specifically comprises the following steps:
acquiring and analyzing an upper computer instruction, and reading hardware information of each storage chip to obtain the type of each storage chip if the upper computer instruction is used for starting a test;
if the first type of memory chips exist, respectively performing a first test on each first type of memory chip, wherein the first test comprises the following steps: sequentially writing test data into the space of each address of a target memory chip, verifying the test data within preset times, if the address which fails to pass the verification exists, generating a test result with a test error according to the information of the address which fails the verification, reporting the test result to an upper computer, if each address passes the verification, reading all stored data of the target memory chip, comparing the stored data with the corresponding test data, if the stored data is inconsistent with the corresponding test data, generating a test result with a test error according to the information of the address corresponding to the stored data, reporting the test result which passes the test to the upper computer, and if all the stored data are consistent with the corresponding test data, reporting the test result to the upper computer;
if the second type of memory chip exists, respectively performing a second test on each second type of memory chip, wherein the second test comprises the following steps: erasing a target memory chip, writing test data into the space of each address of the target memory chip in sequence, then verifying within preset times, if the address which fails to pass the verification exists, generating a test result of a test error by the information of the address which fails to pass the verification, reporting the test result to an upper computer, if each address passes the verification, reading all stored data of the target memory chip and comparing the stored data with the corresponding test data, if the stored data is inconsistent with the corresponding test data, generating a test result of the test error by the information of the address which corresponds to the stored data, reporting the test result which passes the test to the upper computer, and if all the stored data are consistent with the corresponding test data, reporting the test result to the upper computer.
2. The memory chip testing method of claim 1, wherein the step of verifying within the preset number of times after writing the test data in the space of each address of the target memory chip in sequence specifically comprises:
selecting current data as test data, and taking the space of the current address of the target memory chip as the space of the target address;
writing the test data into the space of the target address, reading the stored data in the space of the target address within preset time, if the stored data is the same as the test data, passing the verification, and executing the following steps:
taking the next data as test data, taking the space of the next address of the target memory chip as the space of the target address, and executing the step of writing the test data into the space of the target address until the space traversal of the address of the target memory chip is finished, wherein the next data is different from the current data;
if the stored data is different from the test data, executing the following steps:
if the space reading times of the corresponding target addresses do not reach the preset threshold value, executing a step of reading the stored data in the space of the target addresses within the preset time, if the space reading times of the corresponding target addresses reach the preset threshold value, the verification fails, taking the corresponding target addresses as the addresses which fail to verify, executing a step of generating test results of test errors by using the information of the addresses which fail to verify, and reporting the test results to the upper computer.
3. The method for testing the memory chip according to claim 2, wherein the step of obtaining the next data before the next data is used as the test data specifically comprises: and self-adding one to the value of the current data to obtain the next data.
4. The method of claim 2, wherein if the stored data is the same as the test data, further storing the test data in a first data set; the step of reading all stored data of the memory chip and comparing the stored data with corresponding written data specifically comprises:
reading corresponding saved data from the space of all the addresses of the target memory chip and saving the corresponding saved data to a second data set;
selecting stored data from the second data set, and matching corresponding test data from the first data set according to the address corresponding to the stored data;
comparing the stored data with the corresponding test data, and if the stored data is the same as the corresponding test data, executing the step of selecting the stored data from the second data set until the stored data in the second data set is selected; and if the stored data is different from the corresponding test data, generating a test result of a test error by using the information of the address corresponding to the stored data, and reporting the test result to the upper computer.
5. The method for testing a memory chip according to claim 1, further comprising the steps of, after erasing the target memory chip: if the erasure is successful, the steps of writing test data into the space of each address of the storage chip in sequence and verifying are executed, and if the erasure fails, the test result of the erasure failure is reported to the upper computer.
6. The memory chip testing method of claim 1, further comprising the step of interaction between the upper computer and the DSP unit, specifically comprising:
generating an upper computer instruction for starting a test, and sending the upper computer instruction to a DSP unit;
waiting and obtaining a test result reported by the DSP unit, and marking that the corresponding memory chip passes the test if the test result is passed; if the test result is a test error, marking that the corresponding memory chip fails to pass the test, and recording address information in the test result; and if the information is the notice of the erasure failure, marking the erasure failure of the corresponding memory chip.
7. The memory chip testing method of claim 6, wherein the step of the upper computer and the DSP unit interacting further comprises: generating an upper computer instruction for stopping testing and sending the upper computer instruction to the DSP unit;
the step of testing the memory chip by the DSP unit further comprises: and acquiring and analyzing the instruction of the upper computer, and if the instruction is to stop the test, ending and exiting.
8. The utility model provides a memory chip testing arrangement which characterized in that, is including the DSP unit, bridging unit, communication unit and the host computer that connect gradually, the DSP unit still is connected with two at least memory chips that are tested, wherein:
the upper computer is used for generating an upper computer instruction for starting a test, sending the upper computer instruction to the DSP unit through the communication unit, waiting for and acquiring a test result reported by the DSP unit through the communication unit, and marking that the corresponding memory chip passes the test if the test result is passed; if the test result is a test error, marking that the corresponding memory chip fails to pass the test, and recording address information in the test result; if the memory chip is notified of the erasure failure, marking the erasure failure of the corresponding memory chip;
the communication unit is used for issuing an upper computer instruction to the DSP unit through the bridge unit, acquiring a test result reported by the DSP unit through the bridge unit and reporting the test result reported by the DSP unit to the upper computer;
the DSP unit is used for acquiring and analyzing instructions of the upper computer through the communication unit, if the testing is started, corresponding testing is respectively carried out according to the type of each memory chip, if the type of the memory chip is a first type, test data are written into the space of each address of the memory chip in sequence and then verified within preset times, if the type of the memory chip is a second type, after the memory chip is erased, if the erasing is successful, the step of verifying within the preset times after the test data are written into the space of each address of the memory chip in sequence is executed, and if the erasing is failed, the test result of the erasing failure is reported to the upper computer through the bridging unit and the communication unit in sequence; after test data are written into the space of each address of the memory chip in sequence and are verified within preset times, if an address which fails to pass the verification exists, generating a test result of a test error by the information of the address which fails to pass the verification, and reporting the test result to an upper computer through a bridging unit and a communication unit in sequence; if each address passes the verification, reading all stored data of the memory chip and comparing the stored data with corresponding test data, if the stored data is inconsistent with the corresponding test data, generating a test result of a test error by the information of the address corresponding to the stored data, and reporting the test result to the upper computer through the bridging unit and the communication unit in sequence; and if all the stored data are consistent with the corresponding test data, reporting the test result passing the test to the upper computer sequentially through the bridging unit and the communication unit.
9. The memory chip testing device of claim 8, wherein when the space of each address of the target memory chip is verified within a preset number of times after the test data is written in sequence, the DSP unit is specifically configured to:
selecting current data as test data, and taking the space of the current address of the memory chip as the space of a target address;
writing the test data into the space of the target address, reading the stored data in the space of the target address within a preset time, if the stored data is the same as the test data, passing the verification, selecting the next data as the test data, and the next data is different from the current data, using the space of the next address of the target memory chip as the space of the target address, executing the step of writing the test data into the space of the target address until the space traversal of the address of the target memory chip is completed, if the stored data is different from the test data and the space reading frequency of the corresponding target address does not reach a preset threshold value, executing the step of reading the stored data in the space of the target address within the preset time, if the space reading frequency of the corresponding target address reaches the preset threshold value, failing the verification, and using the corresponding target address as the address which does not pass the verification, and executing the step of generating a test result of the test error by the address information and reporting the test result to the upper computer.
10. The memory chip testing device of claim 8, wherein the DSP unit is further configured to store the test data to a first data set when the stored data and the test data are the same, and when all stored data of the memory chip are read and compared with corresponding write data, the DSP unit is specifically configured to:
reading corresponding saved data from the space of all the addresses of the memory chip and saving the corresponding saved data to a second data set;
selecting stored data from the second data set, and matching corresponding test data from the first data set according to the address corresponding to the stored data;
comparing the stored data with the corresponding test data, and if the stored data is the same as the corresponding test data, executing the step of selecting the stored data from the second data set until the stored data in the second data set is selected; and if the stored data is different from the corresponding test data, generating a test result of a test error by using the information of the address corresponding to the stored data, and reporting the test result to the upper computer.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116580758A (en) * | 2023-07-13 | 2023-08-11 | 联和存储科技(江苏)有限公司 | SD NAND test device, SD NAND test method, and computer-readable storage medium |
| CN117435416A (en) * | 2023-12-19 | 2024-01-23 | 合肥康芯威存储技术有限公司 | Memory testing system and method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116580758A (en) * | 2023-07-13 | 2023-08-11 | 联和存储科技(江苏)有限公司 | SD NAND test device, SD NAND test method, and computer-readable storage medium |
| CN117435416A (en) * | 2023-12-19 | 2024-01-23 | 合肥康芯威存储技术有限公司 | Memory testing system and method |
| CN117435416B (en) * | 2023-12-19 | 2024-04-05 | 合肥康芯威存储技术有限公司 | Memory testing system and method |
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