CN204834060U - A damage interior statistical system of unit piece for having more page memory array - Google Patents
A damage interior statistical system of unit piece for having more page memory array Download PDFInfo
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- CN204834060U CN204834060U CN201520591729.0U CN201520591729U CN204834060U CN 204834060 U CN204834060 U CN 204834060U CN 201520591729 U CN201520591729 U CN 201520591729U CN 204834060 U CN204834060 U CN 204834060U
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Abstract
The utility model relates to a damage interior statistical system of unit piece for having more page memory array, including latching the module, it can the module to latch the messenger, write -back address module, page buffer write -back module, the error counting module, verification result latchs module and wrong figure statistics district, it is located and reads data path to latch the module, a success zone digit for receiving verification module sends, and latch latching under the condition of signal that the messenger can the module sends receiving, and when the successful zone digit of current address is the mistake, produce and keep the erroneous operation result to give the page buffer, the error counting module is given to the wrong result that produces real -time update simultaneously, the utility model provides a current memory chip test method consuming time for a long time, the complicated technical problem of test, the utility model discloses a statistical system has directly left out subsequent read operation page by page in the piece, very big simplification the test sequence, saved test time, reduced test cost.
Description
Technical field
The utility model relates to a kind of for statistical system in the impairment unit sheet of multipage storage array storer.
Background technology
In memory inside, its storage array is made up of both direction, as the inside of page operations class storer (as FLASH or RRAM etc.), its array structure is as Fig. 1, interweaved by wordline (bl) and bit line (wl) and define storage array, there is a storage unit at each point of crossing place, and each storage unit comprises wl, bl and sl port.Wherein every root wl is expert at and is one page, it has been connected and has been in all storage unit of same one page, when performing page operations, a wl will be had selected, all storage unit of same one page that this wl connects are by selected, then array periphery control circuit transmits different operation informations (as in programming, giving different operating voltages under the operations such as erasing) according to data content to be read and write to each bl, thus realizes the access work to data.Every root bl shuttles back and forth between multiple page, and when array processing, data are according to mode page by page, and by selecting wl to select operation page, pair array realizes data access.The data bits of page buffer is identical with the bl radical of array page, thus when page array processing, data are moved from page array (page buffer) to page buffer (page array) by the realization of the complete equity that can walk abreast.
But due to a variety of causes such as semiconductor fabrication process, in memory more or less there is impairment unit.These impairment units show and array have various distribution.The general storage unit having the damage be present on not same page on bl, these different spot failures be present in different wl capable on same bl on, be referred to as bl direction and damage.So chip can add some in array inside redundant word line bl when designing carries out reparation replacement for damaging for known bl when the later stage tests, thus make chip can continue to use.In like manner in wl direction, still can there is similar damage, the storage unit certain root wl existing varying number is damaged, be called that wl direction is damaged, therefore in like manner also can be designed with the redundant bit line wl of some at chip internal, damage for known wl when testing for the later stage and carry out reparation replacement.Because redundancy wl/bl number is limited, the repair ability of this repair mode is also limited, can only repair error number situation within the specific limits.Therefore in chip testing, need to test all arrays, according to mistake of statistics distribution results, the type of error of chip and error number are analyzed, and then determines recovery scenario.For how detected and record by the damaged memory unit in memory array, test mode main is at present: test phase before memory chip dispatches from the factory, and carries out test specific practice as follows by test base station to memory chip:
The all storage arrays of test base station to chip to be measured are utilized to carry out read-write operation, during operation for each address, base station can carry out data writing operation, and record data that current address is write, afterwards read data operation is carried out to same address, contrast with the data of writing recorded before, if data can not be mated simultaneously, then think that the storage unit of this address is impairment unit, by current address record to a certain extent.By that analogy, after test base station travels through whole memory space address, namely the position of impairment units all in array can be screened.
Although this mode can carry out test statistics to memory chip comparatively accurately, obtain the error rate statistic data of every chips, and then carry out follow-up reparation flow process.But this test mode still has the following disadvantages:
1, based on the measuring method of test base station need to expend time in exploitation base station end test and excitation and compare screening supervisor, the development in early stage needs the human and material resources of at substantial.
2, this method needs to do once complete read-write operation for each memory address simultaneously, and this all makes the memory chip test duration longer, extends the product export time.
Summary of the invention
For a long time consuming time in order to solve existing storage core chip test method, the technical matters of testing complex, the utility model provides a kind of for statistical system in the impairment unit sheet of multipage storage array.
Technical solution of the present utility model:
A kind of for statistical system in the impairment unit sheet of multipage storage array, its special character is: comprise latch module, latch enable module, write back address module, page buffer write-back module, error count module, the result latch module and error number Statistical Area
Described latch module is positioned in read data path, for the Success Flag position that Receipt Validation module sends, and when receiving the latch signal that latch enable module sends, and the Success Flag position of current address be mistake time, produce and keep faulty operation result to page buffer, producing the error result of real-time update to error count module simultaneously;
Described latch enable module is used for the generation latch signal when control decision logic module judges to learn that current operation is the secondary operation eventually of current address, and sends to latch module and page buffer write-back module;
Described write back address module be used for control decision logic module judge to learn current operation is current address eventually time operation time from address generator extract with this end secondary operate corresponding to current address information, and send to page buffer write-back module;
Described page buffer write-back module be used for producing write back address information according to the current address information that receives and latch signal and write-back enable, and send to page buffer, page buffer according to the write back address information received and write-back enable, the final operating result of current address is stored in page buffer relevant position, for the follow-up reading of external interface;
Described error count module: for carrying out sampling judgement to latching the result of reading returned, if the zone bit reading the result final is returned as failure, then counting adds 1, otherwise keeps;
Described error number Statistical Area is used for the error statistics number of damaged memory unit in storage array.
Also comprise compression module, described compression module is used for carrying out data compression process to reduce storage consumption to the count value of error count module, error statistics information is stored in error number Statistical Area.
Above-mentioned latch module comprises the first latch cicuit and the second latch cicuit, described first latch cicuit comprises or door and the first latch, described second latch cicuit comprises the second latch, an input termination that is described or door connects the Success Flag position that authentication module sends, described or gate output terminal connects the data input pin of the first latch, the input end of clock of described first latch connects latch signal, the final operating result that the output terminal of described first latch exports current address to page buffer and or another input end of door;
The data input pin of described second latch connects the Success Flag position of authentication module transmission, and the input end of clock of described second latch connects latch signal, and the output terminal output error result of described latch is to error count module.
The advantage that the utility model has:
Of the present utility model interior statistical system is for external test sequence, can after executing write operation page by page, the concrete error distribution statistics information in current multipage array only can be obtained with a page buffer read operation, directly eliminate follow-up read operation page by page, greatly simplify cycle tests, save the test duration, reduce testing cost.
Accompanying drawing explanation
Fig. 1 is storage array schematic layout pattern;
Fig. 2 is enforcement module diagram of the present utility model;
Fig. 3 is enforcement module diagram of the present utility model
Fig. 4 is utility model works schematic flow sheet;
Fig. 5 is the cycle tests application example contrast figure in test process;
Fig. 6 is the signal of latch module circuit; Fig. 6 a is the structural representation of the first latch, and Fig. 6 b is the structural representation of the second latch;
Fig. 7 is the signal of the utility model physical circuit module;
Wherein Reference numeral is: U1-page buffer, U2-data path, U3-storage array.
Embodiment
As shown in Figure 2, add latch module, latch enable module, write back address module, page buffer write-back module, error count module, compression module, the result latch module and error number Statistical Area, error number Statistical Area is the region for depositing maximum bl error number in array added at page buffer, it is open to external interface io, can be read by external interface io.Compression module is for carrying out data compression process to reduce storage consumption to the value of counter.The function of error count module is for adding up to the misdata occurred on certain root bl, namely when array is write, sampling judgement is carried out to the result of reading of each address in each page operations process, if the final zone bit of operation address is returned as failure, then counting adds 1, otherwise keeps.Like this along with array write operation page by page, when every root bl detecting the Returning mark of operation failure occurs, this counter all can upgrade and add 1.By that analogy, at the end of each page operations, the result of this counter is each bl in current block and makes a mistake the final statistics numbers of number of times.Afterwards this count value is carried out compression process, and be stored in the error number Statistical Area of page buffer.
Simultaneously, give to improve in the middle of the result latch module, as shown in Figure 2 and Figure 3, once certain bl address detected occurs to mistake, then keep this error message, even if this address inerrancy occurs or has more mistakes to occur in continued page, latch module still keeps error flag never to upgrade (if wl different in array is in the erroneous point in same bl direction), until all page operations terminate, the information that these reflections last damage positions is deposited into the relevant position of page buffer, to be used to indicate on the bl of its place whether wrong generation.And then test base station can pass through page buffer read operation, reads the content of page buffer, carry out analyzing the bl radical can learning damage, its workflow as shown in Figure 4.
Adding of error count mechanism makes chip namely innerly can carry out cumulative statistics to the error number on bl automatically in normal array processing process, and is stored into error statistics district (page buffer redundant space).Meanwhile, in storage array, the bl positional information of the wrong generation of every root also can be stored in page buffer accordingly, is equivalent to the error statistics work that chip internal completes bl automatically.So far, bl Fault Distribution situation and error number are all obtained by Built-In Self-Test mechanism and are opened to interface.Test base station only needs the information of direct read error Statistical Area, both can obtain the statistics that bl mistake occurs in chip-stored inside, directly reads page buffer simultaneously and can obtain bl Fault Distribution situation.Then the further profiling error situation of tester, and then make concrete recovery scenario in conjunction with actual conditions.
Fig. 5 is the utility model physical circuit module diagram, comprise latch module, latch enable module, write back address module, page buffer write-back module, error count module, compression module, the result latch module and error number Statistical Area, latch module is positioned in read data path, for the Success Flag position that Receipt Validation module sends, and when receiving the latch signal that latch enable module sends, is sampled in the Success Flag position of current address, produce the final operating result of current address; Latch enable module is used for the generation latch signal when control decision logic module judges to learn that current operation is the secondary operation eventually of current address, and sends to latch module and page buffer write-back module; Write back address module be used for control decision logic module judge to learn current operation is current address eventually time operation time from address generator extract with this end secondary operate corresponding to current address information, and send to page buffer write-back module; Page buffer write-back module be used for producing write back address information according to the current address information that receives and latch signal and write-back enable, and send to page buffer, page buffer according to the write back address information received and write-back enable, the final operating result of current address is stored in page buffer relevant position, for the follow-up reading of external interface; Error count module: for carrying out sampling judgement to latching the result of reading returned, if the zone bit reading the result final is returned as failure, then counting adds 1, otherwise keeps; Error number Statistical Area is used for the error statistics number of damaged memory unit in storage array, compression module, described compression module is used for carrying out data compression process to reduce storage consumption to the count value of error count module, error statistics information is stored in error number Statistical Area.
As shown in Figure 6, latch module is latch circuit, and latch circuit 1 is error result holding circuit, as certain root bl makes a mistake, does not record a demerit with the mistake on root bl in this mistake of renewal.Latch module 2 is real-time sampling bl error result circuit, and also upgrade the final operating result from the same bl of different wl for real-time sampling, if wrong result occurs, error number counting module adds 1, to add up the error number of same root bl.The data input pin of latch circuit connects the Success Flag position of authentication module transmission, and the input end of clock of latch connects latch signal, and the output terminal of latch exports the final operating result of current address.
As the cycle tests application example contrast that Fig. 7 is in test process, in traditional cycle tests, need to carry out the read operation of write operation page by page-page by page, then obtaining reads and writes data is compared and is obtained mistake contrast distribution.And if sheet in add concrete enforcement of the present utility model after, for external test sequence, can after executing write operation page by page, the concrete error distribution statistics information in current multipage array only can be obtained with a page buffer read operation, directly eliminate follow-up read operation page by page, greatly simplify cycle tests, save the test duration, reduce testing cost.
Claims (3)
1. one kind for statistical system in the impairment unit sheet of multipage storage array, it is characterized in that: comprise latch module, latch enable module, write back address module, page buffer write-back module, error count module, the result latch module and error number Statistical Area
Described latch module is positioned in read data path, for the Success Flag position that Receipt Validation module sends, and when receiving the latch signal that latch enable module sends, and the Success Flag position of current address be mistake time, produce and keep faulty operation result to page buffer, producing the error result of real-time update to error count module simultaneously;
Described latch enable module is used for the generation latch signal when control decision logic module judges to learn that current operation is the secondary operation eventually of current address, and sends to latch module and page buffer write-back module;
Described write back address module be used for control decision logic module judge to learn current operation is current address eventually time operation time from address generator extract with this end secondary operate corresponding to current address information, and send to page buffer write-back module;
Described page buffer write-back module be used for producing write back address information according to the current address information that receives and latch signal and write-back enable, and send to page buffer, page buffer according to the write back address information received and write-back enable, the final operating result of current address is stored in page buffer relevant position, for the follow-up reading of external interface;
Described error count module: for carrying out sampling judgement to latching the result of reading returned, if the zone bit reading the result final is returned as failure, then counting adds 1, otherwise keeps;
Described error number Statistical Area is used for the error statistics number of damaged memory unit in storage array.
2. according to claim 1 for statistical system in the impairment unit sheet of multipage storage array, it is characterized in that: also comprise compression module, described compression module is used for carrying out data compression process to reduce storage consumption to the count value of error count module, error statistics information is stored in error number Statistical Area.
3. according to claim 1 and 2 for statistical system in the impairment unit sheet of multipage storage array, it is characterized in that: described latch module comprises the first latch cicuit and the second latch cicuit, described first latch cicuit comprises or door and the first latch, described second latch cicuit comprises the second latch, an input termination that is described or door connects the Success Flag position that authentication module sends, described or gate output terminal connects the data input pin of the first latch, the input end of clock of described first latch connects latch signal, the final operating result that the output terminal of described first latch exports current address to page buffer and or another input end of door,
The data input pin of described second latch connects the Success Flag position of authentication module transmission, and the input end of clock of described second latch connects latch signal, and the output terminal output error result of described latch is to error count module.
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| CN201520591729.0U CN204834060U (en) | 2015-08-03 | 2015-08-03 | A damage interior statistical system of unit piece for having more page memory array |
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| CN201520591729.0U CN204834060U (en) | 2015-08-03 | 2015-08-03 | A damage interior statistical system of unit piece for having more page memory array |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105097049A (en) * | 2015-08-03 | 2015-11-25 | 西安华芯半导体有限公司 | On-chip statistical system used for damaged units in multipage memory arrays |
| CN106776100A (en) * | 2017-01-17 | 2017-05-31 | 上海航天控制技术研究所 | A kind of memory data is layered method of calibration |
-
2015
- 2015-08-03 CN CN201520591729.0U patent/CN204834060U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105097049A (en) * | 2015-08-03 | 2015-11-25 | 西安华芯半导体有限公司 | On-chip statistical system used for damaged units in multipage memory arrays |
| CN105097049B (en) * | 2015-08-03 | 2017-11-10 | 西安紫光国芯半导体有限公司 | Statistical system in a kind of impairment unit piece for multipage storage array |
| CN106776100A (en) * | 2017-01-17 | 2017-05-31 | 上海航天控制技术研究所 | A kind of memory data is layered method of calibration |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Patentee after: XI'AN UNIIC SEMICONDUCTORS Co.,Ltd. Address before: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Patentee before: Xi'an Sinochip Semiconductors Co., Ltd. |
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| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20151202 Effective date of abandoning: 20171110 |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20151202 Effective date of abandoning: 20171110 |