CN112071355A - Self-adaptive BIST (built-in self-test) test method for improving fault coverage rate - Google Patents
Self-adaptive BIST (built-in self-test) test method for improving fault coverage rate Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1202—Word line control
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1204—Bit line control
Abstract
A self-adaptive BIST test method for improving fault coverage rate is realized by an SRAM test control module, a fault pre-analysis module and an algorithm generation module. The SRAM test control module controls the working voltage, temperature, process and the like of the SRAM storage array to be tested, so that the SRAM is exposed to more fault behaviors in different working environments, and the escape rate of faults is reduced; the fault pre-analysis module is used for pre-judging faults possibly occurring in the storage array in advance, the judgment result is input into the algorithm generation module, the algorithm generation module reconstructs the optimal algorithm of the storage array under the current environment and generates a new BIST circuit, and the high-efficiency and rapid fault test is carried out on the storage array. The technology breaks through the limitation of the traditional algorithm, can improve the fault coverage rate and reduce the test cost.
Description
Technical Field
The invention belongs to the field of SRAM test, and particularly provides a self-adaptive BIST test method for improving fault coverage rate.
Background
In the process of high-speed development of integrated circuits, high integration degree, high stability and strong cruising ability become important indexes for measuring products, but with continuous reduction of chip size, voltage is continuously reduced, even tiny manufacturing defects brought by complex processes all provide huge challenges for the stability of the SRAM, various adverse factors cause mismatching of threshold voltages of adjacent transistors in a storage array, the robustness of the SRAM is increasingly poor, the read-write capability is increasingly poor, even read-write failure is caused, and the error rate is increased dramatically. None of the algorithms in the existing research results can completely cover all kinds of failures caused by various adverse factors. Any soft fault that escapes may greatly affect the reliability of the product. There are also many researchers to calculate a specific algorithm for some complex dynamic stability faults, but these algorithms usually face the problems of high complexity, long test time and expensive test cost, so how to solve the limitations of the algorithms and optimize the test time and power consumption of the algorithms, and reducing the test cost becomes the breakthrough point of the current research technology.
Disclosure of Invention
The present invention addresses the above-mentioned problems in the background art by providing an adaptive BIST test technique that improves fault coverage.
A self-adaptive BIST test method for improving fault coverage rate is realized by an SRAM test control module, a fault pre-analysis module, an algorithm generation module, an MBIST controller and an SRAM storage array;
the testing method comprises the steps that the SRAM testing control module sets the working environment of the SRAM storage array, the fault pre-analysis module analyzes the working environment set by the SRAM testing control module, the probability of which faults occur in the SRAM storage array at the moment is judged in advance, the fault pre-analysis module inputs the judgment result to the algorithm generation module, the algorithm generation module makes a response of extracting and adjusting effective testing elements, the extracted and adjusted testing elements are reconstructed into a new testing algorithm, and a special BIST testing circuit is generated to test the SRAM storage array.
Further, the SRAM test control module inputs the operating environment index, including but not limited to temperature, voltage, and process corner, of the specific SRAM memory array that the user needs to set.
Furthermore, the basis of the pre-judgment made by the fault pre-analysis module is research and simulation data of a large number of fault models and fault behaviors in different environments, and the fault models in the fault pre-analysis module can be continuously updated to ensure that various faults are covered.
Further, the failure pre-analysis module can ensure that the updated model is valuable and non-redundant when updating the internal failure model. Meanwhile, the fault pre-analysis module compares the result input by the SRAM test control module with the existing fault model for analysis, and pre-judges which faults are easy to occur in the actual storage array under the environment.
Furthermore, the algorithm generation module stores the optimal test elements with high fault coverage rate after hybrid simulation verification, when the fault pre-analysis module gives a pre-judgment result that the current SRAM memory array has fault types, the algorithm module automatically calls the corresponding optimal test elements to reconstruct a new algorithm, and the BIST circuit with self-adaptability generated by the reconstructed algorithm tests the core unit of the current SRAM memory array.
Further, the test elements stored inside the algorithm generation module are updated and optimized according to the change of the internal fault model in the fault pre-analysis module.
Further, the MBIST controller comprises an algorithm controller, an address generation module, a signal generation module, a data generation module and a comparator, wherein the algorithm controller converts a special BIST test circuit obtained by the algorithm generation module into a specific test operation behavior, the algorithm controller controls each module to generate corresponding address information and data information, the information can open a bit line and a word line of a corresponding SRAM memory cell in the memory array after being transmitted by the circuit, corresponding read-write operation is completed through charging and discharging of a transistor structure in the cell, and finally a test result value is compared with an expected value through the comparator to judge whether the current SRAM memory array has faults or not so as to complete testing.
The invention has the beneficial effects that: (1) the SRAM test control module, the fault pre-analysis module and the algorithm generation module can break through the limitation of the algorithm, and the self-adaptability of the SRAM test control module, the fault pre-analysis module and the algorithm generation module can ensure that complex and various faults can obtain an optimal test scheme. The formed test scheme can realize the aims of high fault coverage rate, low power consumption and short test time; (2) the internal module included in the technology can be updated and optimized continuously, the fault model in the fault pre-analysis module and the test elements stored in the algorithm generation module can be added and modified at any time, and only the added new model or algorithm test elements can be left in the module after the effectiveness of the added new model or algorithm test elements is verified through experiments. Therefore, the sustainable development optimization of the technology is ensured, and the technology cannot occupy excessive resources.
Drawings
Fig. 1 is a general block diagram in an embodiment of the present invention.
Fig. 2 is a flow chart of the operation of the system in the embodiment of the invention.
FIG. 3 is a diagram illustrating the relationship between the hardness and the difficulty of the soft-hard fault test and the power voltage according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a location of a research failure in the embodiment of the present invention.
FIG. 5 is a waveform diagram illustrating a verification waveform of the effective test element Finesim in the embodiment of the present invention.
Fig. 6 is a simulation waveform of a reconstruction algorithm in an embodiment of the present invention.
Fig. 7 is a simulation waveform of the March _ C algorithm in the embodiment of the present invention.
Detailed Description
The technical scheme of the invention is further explained in detail by combining the drawings in the specification.
The embodiment provides an adaptive BIST technology aiming at breaking through the limitation of the algorithm of the memory array, improving the test fault coverage rate and shortening the test time. The technology innovatively provides an algorithm reconstruction idea, and the flexible self-adaptability of the technology can be more than necessary when various complex fault tests are carried out.
The general block diagram is shown in fig. 1, and is composed of an SRAM test control module, a failure pre-analysis module, and an algorithm generation module. The specific system work operation flow is shown in fig. 2.
(1) Introduction to SRAM test control Module
The 6T memory cell is realized by a cross-coupled inverter pair, and as the requirement for reducing power consumption is more and more strict, reducing the working voltage of the SRAM becomes a main means for realizing low power consumption. However, the continuous reduction of the voltage causes the contradiction between the read stability and the write margin of the memory cell, the stability of the transistor is continuously reduced, and more soft faults occur. These soft faults are easy to escape in the traditional classical algorithm test, and the existence of the soft faults becomes the main culprit for influencing the reliability of products. These failures require extensive read and write operations to be desensitized to possible exposure. As shown in fig. 3, the difficulty of soft fault testing at lower voltages increases. Therefore, the research on various soft fault models of the SRAM at low voltage is very important.
The SRAM test control module provides a variable working environment, and the flexibly-adjustable environment can research faults existing in the storage array under different voltages, different temperatures and even different processes. And an experimental environment is provided for guaranteeing the effectiveness of researching each fault model and verifying the algorithm.
(2) Fault pre-analysis module
The failure pre-analysis module has two functions, namely: the internal fault model may be stored and updated. There is also a need to ensure that updated models are valuable and non-repetitive when updating internal fault models, which can reduce resource usage. And a second function: the result output by the controller module can be compared and analyzed with the existing fault model, and the faults of the actual storage array which are easy to occur under the environment can be pre-judged.
By researching which positions in the storage unit are easy to fail, the concrete behavior of the failure is used as a concrete basis for the judgment of the failure pre-analysis module. Fig. 4 is a schematic diagram of locations in a core unit that are prone to failure, for example: DF1 usually delays the charging and discharging of storage nodes during write operations and thus causes tf (transition fault), which is usually detectable by conventional algorithms, but when the core cell stores a logic value of 0, the fault behavior may be converted into a dynamic read destructive fault, which requires a special sensitization operation.
By analyzing the fault behavior, the fault can be continuously changed due to the position, the resistance value of the fault resistor, the logic value stored in the storage node of the core unit, the reading or writing operation of the current circuit and the like, and especially after the voltage is reduced, more hidden soft faults can be exposed along with the weakening of the stability of the core unit, so that a fault model stored in the fault pre-analysis module needs to consider various factors as much as possible, the whole pre-analysis module is set as a function, and the output result shows the response corresponding to the function: f (a, b.c, d …) = E. The factors a, b, c, d … … in the function represent variables that affect the fault behavior, such as voltage, resistance, position, etc., and E represents the fault behavior determined by the factors. And matching the result input into the fault pre-analysis module by the SRAM test control module with an internally stored model to obtain a fault model with high goodness of fit, and outputting a corresponding control signal of the fault model as a pre-analysis result to the next module.
The difficulty of the fault pre-analysis module lies in that fault simulation experiments are required to be carried out on a large number of different conditions, variables influencing fault behaviors are large, even different fault behaviors can be generated on the same fault resistor due to different read-write operations or different voltage values of internal storage nodes, and the obtained optimal fault model can be used for guiding a subsequent reconstruction optimal algorithm.
(3) Algorithm generation module design
And after the results of the fault pre-analysis module are input into the algorithm generation module, the algorithm generation module is started. A number of optimal test elements with high fault coverage already verified by the hybrid simulation are stored in the algorithm generation module, when the failure pre-analysis module gives a pre-judgment result of the failure type of the current storage array, the algorithm module automatically calls the corresponding optimal test element to reconstruct a new algorithm, the reconstructed algorithm can effectively test the failure of the current core unit, each element of the reconstructed algorithm is targeted, the test time does not become longer due to redundant test elements when testing the memory array, the limitation that the traditional test algorithm can only test for some hard faults and single soft faults is broken through, the BIST circuit with the self-adaptability generated by flexible algorithm reconstruction effectively improves the fault coverage rate, reduces the test difficulty and shortens the test time.
In the process of researching different fault models by the fault pre-analysis module, it can be known that the fault behavior can be changed along with certain factors, and the corresponding test sensitized elements need to be modified and optimized continuously, so that the internally stored test elements need to be updated and optimized in the algorithm generation module.
The algorithmic reorganization process is now described:
when a core unit in the memory array has simple hard faults such as fixed faults, bridging faults and the like, usually one read-write operation can be tested, for example, a fixed 1 fault can be tested through a W0R0 (write 0 read 0) operation, and a TF fault needs to be tested by a read operation immediately after a value opposite to that of an original memory unit is written, so that it can be obtained that the sensitization of faults related to resistive open defects of the core unit only needs operation elements such as 1W0R0 and 0W1R1, and the two elements are stored in an algorithm analysis module.
For soft faults such as DRDF (digital data recorder), when the fault resistance is low or the clock frequency is not high, simple read-write operation cannot sensitize the fault, multiple read-write operations are required for sensitizing the fault, the soft faults need more read-write operations compared with hard faults, and the corresponding test element is 0w0r0M 、1w0r0M 、1w1r1MAnd 0w1r1M(M represents the number of times the operation is performed) and these elements are stored in the algorithm module.
There is also a soft fault, which is not easily tested by simply increasing the read-write times, and which is more easily generated at low voltage. For example, two adjacent cells sharing a bit line in a memory array may be susceptible to dynamic coupling failures. The adjacent two units are not interfered under the normal working voltage of the SRAM, but as the voltage is reduced, the voltage of a storage node of a unit with relatively weak stability in the two units is easily influenced by the charging and discharging of a circuit when the other unit carries out read-write operation, when adverse factors are gradually increased, the voltage of the storage node of the storage unit slowly cannot keep the stored logic value, and finally the unit does not carry out the read-write operation but influences the self storage content along with the read-write operation of the other unit. Such failures do not easily occur at normal voltages, but severely affect the stability of the memory array at low voltages. Because the fault is similar to a coupling fault in appearance, test elements of ↓: W0, ↓: W1, and ↓: R0 are selected first, the fault mainly occurs in row units of a common word line, so that address factors need to be considered when the fault is activated, different read-write operations need to be performed on an attack unit and a victim unit, and therefore the test elements need to be distinguished for reading and writing. ↓: R0 (column 0), ×) and ↓ + W2 (column 825956) are effective test elements for the failure in the write operation. This element can effectively activate the fault, the Finesim simulation waveform is shown in fig. 5. The element is stored in the algorithm generation module.
The method comprises the steps of adjusting the working voltage of a current storage array to 0.8V, setting a process angle to TT, setting the temperature to 25 ℃, setting other factors influencing a fault model such as a fault occurrence position to be a victim unit storage node, setting a fault resistance value to be (600-. Integrating the test elements (combining repeated operations), wherein the reconstructed algorithm elements are as follows: ↓: W0, ↓R0 (column 0) ↓ 1 (column 0), ↓r0 (column) ↓ 0). And outputting the reconstructed algorithm to the interior of the MBIST controller, and testing the storage array, wherein the test simulation result is shown in FIG. 6. The simulation waveform of the conventional algorithm March _ C is shown in FIG. 7. And (4) simulating by using the VCS, wherein a Fail _ h signal in a simulation oscillogram is pulled high to represent that a fault is tested, and 0 is always used to represent that no fault is tested. Experimental results show that the traditional testing algorithm cannot cover the complex soft faults, but the reconstructed algorithm breaks through the limitation and detects the faults. The low complexity of the reconstruction algorithm is considered from the complexity of the algorithm, and the testing time is short.
The above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiment, but equivalent modifications or changes made by those skilled in the art according to the present disclosure should be included in the scope of the present invention as set forth in the appended claims.
Claims (6)
1. A self-adaptive BIST test method for improving fault coverage rate is characterized in that:
the method is realized by an SRAM test control module, a fault pre-analysis module, an algorithm generation module, an MBIST controller and an SRAM storage array;
the testing method comprises the steps that the SRAM testing control module sets the working environment of the SRAM storage array, the fault pre-analysis module analyzes the working environment set by the SRAM testing control module, the probability of which faults occur in the SRAM storage array at the moment is judged in advance, the fault pre-analysis module inputs the judgment result to the algorithm generation module, the algorithm generation module makes a response of extracting and adjusting effective testing elements, the extracted and adjusted elements are reconstructed into a new testing algorithm, a special BIST testing circuit is generated, and the SRAM storage array is tested through the MBIST controller.
2. The adaptive BIST test method for improving fault coverage as recited in claim 1, wherein: the SRAM test control module inputs the environment indexes, including but not limited to temperature, voltage and process angle, of the specific SRAM memory array required to be set by the user.
3. The adaptive BIST test method for improving fault coverage as recited in claim 1, wherein: the fault pre-analysis module makes a pre-judgment according to the research and simulation data of a large number of fault models and fault behaviors in different environments, and the fault models stored in the fault pre-analysis module can be continuously updated so as to ensure that various faults are covered.
4. The adaptive BIST test method for improving fault coverage of claim 3, wherein: the failure pre-analysis module can ensure that the updated model is valuable and non-repeatable when the internal failure model is updated, and meanwhile, the failure pre-analysis module compares the result input by the SRAM test control module with the existing failure model for analysis, and pre-judges which failures are easy to occur in the actual storage array under the environment.
5. The adaptive BIST test method for improving fault coverage as recited in claim 1, wherein: the algorithm generation module stores the optimal algorithm elements with high fault coverage rate after hybrid simulation verification, when the fault pre-analysis module gives a pre-judgment result of the fault types of the current SRAM storage array, the algorithm module automatically calls the corresponding optimal test elements to reconstruct a new algorithm, and the reconstructed algorithm generates a self-adaptive BIST circuit to test the core unit of the current SRAM storage array.
6. The adaptive BIST test method for improving fault coverage of claim 5, wherein: and the test elements stored in the algorithm generation module are updated and optimized according to the change of the fault model stored in the fault pre-analysis module.
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| WO2022099947A1 (en) * | 2020-11-12 | 2022-05-19 | 南京邮电大学 | Adaptive bist method for improving fault coverage |
| CN115083500A (en) * | 2022-08-19 | 2022-09-20 | 南京邮电大学 | Reconfigurable MBIST method based on adaptive March algorithm |
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| CN111243657A (en) * | 2020-03-03 | 2020-06-05 | 南京邮电大学 | Effective random fault injection method for memory circuit |
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| US20090296505A1 (en) * | 2008-05-30 | 2009-12-03 | Fujitsu Limited | Memory test method and memory test device |
| CN111383704A (en) * | 2018-12-29 | 2020-07-07 | 深圳市海思半导体有限公司 | Memory built-in self-test circuit and memory test method |
| CN110570896A (en) * | 2019-07-31 | 2019-12-13 | 南京邮电大学 | Low-voltage SRAM (static random Access memory) testing method for weak faults |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2022099947A1 (en) * | 2020-11-12 | 2022-05-19 | 南京邮电大学 | Adaptive bist method for improving fault coverage |
| CN115083500A (en) * | 2022-08-19 | 2022-09-20 | 南京邮电大学 | Reconfigurable MBIST method based on adaptive March algorithm |
| CN115083500B (en) * | 2022-08-19 | 2022-11-01 | 南京邮电大学 | Reconfigurable MBIST method based on adaptive March algorithm |
| WO2024036881A1 (en) * | 2022-08-19 | 2024-02-22 | 南京邮电大学 | Reconfigurable mbist method based on adaptive march algorithm |
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