CN111243657A - Effective random fault injection method for memory circuit - Google Patents
Effective random fault injection method for memory circuit Download PDFInfo
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Abstract
The invention provides an effective random fault injection method for a memory circuit, which comprises the following steps: the method comprises the following steps: extracting all nodes which are possible to have faults by using a Perl language, modifying all fault node names, and generating a new file; step two: randomly selecting one or more fault nodes in the node file, and inserting a resistance random resistor into the nodes; step three: and after inserting the resistor, generating a new memory netlist file which completes random fault injection. The netlist after fault injection can be generated by the method, and random fault injection is realized. The random fault injection method provided by the invention is characterized in that the positions of the nodes of the fault injection circuit are random, the fault injection quantity is random, and the injection resistance value is random, so that the method is a feasible method and can effectively verify the fault coverage rate of the test algorithm.
Description
Technical Field
The invention relates to the field of testing of very large scale digital integrated circuits, in particular to an effective random fault injection method for a memory circuit.
Background
The rapid development of mobile internet applications puts increasing demands on the processing power and endurance time of smart mobile devices. Static Random Access Memory (SRAM) is one of the key modules of a mobile processor, and SRAM has a fast speed, a small capacity, and good compatibility, and is generally used as an embedded Memory, i.e., a cache or a temporary Memory. To meet the ever-increasing performance and power consumption requirements, low voltage SRAM design is becoming an increasingly important research focus in the industry. In order to improve the overall performance of the system on chip, reducing the power supply voltage is an effective means for improving the energy efficiency index of the circuit. However, in the case where the power supply voltage is lower than the threshold voltage, the influence of the process parameter variation on the stability of the memory cell and the critical path delay variation also increases sharply. With advanced technology, SRAM will exhibit more and more complex failure models.
The SRAM circuit is different from a general digital circuit, the SRAM is composed of a high-density memory array, the circuit structure is different according to different requirements, the failure occurrence rate is higher, the failure type is more complicated, and therefore, the test of the SRAM becomes more and more difficult, and due to various technical limitations, whether the conventional test algorithm can really detect the failure of the memory circuit and the coverage rate of the failure is not effectively verified. A feasible memory fault injection method for verifying a test algorithm is lacked in the field of memory test; the fault injection method applied in the engineering at present is software injection fault, injection fault based on Verilog level and chip injection fault in FPGA machine, the above methods have advantages and disadvantages, and the limitation is too high, most of the injection faults of the FPGA machine are faults caused by single event upset, and the functional faults caused by injection and manufacturing defects of the invention are very different; software-based and Verilog-level fault injection technology has no randomness, a single fault model is adopted, open-circuit and short-circuit faults are realized only artificially, the environment is ideal, and the actual working state of a circuit cannot be simulated.
Disclosure of Invention
The invention aims to provide an effective random fault injection method for a memory circuit, which is carried out at a circuit simulation level, realizes random fault injection node positions, random injection node numbers and random injection resistance values when faults are injected, has strong randomness compared with the existing method, and reduces the complexity of fault injection while verifying the effectiveness of an algorithm.
The invention provides an effective random fault injection method for a memory circuit, which comprises the following steps:
the method comprises the following steps: extracting all nodes which are possible to have faults by using a Perl language, modifying all fault node names, and generating a new file;
step two: randomly selecting one or more fault nodes in the node file, and inserting a resistance random resistor into the nodes;
step three: and after inserting the resistor, generating a new memory netlist file which completes random fault injection.
The further improvement lies in that: when the failed node is extracted in the first step, the netlist of the memory is analyzed, all circuit nodes which are possibly failed in the storage unit are extracted through Perl language, and the names of all the failed nodes are modified according to a preset naming rule, so that the randomly selected failed node is conveniently positioned in the original netlist when the fault is injected, a new fault node file is generated, and each row in the file is a fault node.
The further improvement lies in that: the method for selecting the fault node in the second step is as follows: randomly selecting p fault nodes from the fault node file, determining the positions of the randomly selected nodes in the original netlist through a naming rule, and injecting resistors with random resistance values; if p nodes are selected, the resistance values of the injection resistors are r1…..rpAnd each resistance value is random in size.
The further improvement lies in that: the resistor injected in the second step is named as Rfau1…RfaupThe back surface corresponds to two port sectionsDots, and random resistance r1…..rpAnd adding the information into the memory unit module to generate a new memory netlist file.
The invention has the beneficial effects that: the random and comprehensive fault injection is considered while fault injection is carried out, the resistor is added into the circuit structure of the memory, circuit defects possibly occurring in the manufacturing engineering of the analog circuit are simulated, and the fault coverage rate of the algorithm is verified while the effectiveness of the algorithm is verified. The fault injection is carried out on the spice netlist of the memory, so that the performability of the fault injection is improved, the correlation of the fault injection in practice is enhanced, and the complexity of subsequent simulation verification is reduced.
Drawings
FIG. 1 is a flow chart of a random fault injection method of the present invention.
FIG. 2 is a diagram of the structure of the SRAM of the present invention.
FIG. 3 is a node insertion resistance diagram of a 6T based SRAM circuit of the present invention.
FIG. 4 is a block diagram of a verify-after-fault-injection architecture based on an SRAM example of the present invention.
FIG. 5 is a waveform illustrating random fault injection verification for a 6T based SRAM cell in accordance with the present invention.
Detailed Description
For the purpose of enhancing understanding of the present invention, the present invention will be further described in detail with reference to the following examples, which are provided for illustration only and are not to be construed as limiting the scope of the present invention.
As shown in fig. 1-5, the present embodiment provides an efficient random fault injection method for a memory circuit, which comprises the following steps:
the method comprises the following steps: extracting all nodes which are possible to have faults by using a Perl language, modifying all fault node names, and generating a new file;
step two: randomly selecting one or more fault nodes in the node file, and inserting a resistance random resistor into the nodes;
step three: and after inserting the resistor, generating a new memory netlist file which completes random fault injection.
When the failed node is extracted in the first step, the netlist of the memory is analyzed, all circuit nodes which are possibly failed in the storage unit are extracted through Perl language, and the names of all the failed nodes are modified according to a preset naming rule, so that the randomly selected failed node is conveniently positioned in the original netlist when the fault is injected, a new fault node file is generated, and each row in the file is a fault node. The method for selecting the fault node in the second step is as follows: randomly selecting p fault nodes from the fault node file, determining the positions of the randomly selected nodes in the original netlist through a naming rule, and injecting resistors with random resistance values; if p nodes are selected, the resistance values of the injection resistors are r1…..rpAnd each resistance value is random in size. The resistor injected in the second step is named as Rfau1…RfaupThe back corresponds to two port nodes, and a random resistance r1…..rpAnd adding the information into the memory unit module to generate a new memory netlist file.
The embodiment improves the technical problem of fault injection of the memory, innovatively implements an effective random fault injection method of the memory, considers the randomness and the comprehensiveness of the fault injection while injecting the fault, adds a resistor in a circuit structure of the memory, simulates circuit defects possibly generated in a manufacturing project of a circuit, and verifies the fault coverage rate of an algorithm while verifying the effectiveness of the algorithm. The fault injection is performed on the memory spice netlist, so that the performability of the fault injection is improved, the correlation of the fault injection in practice is enhanced, and the complexity of subsequent simulation verification is reduced.
Fig. 1 shows a flowchart of the random fault injection method of this embodiment, and as shown in the figure, three major steps, including fault node extraction, random fault injection, and random fault injection verification, need to be completed to complete the random fault injection. The fault node extraction comprises the steps of positioning circuit nodes with possible faults of a memory, extracting all the circuit nodes, modifying the names of the circuit nodes, generating a circuit node list file, wherein each line in the file corresponds to one circuit node, and finishing the fault node extraction; random fault injection is a core module of the embodiment, and comprises random selected fault nodes, random number of selected nodes and random injection resistance values; randomly selecting different fault nodes at p (p > 0) in the node file, and injecting resistance values into each node randomly; as shown in fig. 1, when p different nodes are randomly selected, it is necessary to determine whether the selected node is the same as a fault node selected at the previous time after each selection is finished, if the selected node is the same, the node is selected again, and if the selected node is different, a resistor with a random resistance value is injected at the selected node, and then it is determined whether the selected p nodes have completely completed resistor injection (for example, 4 nodes are randomly selected, it is first determined that the 4 nodes do not have the same node, and then it is determined whether four resistors with random resistance values are injected), and finally a new memory netlist is generated, so as to implement random fault injection; and finally, verifying the feasibility of fault injection, generating a BIST test circuit based on a memory test algorithm, respectively testing the original netlist and the netlist after the fault injection, and verifying the feasibility of the fault injection by comparing the two test oscillograms.
In this embodiment, fault injection is completed based on memory cells, and fig. 2 is a structural diagram of a static random access memory, and as shown in the figure, a complete memory system includes an address decoder, a timing control unit, a column selector, a sense amplifier, a data buffer unit, and a memory array, where the memory array is a plurality of memory cells arranged in order, and as shown in the figure, a circuit structural diagram of the memory cells can be seen.
Fig. 3 is a circuit node insertion resistance diagram based on a 6T SRAM, as shown in the figure, each MOS device name and port node name are marked according to the description of the memory netlist file, when a circuit node is extracted, the circuit node name is modified, since a fault node is three ports of each MOS device, the device name is added before the node name, after a fault node is randomly selected, the corresponding node position can be located by the device name, as shown in the figure, when the randomly selected node name is Mnpg-b.bb, the fault injection position can be located according to the naming rule as Mnpg-b deviceAt bb node, injecting resistance r at fault node1Under the name Rfau1The resistance of (2).
FIG. 4 is a block diagram of a verification structure after fault injection is completed based on an SRAM example in the embodiment, as shown in the figure, a BIST circuit includes modules such as a state machine, an address generator, a data generator, an algorithm controller, and the like, and generates a test vector test memory circuit by using a March2 algorithm; and comparing the test output with expected data through a comparator, jumping to 1 from the tst-done signal after the comparison is finished, and jumping to 1 from the fail-h signal if the comparison data are consistent, otherwise. The experiment verifies the feasibility of the fault injection method based on a hybrid simulation environment, the BIST test circuit is written by Verilog statements and is simulated by VCS, and the SRAM to be tested is cdl netlist and is simulated by HSIM.
FIG. 5 is a waveform diagram for verifying random fault injection based on a 6T SRAM cell, comparing experimental results by a hybrid simulation test waveform diagram, wherein (a) is a waveform diagram of an original netlist test result of a memory, and observing two waveforms tst-done and fail-h in the diagram, wherein after tst-done jumps to 1, a fail-h signal is always 0, which indicates that a circuit test is finished and no fault occurs; and observing the two waveform jumps of the tst-done and the fail-h, and finding that when the tst-done signal is still 0, the fail-h signal jumps to 1, which indicates that the circuit has a fault. Further analysis shows that the corresponding test step is w1R1 when the waveform jumps, and the injection fault node is Rfau1The fault is represented by a conversion fault, the conversion from 0 to 1 cannot be realized, and the waveform is consistent with the waveform result checked by the algorithm, so that the feasibility of the method of the embodiment is effectively verified.
Claims (4)
1. An efficient random fault injection method for memory circuits, comprising: the method comprises the following steps:
the method comprises the following steps: extracting all nodes which are possible to have faults by using a Perl language, modifying all fault node names, and generating a new file;
step two: randomly selecting one or more fault nodes in the node file, and inserting a resistance random resistor into the nodes;
step three: and after inserting the resistor, generating a new memory netlist file which completes random fault injection.
2. An efficient memory circuit random fault injection method as recited in claim 1, wherein: when the failed node is extracted in the first step, the netlist of the memory is analyzed, all circuit nodes which are possibly failed in the storage unit are extracted through Perl language, and the names of all the failed nodes are modified according to a preset naming rule, so that the randomly selected failed node is conveniently positioned in the original netlist when the fault is injected, a new fault node file is generated, and each row in the file is a fault node.
3. An efficient memory circuit random fault injection method as recited in claim 1, wherein: the method for selecting the fault node in the second step is as follows: randomly selecting p fault nodes from the fault node file, determining the positions of the randomly selected nodes in the original netlist through a naming rule, and injecting resistors with random resistance values; if p nodes are selected, the resistance values of the injection resistors are r1…..rpAnd each resistance value is random in size.
4. An efficient memory circuit random fault injection method as recited in claim 1, wherein: the resistor injected in the second step is named as Rfau1…RfaupThe back corresponds to two port nodes, and a random resistance r1…..rpAnd adding the information into the memory unit module to generate a new memory netlist file.
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| CN202010138469.7A CN111243657A (en) | 2020-03-03 | 2020-03-03 | Effective random fault injection method for memory circuit |
| PCT/CN2021/075704 WO2021175099A1 (en) | 2020-03-03 | 2021-02-07 | Effective random fault injection method for memory circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021175099A1 (en) * | 2020-03-03 | 2021-09-10 | 南京邮电大学 | Effective random fault injection method for memory circuit |
| WO2022099947A1 (en) * | 2020-11-12 | 2022-05-19 | 南京邮电大学 | Adaptive bist method for improving fault coverage |
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| CN105548866A (en) * | 2015-12-08 | 2016-05-04 | 中国科学院电子学研究所 | SRAM type FPGA test method based on irradiation test environment simulation |
| CN108257645A (en) * | 2018-02-23 | 2018-07-06 | 南京邮电大学 | A kind of stable fault test method for low-voltage SRAM |
| CN108363894A (en) * | 2018-05-04 | 2018-08-03 | 西安电子科技大学 | A kind of circuit-level single particle effect emulation platform |
| CN110570896A (en) * | 2019-07-31 | 2019-12-13 | 南京邮电大学 | Low-voltage SRAM (static random Access memory) testing method for weak faults |
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| US10777294B2 (en) * | 2016-01-26 | 2020-09-15 | Hewlett Packard Enterprise Development Lp | DRAM-level error injection and tracking |
| CN108766501B (en) * | 2018-05-31 | 2020-06-30 | 西安微电子技术研究所 | Design and verification method for fault injection of storage with EDAC fault tolerance |
| CN111243657A (en) * | 2020-03-03 | 2020-06-05 | 南京邮电大学 | Effective random fault injection method for memory circuit |
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Patent Citations (4)
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| CN105548866A (en) * | 2015-12-08 | 2016-05-04 | 中国科学院电子学研究所 | SRAM type FPGA test method based on irradiation test environment simulation |
| CN108257645A (en) * | 2018-02-23 | 2018-07-06 | 南京邮电大学 | A kind of stable fault test method for low-voltage SRAM |
| CN108363894A (en) * | 2018-05-04 | 2018-08-03 | 西安电子科技大学 | A kind of circuit-level single particle effect emulation platform |
| CN110570896A (en) * | 2019-07-31 | 2019-12-13 | 南京邮电大学 | Low-voltage SRAM (static random Access memory) testing method for weak faults |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2021175099A1 (en) * | 2020-03-03 | 2021-09-10 | 南京邮电大学 | Effective random fault injection method for memory circuit |
| WO2022099947A1 (en) * | 2020-11-12 | 2022-05-19 | 南京邮电大学 | Adaptive bist method for improving fault coverage |
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