WO2021175099A1

WO2021175099A1 - Effective random fault injection method for memory circuit

Info

Publication number: WO2021175099A1
Application number: PCT/CN2021/075704
Authority: WO
Inventors: 蔡志匡; 余昊杰; 周正; 王荧; 王子轩; 谢祖帅; 刘璐; 郭宇锋
Original assignee: 南京邮电大学
Priority date: 2020-03-03
Filing date: 2021-02-07
Publication date: 2021-09-10
Also published as: CN111243657A

Abstract

The present invention provides an effective random fault injection method for a memory circuit. The method comprises the following steps: step 1, extracting all possible fault nodes with a Perl language, modifying the names of all fault nodes, and generating a new file; step 2, randomly selecting one or more fault nodes in the node file, and inserting resistance random resistors into the nodes; and step 3, generating a new memory netlist file with random fault injection completed after the resistor is inserted. According to the method, the netlist after the fault injection can be generated, and random fault injection is realized. The random fault injection method is characterized in that the node position of the fault injection circuit is random, the fault injection quantity is random, and the resistance value of the injection resistor is random, and the method is a feasible method, and can effectively verify the fault coverage of a test algorithm.

Description

An Effective Random Fault Injection Method for Memory Circuits

Technical field

The invention relates to the field of ultra-large-scale digital integrated circuit testing, in particular to an effective random fault injection method of a memory circuit.

Background technique

The rapid development of mobile Internet applications has put forward higher and higher requirements for the processing capabilities and battery life of smart mobile devices. Static Random Access Memory (SRAM) is one of the key modules of mobile processors. SRAM is fast, has a small capacity, and has good compatibility. It is generally used as embedded memory, that is, cache or temporary storage. Device. To meet the ever-increasing demand for performance and power consumption, low-voltage SRAM design is gradually becoming a research hotspot in the industry. In order to improve the overall performance of the system-on-chip, reducing the power supply voltage is an effective means to improve the energy efficiency of the circuit. However, when the power supply voltage is lower than the threshold voltage, the influence of process parameter changes on the stability of the memory cell and the change of the critical path delay also increases sharply. Under advanced technology, SRAM will have more and more complicated failure models.

The SRAM circuit is different from the general digital circuit. SRAM is composed of a high-density storage array. According to different needs, the circuit structure is also different. Its failure rate is higher and the type of failure is more complicated. Therefore, the test of SRAM becomes more and more complicated. It has become more difficult, and due to the limitations of various technologies, whether the traditional test algorithm can really detect the failure of the memory circuit and the coverage of the failure has not been effectively verified. In the field of memory testing, there has always been a lack of a feasible method of memory fault injection to verify the test algorithm; the current fault injection methods used in engineering are software injection faults, Verilog-based fault injections and chip faults in the FPGA machine. The above methods Each has its own advantages and disadvantages, and the limitations are too high. Most of the FPGA machine injection failures are caused by single event flipping. There is a big difference between the functional failures caused by the injection of manufacturing defects in the present invention; software-based and Verilog-level fault injection technology does not have Randomness and single fault model, only artificially realize open circuit and short circuit faults, the environment is more ideal, and the actual working state of the circuit cannot be simulated.

Summary of the invention

The purpose of the present invention is to provide an effective random fault injection method for a memory circuit, which can achieve random fault injection node positions, random number of injection nodes, and random injection resistance values by performing at the circuit simulation level and when injecting faults. The existing methods have strong randomness, which reduces the complexity of fault injection while verifying the effectiveness of the algorithm.

The present invention provides an effective random fault injection method for a memory circuit, and the method steps are as follows:

Step 1: Use Perl language to extract all the nodes that may fail, modify the names of all failed nodes, and generate a new file;

Step 2: Randomly select one or more faulty nodes in the node file, and insert random resistors with resistance values at the nodes;

Step 3: After inserting the resistor, a new memory netlist file with random fault injection is generated.

A further improvement is that when extracting faulty nodes in the first step, the storage netlist is first analyzed, and all the circuit nodes that may be faulty in the storage unit are extracted through Perl language, and the names of all faulty nodes are modified according to the predetermined naming rules, which is convenient During fault injection, the randomly selected faulty node is located in the original netlist, and a new faulty node file is generated. Each line in the file is a faulty node.

A further improvement is that the method for selecting faulty nodes in the second step is as follows: randomly select p faulty nodes from the faulty node file, and determine the position of the randomly selected node in the original netlist through naming rules, and inject a resistor with random resistance ; If p nodes are selected, the resistance values of the injection resistors are r ₁ … _{r p} , and the size of each resistance is random.

A further improvement is that the resistors injected in the second step are named R _fau1 …R _faup , which correspond to two port nodes and random resistance _values _{r 1} …r p, and the above information is added to the memory cell module to generate a new The storage netlist file.

The beneficial effects of the present invention: the randomness and comprehensiveness of the fault injection are taken into account while the fault is injected, resistors are added to the memory circuit structure, and the circuit defects that may occur in the manufacturing engineering of the circuit are simulated, and the validity of the algorithm is verified at the same time , Verified the fault coverage of the algorithm. The fault injection of the present invention is performed on the memory spice netlist, which improves the executable of the fault injection, enhances the relevance of the fault injection in practice, and reduces the complexity of subsequent simulation verification.

Description of the drawings

Fig. 1 is a flow chart of the random fault injection method of the present invention.

Figure 2 is a structural diagram of the SRAM of the present invention.

Fig. 3 is a diagram of node insertion resistance based on the 6T SRAM circuit of the present invention.

Fig. 4 is a block diagram of the verification structure after fault injection is completed based on the SRAM example of the present invention.

Fig. 5 is a waveform diagram of the random fault injection verification based on the 6T SRAM cell of the present invention.

Detailed ways

In order to deepen the understanding of the present invention, the present invention will be described in further detail below in conjunction with examples. The examples are only used to explain the present invention and do not constitute a limitation on the protection scope of the present invention.

As shown in Figures 1-5, this embodiment provides an effective random fault injection method for a memory circuit, and the method steps are as follows:

When extracting faulty nodes in the first step, first analyze the storage netlist, extract all possible faulty circuit nodes of the storage unit through Perl language, and modify the names of all faulty nodes in accordance with the predetermined naming rules to facilitate fault injection. In the original netlist, randomly selected faulty nodes are located, and a new faulty node file is generated. Each line in the file is a faulty node. The method for selecting the faulty node in the second step is as follows: randomly select p faulty nodes from the faulty node file, and determine the position of the randomly selected node in the original netlist by naming rules, and inject a resistor with random resistance; if the node is selected If the number is p, the resistance values of the injection resistors are r ₁ … _{r p} , and each resistance value is random. The resistors injected in the second step are named R _fau1 …R _faup , which correspond to two port nodes and random resistance _values _{r 1} …r p, add the above information to the memory cell module to generate a new memory netlist document.

This embodiment improves on the technical problem of memory fault injection, and innovatively implements an effective random fault injection method for memory. While fault injection, the randomness and comprehensiveness of fault injection are considered. In the memory circuit structure Adding resistance to simulate the circuit defects that may occur in the manufacturing engineering of the circuit, while verifying the effectiveness of the algorithm, it also verifies the fault coverage of the algorithm. The fault injection in this embodiment is performed on the memory spice netlist, which improves the executable of fault injection, enhances the relevance of fault injection in practice, and reduces the complexity of subsequent simulation verification.

Figure 1 shows a flow chart of the random fault injection method of this embodiment. As shown in the figure, three steps are required to complete the random fault injection, including fault node extraction, random fault injection, and random fault injection verification. The extraction of faulty nodes includes the location of possible faulty circuit nodes in the memory, extracting all circuit nodes and modifying the names of circuit nodes, generating a circuit node list file, and each line in the file corresponds to a circuit node to complete the extraction of faulty nodes; random fault injection is the implementation The core module of the example includes the selected fault nodes randomly, the number of selected nodes is random, and the injection resistance value is random; different fault nodes at p (p>0) are randomly selected in the node file, and the resistance value of each node is injected Random; as shown in Figure 1, when randomly selecting different nodes at p, each time the selection is completed, it is necessary to determine whether the failure node is the same as the previous selection. If it is the same, select the node again, if it is different, continue, and inject at the selected node Random resistance resistors, and then determine whether the selected p nodes have all completed resistance injection (for example, randomly select 4 nodes, first determine that these 4 nodes do not have the same node, and then determine whether to inject four random resistance resistors) Finally, a new memory netlist is generated to achieve random fault injection; the last is to verify the feasibility of fault injection, generate a BIST test circuit based on the memory test algorithm, test the original netlist and the netlist after fault injection, and compare the two tests The waveform diagram verifies the feasibility of fault injection.

This embodiment completes fault injection based on the memory storage unit. Figure 2 is a structure diagram of the static random access memory. As shown in the figure, a complete memory system includes an address decoder, a timing control unit, a column selector, a sensitive amplifier, and a data buffer unit. And a storage array, where the storage array is a plurality of neatly arranged storage units. As shown in the figure, the circuit structure diagram of the storage unit can be seen.

Figure 3 is based on the 6T SRAM circuit node insertion resistance diagram. As shown in the figure, according to the description of the memory netlist file, each MOS device name and port node name are marked. When the circuit node is extracted, the circuit node name is modified. The node is the three ports of each MOS device, so the device name is added before the node name. After the faulty node is selected randomly, the corresponding node location can be located by the device name, as shown in the figure, when the node name is randomly selected as MNPg-b In the case of .bb, the fault injection location can be located at the bb node of the MNPg-b device according to the naming rule, and the resistance at the fault node is injected with a resistance value of r ₁ and a resistor named R _fau1.

Figure 4 is a block diagram of the verification structure after fault injection is completed based on the SRAM example of this embodiment. As shown in the figure, the BIST circuit includes modules such as state machine, address generator, data generator, and algorithm controller, and uses March2 algorithm to generate test vector tests. Memory circuit: The test output is compared with the expected data through a comparator. After the comparison, the tst-done signal jumps to 1. If the comparison data is consistent, the fail-h signal is 0, otherwise it jumps to 1. This experiment is based on a mixed simulation environment to verify the feasibility of the fault injection method. The BIST test circuit is written in Verilog sentences and simulated by VCS. The SRAM to be tested is a cdl netlist and simulated by HSIM.

Figure 5 is based on the random fault injection verification waveform of the 6T SRAM cell. The experimental results are compared through the hybrid simulation test waveform. Among them, (a) is the waveform of the original netlist test result of the memory. Observe the tst-done and fail-h in the figure. After the tst-done jumps to 1, the fail-h signal is always 0, indicating that the circuit test is over and there is no failure; Figure 6 (b) is the same simulation environment, after the random fault is injected Generate the netlist file test result waveform diagram, observe the tst-done and fail-h waveform transitions, and find that when the tst-done signal is still 0, the fail-h signal has jumped to 1, indicating that the circuit is faulty. Further analysis found that the corresponding test step when the waveform jumps is w1r1, and the injected fault node is R _fau1 . The fault manifestation is a conversion failure, which cannot be converted from 0 to 1, which is consistent with the waveform check result of the algorithm, effectively verifying this embodiment The feasibility of the method.

Claims

An effective random fault injection method for a memory circuit is characterized in that the method steps are as follows:

Step 1: Use Perl language to extract all the nodes that may fail, modify the names of all failed nodes, and generate a new file;

Step 2: Randomly select one or more faulty nodes in the node file, and insert random resistors with resistance values at the nodes;

Step 3: After inserting the resistor, a new memory netlist file with random fault injection is generated.
An effective random fault injection method for a memory circuit according to claim 1, characterized in that: when extracting faulty nodes in step one, the memory netlist is first analyzed, and all possible faults in the storage unit are extracted through Perl language. The name of all faulty nodes is modified in accordance with the predetermined naming rules to facilitate the location of randomly selected faulty nodes in the original netlist during fault injection, and a new faulty node file is generated. Each line in the file is a The failed node.
An effective random fault injection method for a memory circuit according to claim 1, wherein the method for selecting faulty nodes in the second step is as follows: randomly selecting p faulty nodes from the faulty node file, and adopting a naming rule Determine the position of randomly selected nodes in the original netlist, and inject resistors with random resistance values; if the selected nodes are p, the injected resistance values are r 1 … r p , and each resistance value is random.
An effective random fault injection method for a memory circuit according to claim 1, wherein the resistors injected in the second step are named R fau1 ... R faup , followed by two port nodes, and a random resistance value r 1 …..r p , add the above information to the memory unit module to generate a new memory netlist file.