CN108766501A - A kind of the storage failure injection design and verification method fault-tolerant with EDAC - Google Patents
A kind of the storage failure injection design and verification method fault-tolerant with EDAC Download PDFInfo
- Publication number
- CN108766501A CN108766501A CN201810549625.1A CN201810549625A CN108766501A CN 108766501 A CN108766501 A CN 108766501A CN 201810549625 A CN201810549625 A CN 201810549625A CN 108766501 A CN108766501 A CN 108766501A
- Authority
- CN
- China
- Prior art keywords
- domain
- data
- verification
- test
- write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention discloses a kind of the storage failure injection designs and verification method fault-tolerant with EDAC, division of labor operation mode carries out different control to the read and write access of data/domain of instruction and verification domain respectively, in test mode, when carrying out read operation to data/domain of instruction, only make the control signal of the read operation in data/commands domain effective, realizes the test read access in data/commands domain；When carrying out read operation to verification domain, only make the control signal of the read operation in verification domain effective, realize the test read access in verification domain, when carrying out direct fault location to data/domain of instruction, only make the control signal of the write operation in data/commands domain effective, when carrying out direct fault location to verification domain, only make the control signal of the write operation in verification domain effective, realize data/commands domain and verifies the Arbitrary Fault injection in domain.The present invention realizes data/commands domain and the verification independent read and write access in domain, it is ensured that memory carries out the testability after fault-tolerant design.
Description
Technical field
The invention belongs to IC design technical fields, and in particular to a kind of storage failure note fault-tolerant with EDAC
Enter design and verification method.
Background technology
SEU (Single-Event-Upset) effect in space environment easily influences digital integrated electronic circuit component, especially
It is memory device, leads to program execution error, so as to cause thrashing.Memory can be located at SoC (System on
Chip) on piece, or its external memory space is used as outside SoC, but Memory Controller is generally placed in SoC.Needle
To the practical application of space environment, in order to improve the capability of resistance to radiation of SoC main storage systems, on-chip memory and chip external memory
It needs to use fault-tolerant Design of Reinforcement, since main storage system is not reproducible, generally use EDAC codings so that miscount mistake greatly absolutely
It can achieve the purpose that correctly to reappear by correcting.Using EDAC coding techniques, it is necessary on the basis of original memory, increase
Add the verification metamemory of redundancy as verification domain.Under normal functioning mode, when carrying out write operation to memory, without sending
Verification member writes data and first passes through the corresponding verification member of EDAC encoders generation, then will write data and verify member respectively while being written
In data/commands domain and verification domain；When carrying out read operation to memory, reads data and corresponding verification member can be simultaneously respectively from number
It,, only will reading if it is error-free to read data into carrying out error detection in EDAC decoders according to being read in/domain of instruction and verification domain
According to processor is returned to, processor is not necessarily to be concerned about the situation of corresponding verification member.Then, under normal functioning mode, verification member
It is transparent to processor.
But the fault-tolerant design of memory needs to ensure the reliability of design by verifying.The method master used at present
If analysis model method, live error data analysis method and fault injection methods etc., wherein direct fault location is reliable to fault-tolerant design
Property verification effective ways, include mainly that software note is wrong, physics note is wrong and simulation note mistake etc..In order to realize to error-tolerance type memory
Purpose that is wrong and observing in real time can be arbitrarily noted, when carrying out fault-tolerant design, it is necessary to specially be designed the wrong structure of note, be met
Subsequent authentication fault-tolerant architecture correctness carries out the demand of direct fault location and verification.
It is many about how the patent and documents and materials that carry out direct fault location and verification, such as " one kind being used for single-particle
The fault simulation system and analysis method of overturning " proposes the single-particle inversion in a kind of large scale integrated circuit SRAM type FPGA
Fault simulation system and analysis method, by the way of software and hardware combining, pass through host computer and control panel interaction complete therefore
Barrier injection and fault detect, realize the verification of SRAM type FPGA fault-tolerant abilitys.But it is wrong how to carry out note based on fault-tolerant architecture
The data of design is simultaneously few, about TMR structure note the document of wrong design, such as " TMR direct fault locations are ground with verification method
Study carefully and realize " (computer measurement and control).The design of note mistake and verification for especially how realizing error-tolerance type memory, through retrieval
Related patents and document, it is not yet found that the method for solving the problems, such as this.
Invention content
In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is that providing a kind of with EDAC
Fault-tolerant storage failure injection design and verification method, in test mode, data/commands domain and verification domain can realize independence
Read-write operation, and read and write data/commands and verification member be by corresponding registers read-write completion, can appoint
While meaning note is wrong, the purpose that can be observed in real time of data/commands and verification member is realized, it is ensured that memory carries out fault-tolerant design
Testability later.
The present invention uses following technical scheme：
It is a kind of with EDAC it is fault-tolerant storage failure injection design and verification method, the division of labor operation mode respectively to data/
The read and write access of domain of instruction and verification domain carries out different control, in test mode, read operation is carried out to data/domain of instruction
When, only make the control signal of the read operation in data/commands domain effective, realizes the test read access in data/commands domain；To verifying domain
Carry out read operation when, only make the control signal of the read operation in verification domain effective, realize verification domain test read access, to data/
When domain of instruction carries out direct fault location, only make the control signal of the write operation in data/commands domain effective, failure note is carried out to verification domain
It is fashionable, only make the control signal of the write operation in verification domain effective, realizes data/commands domain and verify the Arbitrary Fault note in domain
Enter.
Specifically, according to operating mode, the read and write access in data/commands domain and verification domain is specific as follows：
Under normal mode of operation, data/commands domain is consistent with the control signal of verification domain read and write access, control sequential, number
It is corresponded according to/domain of instruction and verification domain；Under test pattern, data/commands domain and verification domain need independent read and write access
Control.
Further, under normal mode of operation, control signal controls data/commands domain and verifies the read-write in domain simultaneously；?
Under test pattern, if it is test data/domain of instruction, then read-write control signal is effective to the access of data/domain of instruction, right
The read and write access controller in verification domain will be set in vain；Domain is verified if it is test, then read-write control signal is to verification domain
Access is effective, will be set in vain to the read and write access controller of data/domain of instruction.
Specifically, being specially to data/domain of instruction progress read operation：
In test mode, it is first configured to the pattern tested data/commands, makes the read operation in data/commands domain
Control signal it is effective, shielding verification domain read operation control signal, hair read certain address read access operation, corresponding address
Data/commands carry out read operation back to test reading according in register test_rdata, then to the test_rdata registers,
Realize the test read access in data/commands domain.
Specifically, being specially to the progress read operation of verification domain：
In test mode, it is first configured to verification domain test pattern, keeps the control signal of the read operation in verification domain effective, is shielded
The control signal of the read operation in data/commands domain is covered, hair reads the read access operation of certain address, and the verification member of corresponding address can return
Read operation is carried out into test read check member register test_redac, then to the test_redac registers, realizes verification domain
Test read access.
Specifically, being specially to data/domain of instruction progress write operation：
In test mode, it is first configured to the pattern tested data/commands, makes the write operation in data/commands domain
Control signal it is effective, shielding verification domain write operation control signal, the data that will be write first be written test writes data register
In device test_wdata, hair writes the access operation of certain address later, and the data in test_wdata registers will be written accordingly
In the data/commands domain of location, and the verification member corresponded in verification domain maintains initial value constant, reads test_wdata registers
Operation confirms the consistency of write-in data, realizes that the arbitrary note in data/commands domain is wrong.
Specifically, being specially to verification domain progress write operation：
In test mode, it is first configured to verification domain test pattern, makes the control signal of the write operation in verification domain, shields number
According to the control signal of the write operation of/domain of instruction, test write check member register test_wedac is first written in the verification member that will be write
In, hair writes the access operation of certain address later, and the data in test_wedac registers will be written in the verification domain of corresponding address,
Value in corresponding data/domain of instruction remains unchanged, and read operation is carried out to test_wedac registers, confirms the one of write-in verification member
Cause property realizes that the arbitrary note in verification domain is wrong.
Specifically, selection data/commands domain is specially to carrying out direct fault location with memory fault-tolerant EDAC：
It staggers the time, needs to configure as data/commands domain test pattern, when known current number when carrying out note to data/domain of instruction
According to the value of corresponding address in/domain of instruction, in the data write-in test_wdata registers that will be corrected mistakes, initiate to appropriate address
Write operation initiates once to read the read operation of identical address if the value of corresponding address is unknown in data/commands domain
Data be recorded in test_rdata registers, take out the value in test_rdata registers later, and corrected mistakes, be written
In test_wdata registers, initiating write operation will be in error injection to corresponding address.
Further, selection check domain is specially to carrying out direct fault location with memory fault-tolerant EDAC：
It staggers the time when carrying out note to verification domain, the register of operation is test_wedac and test_redac, need not be school
It tests domain and distributes additional address space, it is identical as the access address in data/commands domain to the address access for verifying domain, only
Under different test patterns, the storage region of access is different.
Specifically, in the design and verification method, corresponding password is designed to the write access of testing and control register and is posted
First corresponding password is written into corresponding password register in storage, and password is correct, is just carried out to testing and control register primary
Operation.
Compared with prior art, the present invention at least has the advantages that：
The present invention a kind of the storage failure injection design and verification method, division of labor operation mode fault-tolerant with EDAC is right respectively
The read and write access in data/commands domain and verification domain carries out different control, in test mode, reads data/domain of instruction
When operation, only make the control signal of the read operation in data/commands domain effective, realizes the test read access in data/commands domain；To school
When testing domain progress read operation, only makes the control signal of the read operation in verification domain effective, realize the test read access in verification domain, logarithm
When carrying out direct fault location according to/domain of instruction, only make the control signal of the write operation in data/commands domain effective, verification domain is carried out therefore
When barrier injection, only make the control signal of the write operation in verification domain effective, realize data/commands domain and verifies the Arbitrary Fault in domain
Injection.Data/commands domain and the verification independent read and write access in domain are realized, the data/commands and verification member of read-write pass through
The read-write of corresponding registers is completed, while arbitrarily can note mistake, data/commands is realized and verifies can seeing in real time for member
The purpose of survey, it is ensured that memory carries out the testability after fault-tolerant design, and acquired effect is as follows：
By the way that the mode configuration register of user-programmable is arranged and carries out corresponding structure design, ensure that normal
Under operating mode, the read and write access control in data/commands domain and verification domain is simultaneously, it is ensured that data/commands and verification are first
The read and write access control in consistency, and in test mode, data/commands domain and verification domain is independent again, according to currently matching
What is set is test data/domain of instruction, or test verification domain, and read and write access control signal only has the storage domain of current-configuration
Effect is, it can be achieved that the note respectively to data/commands domain and verification domain is wrong.
Write data register test_wdata and the first register test_wedac of test verification are tested by design, is realized
In test mode, tester is by respectively can arbitrarily note data/domain of instruction, verification domain register manipulation
Mistake, direct fault location mode are simple and clear.
By designing test reading according to register test_rdata and test read check member register test_redac, realize
In test mode, tester, can real-time observed data/domain of instruction, verification domain by the read access to corresponding registers
Note mistake situation.
Using password register, when correct password is written into password register, testing and control deposit could be opened
Writing for device is enabled, improves the reliability of test design structure.
Below by drawings and examples, technical scheme of the present invention will be described in further detail.
Description of the drawings
Fig. 1 is the read and write access control structure schematic diagram that the present invention has the fault-tolerant memories of EDAC.
Specific implementation mode
The present invention provides a kind of the storage failure injection designs and verification method fault-tolerant with EDAC, for independent real
The now direct fault location to the data/commands domain of error-tolerance type memory and verification domain and verification.
The present invention a kind of the storage failure injection design and verification method fault-tolerant with EDAC, include the following steps：
S1, the read and write access for data/commands domain and verification domain, operation mode of dividing the work carry out different control respectively；
In the normal mode of operation, data/commands domain is consistent with the control signal of verification domain read and write access, control sequential
, it need not be that independent access control signal is arranged in verification domain, also need not be that additional access address is distributed in verification domain, number
It is one-to-one according to/domain of instruction and verification domain, uses address identical with data/commands domain.
In test mode, data/commands domain and verification domain need independent read and write access control.
In fact, the control signal of data/commands domain and verification domain read and write access can also be a set of, in normal work mould
Under formula, these control signals control data/commands domain and verify the read-write in domain simultaneously；In test mode, if it is test number
According to/domain of instruction, then read-write control signal is effective to the access of data/domain of instruction, to verifying the read and write access controller in domain
It is invalid to be set to；Domain is verified if it is test, then read-write control signal is effective to the access for verifying domain, to data/refer to
Enable the read and write access controller in domain that will be set in vain.
S2, in test mode is first configured to test data/commands when carrying out read operation to data/domain of instruction
Pattern, it is therefore an objective to keep the control signal of the read operation in data/commands domain effective, and shield verification domain read operation control letter
Number, hair reads the read access operation of certain address later, and the data/commands of corresponding address can return to test reading according to register
In test_rdata, then read operation is carried out to the test_rdata registers, realizes the test read access in data/commands domain；
When carrying out read operation to verification domain, it is first configured to verification domain test pattern, it is therefore an objective to make the read operation in verification domain
It is effective to control signal, and shields the control signal of the read operation in data/commands domain, hair reads the read access operation of certain address, corresponding
The verification member of address can be returned in test read check member register test_redac, then be carried out to the test_redac registers
The test read access in verification domain is realized in read operation；
S3, in test mode is first configured to test data/commands when carrying out write operation to data/domain of instruction
Pattern, it is therefore an objective to keep the control signal of the write operation in data/commands domain effective, and shield verification domain write operation control letter
Number, the data that will be write later are first written in test write data register test_wdata, and hair writes the access operation of certain address,
Data in test_wdata registers will be written in the data/commands domain of corresponding address, and correspond to the verification member in verification domain
It maintains initial value constant, read operation can be carried out to test_wdata registers, the consistency of write-in data be confirmed, to data/refer to
Enable the arbitrary note that the test write operation in domain realizes data/commands domain wrong；
When carrying out write operation to verification domain, it is first configured to verification domain test pattern, it is therefore an objective to make the write operation in verification domain
It is effective to control signal, and shields the control signal of the write operation in data/commands domain, the verification member that will be write first is written test and writes school
It tests in first register test_wedac, hair writes the access operation of certain address later, and the data in test_wedac registers will be write
In the verification domain for entering corresponding address, and the value in corresponding data/domain of instruction remains unchanged, can to test_wedac registers into
Row read operation confirms the consistency of write-in verification member, and the arbitrary note that the test write operation to verifying domain realizes verification domain is wrong；
S4, to carrying out direct fault location with the fault-tolerant memories of EDAC when, can select be to data/domain of instruction and/or
It is wrong to verify domain note；
It staggers the time, needs to configure as data/commands domain test pattern, if it is known that at present when carrying out note to data/domain of instruction
The value of corresponding address in data/commands domain, the data that will be corrected mistakes are written in test_wdata registers, initiate to appropriate address
Write operation can first be initiated once to identical address if the value of corresponding address is unknown in data/commands domain
The data of read operation, reading can be recorded in test_rdata registers, take out the value in test_rdata registers later, and
It is corrected mistakes, is written in test_wdata registers, initiating write operation will be in error injection to corresponding address.
When to verification domain carry out note stagger the time, flow is consistent, the register only operated be test_wedac and
test_redac.It should be noted that need not be verification domain distribute additional address space, to verify domain address access with
The access address in data/commands domain is identical, and only under different test patterns, the storage region of access is different；
S5, based on the considerations of reliability, the system failure caused by artificial maloperation and space radiation environment in order to prevent,
Corresponding password register is specially designed to the write access of testing and control register, i.e., it must be first into corresponding password register
Corresponding password is written, password is correct, could carry out once-through operation to testing and control register, improve test design structure
Reliability.
The present invention is based on the design structures of such direct fault location so that data/commands domain and verification domain are with independent
Access path, arbitrary note mistake can be distinguished by realizing data/commands domain and verification domain, and it is equal to have reached data/commands domain and verification domain
Purpose with testability.Meanwhile data/commands domain and verification domain in data can respectively by read test_rdata and
Test_redac registers check data/commands domain and verify the note mistake situation in domain, realize the purpose that can be observed in real time.
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.The present invention being described and shown in usually here in attached drawing is real
Applying the component of example can be arranged and be designed by a variety of different configurations.Therefore, the present invention to providing in the accompanying drawings below
The detailed description of embodiment be not intended to limit the range of claimed invention, but be merely representative of the selected of the present invention
Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are obtained without creative efforts
The every other embodiment obtained, shall fall within the protection scope of the present invention.
Referring to Fig. 1, being the read and write access control structure with memory fault-tolerant EDAC.Under normal functioning mode,
When system sends out a write operation to memory, writes data sys_data and first pass through the corresponding verification member of Edac coding generations
Wedac, the write enable signal Wen that system is sent out by data/commands domain write enabled Wen_data and verify domain write it is enabled
Wen_edac signals are set to effectively simultaneously, and sys_data and wedac is respectively written into data/commands domain and verification domain simultaneously；When
When system sends out a read operation to memory, the reading in data/commands domain is enabled Oen_ by the reading enable signal Oen that system is sent out
The reading in data and verification domain enables Oen_edac signals and is set to simultaneously effectively, is read simultaneously from data/commands domain and verification domain respectively
Go out data rdata and verification member redac, and carry out Edac decodings, the data after decoding result and correcting will return to system.
In test mode, if being configured to test data/domain of instruction, when carrying out test write operation, the data of write-in
Carry out self-test write data register test_wdata, because of only test data/domain of instruction, verification domain remains unchanged, without carrying out
Edac is encoded, and the write enable signal in only data/commands domain is effective, and verify domain writes enabled shielded；It is being tested
When read operation, system reads enable signal Oen and is set to the reading enable signal Oen_data in data/commands domain effectively, verifies domain
It reads enable signal to be shielded, test reading will be written according in register test_rdata in the data of reading.
In test mode, if being configured to test verification domain, when carrying out write operation, the data of write-in are carried out self-test and are write
First register test_wedac, the Edac coding module of verification does not enable, and only verifies the write enable signal Wen_edac in domain
Effectively, writing for data/commands domain enables to be shielded；When carrying out test read operation, system, which reads enable signal Oen, will verify domain
It reads enable signal Oen_edac to be set to effectively, the reading enable signal in data/commands domain will be shielded, and the data of reading survey write-in
In the first register test_redac of academic probation verification.
The present invention has been applied in the SoC of a compatible SPARC V8 structure fault-tolerant processors, the SoC main storage systems
Memory Controller has used direct fault location design structure and verification method in the present invention.When memory in test mode
When, data/commands domain and verification domain can realize independent read-write operation, and the data/commands and verification member read and write are logical
Cross to corresponding registers read-write complete, while arbitrarily can note mistake, realize data/commands and verification member can be real-time
The purpose of observation, it is ensured that memory carries out the testability after fault-tolerant design.
The above content is merely illustrative of the invention's technical idea, and protection scope of the present invention cannot be limited with this, every to press
According to technological thought proposed by the present invention, any change done on the basis of technical solution each falls within claims of the present invention
Protection domain within.
Claims (10)
1. a kind of the storage failure injection design and verification method fault-tolerant with EDAC, which is characterized in that division of labor operation mode point
It is other to data/domain of instruction and verification domain read and write access carry out different control, in test mode, to data/domain of instruction into
When row read operation, only make the control signal of the read operation in data/commands domain effective, realizes the test read access in data/commands domain；
When carrying out read operation to verification domain, only make the control signal of the read operation in verification domain effective, realize the test read access in verification domain,
When carrying out direct fault location to data/domain of instruction, only make the control signal of the write operation in data/commands domain effective, to verification domain into
When row direct fault location, only make the control signal of the write operation in verification domain effective, realize data/commands domain and verifies the arbitrary of domain
Direct fault location.
2. a kind of the storage failure injection design and verification method fault-tolerant with EDAC according to claim 1, special
Sign is, according to operating mode, the read and write access in data/commands domain and verification domain is specific as follows：
Under normal mode of operation, data/commands domain is consistent with the control signal of verification domain read and write access, control sequential, data/refer to
Domain and verification domain is enabled to correspond；Under test pattern, data/commands domain and verification domain need independent read and write access control.
3. a kind of the storage failure injection design and verification method fault-tolerant with EDAC according to claim 1 or 2,
It is characterized in that, under normal mode of operation, control signal controls data/commands domain and verifies the read-write in domain simultaneously；In test pattern
Under, if it is test data/domain of instruction, then read-write control signal is effective to the access of data/domain of instruction, to verification domain
Read and write access controller will be set in vain；Domain is verified if it is test, then read-write control signal is to have to the access for verifying domain
Effect, the read and write access controller of data/domain of instruction will be set in vain.
4. a kind of the storage failure injection design and verification method fault-tolerant with EDAC according to claim 1, special
Sign is that carrying out read operation to data/domain of instruction is specially：
In test mode, it is first configured to the pattern tested data/commands, makes the control of the read operation in data/commands domain
Signal processed is effective, and the control signal of the read operation in shielding verification domain, hair reads the read access operation of certain address, the number of corresponding address
Read operation is carried out according in register test_rdata, then to the test_rdata registers back to test reading according to/instruction, it is real
The test read access in existing data/commands domain.
5. a kind of the storage failure injection design and verification method fault-tolerant with EDAC according to claim 1, special
Sign is that carrying out read operation to verification domain is specially：
In test mode, it is first configured to verification domain test pattern, keeps the control signal of the read operation in verification domain effective, shields number
According to the control signal of the read operation of/domain of instruction, hair reads the read access operation of certain address, and the verification member of corresponding address, which can return to, to be surveyed
In the first register test_redac of academic probation verification, then read operation is carried out to the test_redac registers, realizes the survey in verification domain
Academic probation accesses.
6. a kind of the storage failure injection design and verification method fault-tolerant with EDAC according to claim 1, special
Sign is that carrying out write operation to data/domain of instruction is specially：
In test mode, it is first configured to the pattern tested data/commands, makes the control of the write operation in data/commands domain
Signal processed is effective, and test write data register is first written in the control signal of the write operation in shielding verification domain, the data that will be write
In test_wdata, hair writes the access operation of certain address later, and corresponding address will be written in the data in test_wdata registers
Data/commands domain in, and correspond to verification domain in verification member maintain initial value it is constant, reading behaviour is carried out to test_wdata registers
Make, confirm the consistency of write-in data, realizes that the arbitrary note in data/commands domain is wrong.
7. a kind of the storage failure injection design and verification method fault-tolerant with EDAC according to claim 1, special
Sign is that carrying out write operation to verification domain is specially：
In test mode, it is first configured to verification domain test pattern, makes the control signal of the write operation in verification domain, shielding data/
The control signal of the write operation of domain of instruction, the verification member that will be write first are written in test write check member register test_wedac,
Hair writes the access operation of certain address later, and the data in test_wedac registers will be written in the verification domain of corresponding address, right
It answers the value in data/commands domain to remain unchanged, read operation is carried out to test_wedac registers, confirm the consistent of write-in verification member
Property, realize that the arbitrary note in verification domain is wrong.
8. a kind of the storage failure injection design and verification method fault-tolerant with EDAC according to claim 1, special
Sign is, selects data/commands domain to being specially with the fault-tolerant memory progress direct fault locations of EDAC：
It staggers the time, needs to configure as data/commands domain test pattern when carrying out note to data/domain of instruction, when known current data/refer to
The value of corresponding address in domain is enabled, in the data write-in test_wdata registers that will be corrected mistakes, initiation writes behaviour to appropriate address
Make, if the value of corresponding address is unknown in data/commands domain, initiates once to the read operation of identical address, the number of reading
According to being recorded in test_rdata registers, the value in test_rdata registers is taken out later, and corrected mistakes, be written
In test_wdata registers, initiating write operation will be in error injection to corresponding address.
9. a kind of the storage failure injection design and verification method fault-tolerant with EDAC according to claim 8, special
Sign is that selection check domain is specially to carrying out direct fault location with memory fault-tolerant EDAC：
It staggers the time when carrying out note to verification domain, the register of operation is test_wedac and test_redac, need not be verification domain
Additional address space is distributed, it is identical as the access address in data/commands domain to the address access for verifying domain, only not
Under same test pattern, the storage region of access is different.
10. a kind of the storage failure injection design and verification method fault-tolerant with EDAC according to claim 1, special
Sign is, in the design and verification method, corresponding password register is designed to the write access of testing and control register, first to
Corresponding password is written in corresponding password register, password is correct, just carries out once-through operation to testing and control register.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810549625.1A CN108766501B (en) | 2018-05-31 | 2018-05-31 | Design and verification method for fault injection of storage with EDAC fault tolerance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810549625.1A CN108766501B (en) | 2018-05-31 | 2018-05-31 | Design and verification method for fault injection of storage with EDAC fault tolerance |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108766501A true CN108766501A (en) | 2018-11-06 |
| CN108766501B CN108766501B (en) | 2020-06-30 |
Family
ID=64001279
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810549625.1A Active CN108766501B (en) | 2018-05-31 | 2018-05-31 | Design and verification method for fault injection of storage with EDAC fault tolerance |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108766501B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109669802A (en) * | 2018-11-13 | 2019-04-23 | 北京时代民芯科技有限公司 | A kind of configurable memory verifying system for EDAC verifying |
| CN111725893A (en) * | 2020-06-19 | 2020-09-29 | 西安微电子技术研究所 | Embedded power health detection and management system |
| CN112613254A (en) * | 2020-11-30 | 2021-04-06 | 天津飞腾信息技术有限公司 | System and method for verifying fault injection of mirror image control module in processor |
| WO2021175099A1 (en) * | 2020-03-03 | 2021-09-10 | 南京邮电大学 | Effective random fault injection method for memory circuit |
| CN114756423A (en) * | 2022-06-16 | 2022-07-15 | 长沙驭电信息技术有限公司 | Software and hardware combined fault injection device and method for EDAC (electronic design automation) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5278847A (en) * | 1990-12-28 | 1994-01-11 | General Electric Company | Fault-tolerant memory system with graceful degradation |
| CN105185413A (en) * | 2015-09-24 | 2015-12-23 | 中国航天科技集团公司第九研究院第七七一研究所 | Automatic verification platform and method for on-chip memory management unit fault-tolerant structure |
| CN106656663A (en) * | 2016-12-07 | 2017-05-10 | 中国电子产品可靠性与环境试验研究所 | Bit flip fault injection method and system for CAN (Controller Area Network) bus data link layer |
-
2018
- 2018-05-31 CN CN201810549625.1A patent/CN108766501B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5278847A (en) * | 1990-12-28 | 1994-01-11 | General Electric Company | Fault-tolerant memory system with graceful degradation |
| CN105185413A (en) * | 2015-09-24 | 2015-12-23 | 中国航天科技集团公司第九研究院第七七一研究所 | Automatic verification platform and method for on-chip memory management unit fault-tolerant structure |
| CN106656663A (en) * | 2016-12-07 | 2017-05-10 | 中国电子产品可靠性与环境试验研究所 | Bit flip fault injection method and system for CAN (Controller Area Network) bus data link layer |
Non-Patent Citations (1)
| Title |
|---|
| 胡鸣姜明华: "性能优化的双盘非同时故障容错布局分析", 《计算机工程与科学》 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109669802A (en) * | 2018-11-13 | 2019-04-23 | 北京时代民芯科技有限公司 | A kind of configurable memory verifying system for EDAC verifying |
| WO2021175099A1 (en) * | 2020-03-03 | 2021-09-10 | 南京邮电大学 | Effective random fault injection method for memory circuit |
| CN111725893A (en) * | 2020-06-19 | 2020-09-29 | 西安微电子技术研究所 | Embedded power health detection and management system |
| CN112613254A (en) * | 2020-11-30 | 2021-04-06 | 天津飞腾信息技术有限公司 | System and method for verifying fault injection of mirror image control module in processor |
| CN112613254B (en) * | 2020-11-30 | 2022-01-25 | 飞腾信息技术有限公司 | System and method for verifying fault injection of mirror image control module in processor |
| CN114756423A (en) * | 2022-06-16 | 2022-07-15 | 长沙驭电信息技术有限公司 | Software and hardware combined fault injection device and method for EDAC (electronic design automation) |
| CN114756423B (en) * | 2022-06-16 | 2022-09-20 | 长沙驭电信息技术有限公司 | Software and hardware combined fault injection device and method for EDAC (electronic design automation) |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108766501B (en) | 2020-06-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108766501A (en) | A kind of the storage failure injection design and verification method fault-tolerant with EDAC | |
| US7437692B2 (en) | Memory debugger for system-on-a-chip designs | |
| CN100495357C (en) | Method and apparatus for processing error information and injecting errors in a processor system | |
| US6539503B1 (en) | Method and apparatus for testing error detection | |
| CN105185413B (en) | For the automatic verification platform and method of on piece MMU memory management unit fault-tolerant architecture | |
| CN109901956A (en) | The system and method for memory integrated testability | |
| DE19952272A1 (en) | System with test device for testing components embedded on integrated circuit (IC), such as system-chip circuit uses hardware in IC itself with only minimum additional hardware needed for testing process | |
| US6424926B1 (en) | Bus signature analyzer and behavioral functional test method | |
| US9437327B2 (en) | Combined rank and linear address incrementing utility for computer memory test operations | |
| CN103871479B (en) | In-line memory tests system | |
| CN109801666A (en) | The test device of memory chip in a kind of hybrid circuit | |
| US7730369B2 (en) | Method for performing memory diagnostics using a programmable diagnostic memory module | |
| CN108491296B (en) | Method for testing single event upset section of microprocessor | |
| Alderighi et al. | A tool for injecting SEU-like faults into the configuration control mechanism of Xilinx Virtex FPGAs | |
| US5442640A (en) | Test and diagnosis of associated output logic for products having embedded arrays | |
| US6587975B2 (en) | Semiconductor test apparatus and method | |
| US9672094B1 (en) | Interconnect circuitry fault detection | |
| CN103871478B (en) | In-line memory tests system | |
| CN111128289B (en) | Scan chain technique and method for utilizing scan chain structure | |
| Gruwell | High-speed programmable FPGA configuration memory access using JTAG | |
| US11069422B1 (en) | Testing multi-port array in integrated circuits | |
| CN110377924A (en) | Hard error simulation and its use | |
| Zabolotny et al. | FPGA-related development for CBM DAQ | |
| RU70720U1 (en) | AUTOMATED DIAGNOSTIC SYSTEM FOR DIGITAL DEVICES | |
| US11657887B2 (en) | Testing bit write operation to a memory array in integrated circuits |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |