CN109801666A - The test device of memory chip in a kind of hybrid circuit - Google Patents
The test device of memory chip in a kind of hybrid circuit Download PDFInfo
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- CN109801666A CN109801666A CN201910064323.XA CN201910064323A CN109801666A CN 109801666 A CN109801666 A CN 109801666A CN 201910064323 A CN201910064323 A CN 201910064323A CN 109801666 A CN109801666 A CN 109801666A
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Abstract
The test device of memory chip, can be achieved at the same time fault location and diagnosis in a kind of hybrid circuit of the present invention；It includes built-in self-test circuit and bus complexing circuit；Built-in self-test circuit and bus complexing circuit are arranged on master control protocol chip；Built-in self-test circuit connects the selection signal port of bus complexing circuit, and built-in self-test circuit connects bus complexing circuit with test pattern data bus by test pattern control bus, test pattern address bus；Master control protocol chip further includes functional memory controller；The control port of the control bus connection memory chip of master control protocol chip, the data port of the data/address bus connection memory chip of master control protocol chip, the address port of the address bus connection memory chip of master control protocol chip；The output data port of the output data bus connection memory chip of master control protocol chip；Built-in self-test circuit and functional memory controller read the data of storage core on piece by output data bus.
Description
Technical field
The invention belongs to memory chip the field of test technology；More particularly to a kind of survey of memory chip in hybrid circuit
Trial assembly is set.
Background technique
Hybrid-intergated-circuit technique is widely used in due to the features such as its packing density is big, high reliablity, good electrical property
The numerous areas such as computer, automobile, communication and space flight and aviation.However, how for the storage core in hybrid circuit form
Piece carries out effective high spreadability test, to examine the packaging technology of hydrid integrated circuit to lack the manufacture that memory introduces
It falls into, is that circuit test Qualify Phase suffers from a problem that.
MBIST (Memory Build in Self Test) is industry approval for the excellent of single-chip embedded memory
Elegant test Solution, but not can be used directly in hydrid integrated circuit, for hybrid circuit memory chip, it is then more
It is tested by the way of function read and write access in traditional sense.However, which asking there are the following aspects
Topic: firstly, function access mode is realized by way of memory write associated control registers, control sequential is complex,
Test vector generation difficulty is big, and the judgement for reading result to memory is not intuitive；Second, the specific structure of memory determines it
There are a variety of dependent failure modes such as fixation, coupling, address decoding, and function access is limited to the function of processor or main controller
Behavior, it is difficult to the test vector for having higher test coverage is generated according to special algorithm for the fault type of memory,
Test coverage is insufficient；Third, the exploitation of function testing vector and debugging are more difficult, and testing time and testing cost are higher.
Furthermore functional test access mode is difficult to carry out fault location and diagnosis to dead-file.
Summary of the invention
The present invention provides a kind of self-test devices of hybrid circuit memory chip；The device can be achieved at the same time failure
Positioning and diagnosis.
The technical scheme is that in a kind of hybrid circuit memory chip test device, including built-in self-test
Circuit and bus complexing circuit；The built-in self-test circuit and bus complexing circuit are arranged on master control protocol chip；It is described
Built-in self-test circuit connects the selection signal port of bus complexing circuit, and built-in self-test circuit is controlled total by test pattern
Line, test pattern address bus connect bus complexing circuit with test pattern data bus；The master control protocol chip further includes
Functional memory controller, functional memory controller pass through functional mode control bus, functional mode address bus and function
Mode data bus connects bus complexing circuit；The control terminal of the control bus connection memory chip of the master control protocol chip
Mouthful, the data port of the data/address bus connection memory chip of master control protocol chip, the address bus connection of master control protocol chip
The address port of memory chip；The output data end of the output data bus connection memory chip of the master control protocol chip
Mouthful；The built-in self-test circuit and functional memory controller read the number of storage core on piece by output data bus
According to.
Further, the features of the present invention also characterized in that:
Wherein built-in self-test circuit includes BIST controller, and BIST controller connects comparator, and comparator reads storage
Data on device chip；BIST controller interconnects diagnostor, and diagnostor carries out diagnosis positioning to the memory chip of failure,
And export diagnostic data；The BIST controller generates test and excitation and is sent to memory chip to be measured.
The data for the memory chip that wherein comparator will acquire are compared with expected data, and generate Tag memory
The test failure mark of test result.
Wherein test and excitation includes that memory control test and excitation, storage address test and excitation and memory write data survey
Examination excitation.
Wherein BIST kernel also obtains test starting signal, and exports test end mark.
Wherein bus complexing circuit obtains functional mode memory control signal and test pattern memory control signal simultaneously
Output storage controls signal, obtains functional mode memory address signal and the output storage of test pattern memory address signal
Device address signal obtains functional mode memory data signal and test pattern memory data signal output storage data letter
Number.
Wherein memory to be measured obtains memory control signal, memory address signal and memory data signal.
Compared with prior art, the beneficial effects of the present invention are: test device provided by the invention, control operation letter
Single, Self -adaptive is easy, test coverage is high, while can be realized the validity test approach of fault location and diagnosis, to realize
Test to hydrid integrated circuit internal embedded memory chip.The device starts test pattern by external, is controlled by BIST
Device processed generates test and excitation, and the height for being directed to memory is realized by the access interface of BIST controller and memory chip to be measured
Spreadability test, external resource expense is small, and control is simple, and is by test completion marking signal and test failure marking signal
It can be from the test result of external directly Tag memory.
Test device provided by the invention, structure control is simple, can realize in meaning and deposit to hybrid circuit mounting completely
The built-in self-test and fault diagnosis of reservoir position；Using the industry mainstream testing algorithm for being directed to memory, can be realized to depositing
The high spreadability of the various failures of reservoir is tested；Using functional memory bus interface, the external connection of memory is simplified, is reduced
Test cost；The test of hybrid circuit built-in storage chip is realized by built-in self-test mode, Self -adaptive is easy, and is surveyed
Try vector small scale.The device is suitable for the plug-in memory test of SIP, 3DIC and board-level circuit.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of one embodiment of the invention；
Fig. 2 is the structure chart of built-in self-test circuit in the present invention；
Fig. 3 is the structure chart of bus complexing circuit in the present invention.
Specific embodiment
Technical solution of the present invention is further illustrated in the following with reference to the drawings and specific embodiments.
The present invention provides a kind of test device of memory chip in hybrid circuit, the device in hybrid circuit using depositing
The characteristics of memory chip and the data interaction of master control protocol chip, built-in self-test circuit is designed in hybrid circuit main control chip,
And performance data, control bus are multiplexed to realize the test access to memory chip, which mainly includes built-in
Self testing circuit and bus complexing circuit.
As shown in Figure 1, the device includes built-in self-test circuit, functional memory controller and bus complexing circuit, and
Built-in self-test circuit, functional memory controller and bus complexing circuit are arranged on master control protocol chip；Simultaneously it is built-in from
Test circuit is not arranged on the same chip with memory chip to be tested.
Wherein built-in self-test circuit passes through test pattern control bus, test pattern data bus and test pattern address
Bus connects bus complexing circuit；Wherein functional memory control passes through functional mode control bus, functional mode address bus
Bus complexing circuit is connected with functional mode data/address bus；Bus complexing circuit connects memory chip to be measured by control bus
Control port, bus complexing circuit connects the address port of memory chip to be measured, bus complexing circuit by address bus
The data port of memory chip to be measured is connected by data/address bus.Built-in self-test circuit and functional memory controller are also logical
Cross the data-out port that output data bus connects memory chip to be measured.
As shown in Fig. 2, built-in self-test circuit includes BIST controller, BIST controller connects comparator and diagnostor,
Wherein BIST controller and diagnostor interconnect, i.e., are able to carry out data interaction between BIST controller and diagnostor.BIST
Controller obtains test starting signal, after the triggering of test starting signal, by the control of state of a control machine, according to testing algorithm
Generate test and excitation；Testing algorithm includes MARCH2 or CHECKERBOARD etc., can also according to the read-write sequence of memory and
The customized testing algorithm of fault type tests the high spreadability of the various fault types of memory to realize；Wherein test swashs
It encourages and writes data test excitation including memory control test and excitation, storage address test and excitation and memory, and will test
Excitation is applied to tested memory chip.
Preferably, it is provided with state of a control machine in BIST controller, is additionally provided with control signal generator, address generator
And Data Generator, above three generator are used to generate the test and excitation.
Wherein comparator will read data from memory to be measured and compare with expected data, while generate test failure
Whether mark, test failure mark are correct for Tag memory test result.
Object in view of the BIST Structure is the plug-in memory of chip, and the memory interface of master chip has
There is diversity, which is mapped outside built-in self-test circuit, is increased bus-sharing mechanism, is made built-in self-test circuit
External memory to be tested can be directly accessed by the memory interface of master control protocol chip.The device avoids master control associations
View chip additionally increases a set of test memory interface, and simplifies external interconnection.As shown in figure 3, bus complexing circuit
Purpose be realize function memory access and test memory access channel switch.Under circuit normal mode of operation, selection function memory control
The signal of device processed exports, and the test signal for selecting BIST controller to generate when test pattern, multiple by selection function and test
With the memory bus interface of former control chip, the interface connection type of primary circuit is not changed.Only increase in function access path
Level-one multi-path choice structure is added, the influence to timing performance is very small, and the memory data that memory output port reads back
It does not need to control, the comparator for being directly inputted into built-in self-test is compared, while being sent to functional module.
The interconnection of master control protocol chip and external memory is unaffected in the present apparatus, and realizes memory chip
Efficiently test.Bus-sharing design further reduces test cost, reduces external switch logic bring interconnection difficulty.
In certain 0.5um technique hydrid integrated circuit, using test device of the invention, realize for hybrid circuit
The test of internal storage chip.
The hybrid circuit mainly includes two chip, is respectively as follows: master control protocol chip and the asynchronous single port bi-directional data of 16K
Bus memory.Two chip carries out assembling interconnection by the thick-film technique of hydrid integrated circuit.Wherein memory chip is mark
Quasi- interface, master control protocol chip initiate the access to memory, control, address, number by host interface in the functional mode
It is drawn from chip pin according to bus.
Firstly, the read-write sequence in master control protocol chip for the asynchronous one-port memory of 16K is modeled, using industry
Boundary's mainstream is able to detect MarchC+ the and Checkboard algorithm of most storage failures, carries out setting for MBIST circuit
Meter, this circuit are that the MBIST circuit only includes the state machine kernel that algorithm executes with the tradition MBIST difference designed, compare
With diagnosis etc. BIST control circuit, do not include memory ontology.
In order to be the standard interface of memory chip, while the outside of facilitating chip by standard built-in self-test interface mappings
Connection is designed using the bus-sharing in invention.The MBIST Memory Controller signal for testing signal and function is carried out
Switching, to guarantee under MBIST test pattern, can normally complete the test operation to hybrid circuit inside separate memory,
The memory operation under normal functioning mode is not influenced simultaneously.Bus-sharing inside configuration is multiple multiplexer circuits, test
It is selected with performance data by multiple selector, is interacted communicate with memory by original function access interface later.
So that entire controller external interface does not change.Scheme control, the testing and diagnosing of MBIST circuit pass through JTAG
Realization, test failure and test complement mark, directly in piece External Observation, need exist for infusing by way of with function pin multiplexing
The controller chip port of meaning multiplexing must be the pin of hybrid circuit top layer.
Since this circuit measurand is the memory of single port BDB Bi-directional Data Bus, in BIST circuit design,
The read-write control signal generated with BIST circuit is needed to control the enable signal of memory BDB Bi-directional Data Bus accordingly.
To guarantee memory in reading and write-in, the data flow of BDB Bi-directional Data Bus is correct.In addition, for MBIST circuit
The structure failure defect of itself can then be guaranteed by the design for Measurability technology of inner scanning.
After structure of the invention, the test of hydrid integrated circuit memory chip is significantly simplified, although from surveying
Examination hardware configuration increases some expenses on area, but bring direct effect is reduction of Self -adaptive difficulty, reduces
Test vector scale, it is often more important that, it can realize to 100% address searching the high spreadability test to memory, improve
The test quality of memory.Based on the structure, we are successfully realized to this hydrid integrated circuit on V93K test platform
The test of memory chip has reached expected good result.
Claims (7)
1. the test device of memory chip in a kind of hybrid circuit, which is characterized in that including built-in self-test circuit and bus
Multiplex circuit；
The built-in self-test circuit and bus complexing circuit are arranged on master control protocol chip；
The built-in self-test circuit passes through test pattern control bus, test pattern address bus and test pattern data bus
Connect bus complexing circuit；
The master control protocol chip further includes functional memory controller, and functional memory controller is controlled total by functional mode
Line, functional mode address bus connect bus complexing circuit with functional mode data/address bus；
The control port of the control bus connection memory chip of the master control protocol chip, the data/address bus of master control protocol chip
Connect the data port of memory chip, the address port of the address bus connection memory chip of master control protocol chip；
The output data port of the output data bus connection memory chip of the master control protocol chip；
The built-in self-test circuit and functional memory controller read the number of storage core on piece by output data bus
According to.
2. the test device of memory chip in a kind of hybrid circuit according to claim 1, which is characterized in that in described
Building self testing circuit includes BIST controller, and BIST controller connects comparator, and comparator reads the data of storage core on piece；
BIST controller interconnects diagnostor, and diagnostor carries out diagnosis positioning to the memory chip of failure, and exports diagnostic data；
The BIST controller generates test and excitation and is sent to memory chip to be measured.
3. the test device of memory chip in a kind of hybrid circuit according to claim 2, which is characterized in that the ratio
The data for the memory chip that will acquire compared with device are compared with expected data, and generate the test of Tag memory test result
Failure mark.
4. the test device of memory chip in a kind of hybrid circuit according to claim 2, which is characterized in that described
BIST kernel also obtains test starting signal, and exports test end mark.
5. the test device of memory chip in a kind of hybrid circuit according to claim 2, which is characterized in that the survey
Examination excitation includes that memory control test and excitation, storage address test and excitation and memory write data test excitation.
6. the test device of memory chip in a kind of hybrid circuit according to claim 1, which is characterized in that described total
Line multiplex circuit obtains functional mode memory control signal and test pattern memory control signal and output storage control
Signal obtains functional mode memory address signal and test pattern memory address signal output storage address signal, obtains
Take functional mode memory data signal and test pattern memory data signal output storage data-signal.
7. the test device of memory chip in a kind of hybrid circuit according to claim 6, which is characterized in that be measured to deposit
Reservoir obtains memory control signal, memory address signal and memory data signal.
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| CN110892483A (en) * | 2019-10-17 | 2020-03-17 | 长江存储科技有限责任公司 | Method for testing memory device using limited number of test pins and memory device using the same |
| CN115480960A (en) * | 2021-05-31 | 2022-12-16 | 西安紫光国芯半导体有限公司 | Many-core computing circuit with self-test function, and test method and device thereof |
| CN116521466A (en) * | 2023-07-03 | 2023-08-01 | 武汉芯必达微电子有限公司 | Built-in self-test circuit and method for embedded Flash |
| CN116758968A (en) * | 2023-08-16 | 2023-09-15 | 英诺达(成都)电子科技有限公司 | Built-in self-test method for memory and circuit and chip thereof |
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| CN116758968A (en) * | 2023-08-16 | 2023-09-15 | 英诺达(成都)电子科技有限公司 | Built-in self-test method for memory and circuit and chip thereof |
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