CN203573309U - Testing structure for embedded system memory - Google Patents
Testing structure for embedded system memory Download PDFInfo
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- CN203573309U CN203573309U CN201320761742.7U CN201320761742U CN203573309U CN 203573309 U CN203573309 U CN 203573309U CN 201320761742 U CN201320761742 U CN 201320761742U CN 203573309 U CN203573309 U CN 203573309U
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Abstract
The utility model discloses a testing structure for an embedded system memory. The testing structure is embedded into an SoC (System on a Chip) chip and comprises a CPU (Central Processing Unit), a controller, a system bus, an SPI (Serial Peripheral Interface) and a multiplexer, wherein the CPU is connected with a memory array in the SoC chip through the system bus; the controller is connected with an external tester through the SPI; one input end of the multiplexer is connected with the system bus, and the other input end of the multiplexer is connected with the controller; the output end of the multiplexer is connected with a zero SRAM (Static Random Access Memory); the SPI is an SPI Slave external interface and is provided with four connection wires with the external tester. The testing structure provided by the utility model can be used for testing the memory array in the SoC chip based on software by using the embedded CPU; the SPI is simply realized, the connection wires are fewer, and the communication rate is high, so that the testing time can be saved.
Description
Technical field
The utility model relates to integrated circuit testing field, relates in particular to a kind of test structure of embedded system storer.
Background technology
Because storer is middle-level darker in the design of fairly large integrated circuit, its defect type is different from the defect type of general logic, ATPG(Automatic Test Pattern Generation, automatically test vector produces method) complete memory test solution can not be provided conventionally, and embedded memory test technology (Memory Build in self test circuit, MBIST) can address these problems.BIST(Build In Self Test, embedded self testing circuit) can under the prerequisite of not sacrificing detection quality, provide a kind of memory test solution, under many circumstances, the needs that outside test vector generated to (and ATE machine memory span) and test application time can thoroughly be eliminated or reduce to greatest extent to BIST structure.Designer can carry out embedded memory test circuit in certain design inside, and realizes at full speed and testing easily due to the contiguous tested storer of embedded memory test circuit.
Therefore, current embedded system memory test adopts embedded self-testing structure mostly.Embedded self-testing structure, by testing algorithm Hardware, is embedded into internal system.Basic method is the requirement according to algorithm, and each piece SRAM is carried out to write operation, then reads result and expected result is compared, if in full accord, determine memory test is passed through, otherwise determine memory test failure.But the method is limited to the algorithm of Hardware, can not cover all faults, if a certain inefficacy is not in algorithm requires, will cause erroneous judgement, to producing, impact.
Therefore, those skilled in the art is devoted to develop a kind of test structure of embedded system storer, makes the test of embedded system storer no longer be limited to hardware, only need outside sheet, test by composition memory test procedure to storer.
Utility model content
Because the above-mentioned defect of prior art, technical problem to be solved in the utility model is to provide a kind of test structure of embedded system storer, by using Embedded CPU, making to realize various Test Algorithms for Memory with software becomes possibility for memory test.
For achieving the above object, the utility model provides a kind of test structure of embedded system storer, is embedded in SoC chip, it is characterized in that, comprises CPU, controller, system bus, SPI interface, zero-bit SRAM and MUX; Described CPU is connected with the memory array in described SoC chip by described system bus; Described memory array comprises described zero-bit SRAM, multiple SRAM and ROM, and the address of described zero-bit SRAM in described SRAM array is 0; Described controller is connected with external testing machine by described SPI interface; Described MUX has first input end, the second input end and output terminal, the described first input end of described MUX connects described system bus, described second input end of described MUX connects described controller, and the described output terminal of described MUX connects described zero-bit SRAM.
Further, described controller is time sequence conversion circuit, for SPI sequential is converted to SRAM sequential.
Further, described SPI interface is SPI Slave external interface.
Further, between described SPI Slave external interface and described external testing machine, there are 4 wiring, connect respectively pin SPICS, pin SPICLK, pin MOSI and the pin MISO of described SPI Slave external interface.
Further, described pin SPICS is input pin.
Further, described pin SPICLK is input pin.
Further, described pin MOSI is input pin.
Further, described pin MISO is output pin.
In preferred embodiments of the present utility model, a kind of test structure of embedded system storer of the SoC of being embedded in chip is provided, comprise embedded CPU, controller, system bus, SPI interface, zero-bit SRAM and MUX.CPU is connected with the memory array in SoC chip by system bus; Controller is connected with external testing machine by SPI interface, for SPI sequential is converted to SRAM sequential; Memory array in SoC chip comprises zero-bit SRAM, multiple SRAM and ROM; The first input end of MUX is connected with system bus, and the second input end connects controller, and output terminal is connected to zero-bit SRAM; SPI interface is SPI Slave external interface, between itself and external testing machine, has 4 wiring, connects respectively pin SPICS, pin SPICLK, pin MOSI and the pin MISO of SPI Slave external interface.
As can be seen here, the memory test program that the test structure of embedded system storer of the present utility model is used SPI Slave external interface to send from test machine, and feedback test result, realize and extraneous communicating by letter, this SPI Interface realization is simple, outside connection only needs four lines, and spi bus traffic rate is higher, has saved thus the test duration.In addition, the utility model is by being used Embedded CPU, and making becomes possibility to the test based on software of the memory array in SoC chip, and this test is not limited to the structure of hardware, testing algorithm be can after chip production, write flexibly, out of memory reason locate failure position searched; And can feed back according to test result, once find the inefficacy that some does not cover, can revise flexibly test procedure, search failure cause locate failure position, greatly improve thus test coverage.
Below with reference to accompanying drawing, the technique effect of design of the present utility model, concrete structure and generation is described further, to understand fully the purpose of this utility model, feature and effect.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the test structure of embedded system storer of the present utility model.
Embodiment
The test structure of embedded system storer of the present utility model is embedded in SoC chip, and as shown in Figure 1, it comprises the i.e. SRAM0 shown in figure of CPU, controller, system bus, SPI interface, zero-bit SRAM() and MUX MUX.Wherein, CPU is embedded CPU, and it is connected with the memory array in SoC chip by system bus.Controller is connected with external testing machine by SPI interface, and it is a time sequence conversion circuit, for SPI sequential is converted to SRAM sequential.Memory array in SoC chip comprises zero-bit SRAM, multiple SRAM and ROM, as shown in Figure 1 SRAM0, SRAM1 ..., SRAMn and ROMn.The address of SRAM0 wherein in memory array is 0; SRAM1 represents first SRAM ..., SRAMn represents n SRAM, ROMn represents n ROM.
CPU by the SRAM1 in system bus and memory array ..., SRAMn and ROMn be connected one by one, and be connected with SRAM0 with MUX MUX by system bus.Particularly, an output terminal of system bus is connected with the first input end of MUX MUX, and it is SRAM0 that the output terminal of MUX MUX is connected to zero-bit SRAM(), the second input end of MUX MUX connects the output terminal of controller.In the present embodiment, MUX MUX has two input ends and an output terminal.
In the present embodiment, SPI interface is SPI Slave external interface, between itself and external testing machine, has 4 wiring, connects respectively pin SPICS, pin SPICLK, pin MOSI and the pin MISO of SPI Slave external interface.Pin SPICS is input pin, and pin SPICLK is input pin, and pin MOSI is input pin, and pin MISO is output pin.Pin SPICS, pin SPICLK, pin MOSI and pin MISO in the present embodiment are all industrywide standard, and wherein SPICS is chip selection signal, and SPICLK is clock signal, and MOSI is input signal, and MISO is output signal.
The test structure of embedded system storer of the present utility model in use, comprises the following steps:
External testing machine setup test program, so that the memory array in SoC chip is tested, it is in particular generation test vector, i.e. a series of pumping signals that are used for testing memory array, its form of expression that is test procedure.
External testing machine SoC chip is set to memory test patterns, starts thus the memory array in SoC chip to test, and correspondingly, MUX MUX selection path is that controller arrives zero-bit SRAM.
External testing machine sends to SoC chip by test procedure.Be in particular, external testing machine sends to the controller of the test structure that is embedded in the embedded system storer of the present utility model in SoC chip by it at the test procedure of preparing before by SPI Slave external interface.
Controller receives test procedure, and is kept in zero-bit SRAM.Be in particular: controller receives the test procedure that external testing machine sends, and pass through MUX MUX at the path of selecting before, the test procedure of reception is saved in to zero-bit SRAM.
External testing machine carries out reset operation to SOC chip, and CPU moves test procedure from zero-bit SRAM then, thereby the memory array in SoC chip is tested, and this test can be the comprehensive test to the memory array in SoC chip.
Controller outputs test result to outside test machine, and test result is passed through or test failure for testing.Test is by being that each SRAM and ROM tested in memory array meets testing standard, and test failure is that in memory array, one or more SRAM and/or ROM exist fault.
When test result is test failure, the test structure of embedded system storer of the present utility model can also provide the analysis to test result, is in particular:
When test result is test failure, controller is to outside test machine output detecting information.This detecting information comprises each SRAM in memory array and the concrete test data of ROM, and external testing machine, by analyzing these concrete test datas, can be searched failure cause the locate failure position of memory array.
More than describe preferred embodiment of the present utility model in detail.Should be appreciated that those of ordinary skill in the art just can make many modifications and variations according to design of the present utility model without creative work.Therefore, all those skilled in the art comply with design of the present utility model on the basis of existing technology by the available technical scheme of logical analysis, reasoning, or a limited experiment, all should be in by the determined protection domain of claims.
Claims (8)
1. a test structure for embedded system storer, is embedded in SoC chip, it is characterized in that, comprises CPU, controller, system bus, SPI interface, zero-bit SRAM and MUX; Described CPU is connected with the memory array in described SoC chip by described system bus; Described memory array comprises described zero-bit SRAM, multiple SRAM and ROM, and the address of described zero-bit SRAM in described SRAM array is 0; Described controller is connected with external testing machine by described SPI interface; Described MUX has first input end, the second input end and output terminal, the described first input end of described MUX connects described system bus, described second input end of described MUX connects described controller, and the described output terminal of described MUX connects described zero-bit SRAM.
2. the test structure of embedded system storer as claimed in claim 1, wherein said controller is time sequence conversion circuit, for SPI sequential is converted to SRAM sequential.
3. the test structure of embedded system storer as claimed in claim 2, wherein said SPI interface is SPISlave external interface.
4. the test structure of embedded system storer as claimed in claim 3, between wherein said SPI Slave external interface and described external testing machine, there are 4 wiring, connect respectively pin SPICS, pin SPICLK, pin MOSI and the pin MISO of described SPI Slave external interface.
5. the test structure of embedded system storer as claimed in claim 4, wherein said pin SPICS is input pin.
6. the test structure of embedded system storer as claimed in claim 5, wherein said pin SPICLK is input pin.
7. the test structure of embedded system storer as claimed in claim 6, wherein said pin MOSI is input pin.
8. the test structure of embedded system storer as claimed in claim 7, wherein said pin MISO is output pin.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320761742.7U CN203573309U (en) | 2013-11-27 | 2013-11-27 | Testing structure for embedded system memory |
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| CN201320761742.7U CN203573309U (en) | 2013-11-27 | 2013-11-27 | Testing structure for embedded system memory |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105116317A (en) * | 2015-07-14 | 2015-12-02 | 工业和信息化部电子第五研究所 | Integrated circuit test system and method |
| CN105446843A (en) * | 2014-05-30 | 2016-03-30 | 展讯通信（上海）有限公司 | SOC chip function test system and method |
-
2013
- 2013-11-27 CN CN201320761742.7U patent/CN203573309U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105446843A (en) * | 2014-05-30 | 2016-03-30 | 展讯通信（上海）有限公司 | SOC chip function test system and method |
| CN105446843B (en) * | 2014-05-30 | 2019-02-15 | 展讯通信（上海）有限公司 | SOC chip function test system and method |
| CN105116317A (en) * | 2015-07-14 | 2015-12-02 | 工业和信息化部电子第五研究所 | Integrated circuit test system and method |
| CN105116317B (en) * | 2015-07-14 | 2017-12-05 | 工业和信息化部电子第五研究所 | Integrated circuit test system and method |
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Effective date of registration: 20230727 Address after: 310053 room 1001, innovation building, 3850 Jiangnan Road, high tech (Binjiang), Hangzhou, Zhejiang Patentee after: Hangzhou Zhongke Microelectronics Co.,Ltd. Address before: 314006 Building 2, No. 778, Asia Pacific Road, Jiaxing, Zhejiang Province (Jiaxing Technopole) Patentee before: JIAXING MICROELECTRONICS AND SYSTEM ENGINEERING CENTER, CHINESE ACADEMY OF SCIENCES |
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