CN107290654A - A kind of fpga logic test structure and method - Google Patents
A kind of fpga logic test structure and method Download PDFInfo
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- CN107290654A CN107290654A CN201710500759.XA CN201710500759A CN107290654A CN 107290654 A CN107290654 A CN 107290654A CN 201710500759 A CN201710500759 A CN 201710500759A CN 107290654 A CN107290654 A CN 107290654A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3177—Testing of logic operation, e.g. by logic analysers
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Abstract
The invention discloses a kind of fpga logic test structure and method, including there is provided measured signal inside FPGA or variable for FPGA module；Outer memory module, connects the FPGA module and carries out storage processing to the inside measured signal from FPGA module or variable；Control module, connects the outer memory module, and chooses the measured signal or variable of storage, completes outside reading, judges to show after the internal logic running status of FPGA module.A kind of fpga logic test structure and method of the present invention is compared with prior art, observation can be easily and efficiently tracked to measured signal, verify FPGA internal logics, significant increase project initial stage and the efficiency for debugging the stage, resource occupation are low, relative to instrumentation, also development cost can be reduced, it is practical, it is applied widely, it is easy to promote.
Description
Technical field
The present invention relates to fpga logic technical field of measurement and test, specifically a kind of FPGA that can be where quick positioning question
Logic testing structure and method.
Background technology
FPGA（Field programmable gate array）It is a kind of semiconducter IC, with hardware description language（Verilog or VHDL）It is complete
Into circuit design, by simple comprehensive with being laid out, quickly it be burned onto on FPGA and tested, available for various functions number
Word circuit is developed, while available for modern IC designs checking.
On stream, test checking need to be carried out to the circuit logic function of being described by hardware description language, typically may be used
Logic analysis function in the piece provided using FPGA manufacturers, or logic testing checking is carried out using special logic analysis instrument,
But these methods or the FPGA internal logic resources for taking uncertain quantity, or higher cost is needed, it is unfavorable for general
FPGA projects are debugged, and when FPGA internal signals or variable are abnormal, need to carry out test checking, tend not to orientation problem institute quickly
.
Based on this, this patent provides a kind of fpga logic test structure and method solved the above problems.
The content of the invention
The technical assignment of the present invention is that there is provided a kind of fpga logic test structure and method for above weak point.
A kind of fpga logic test structure, including,
There is provided measured signal inside FPGA or variable for FPGA module；
Outer memory module, connects the FPGA module and inside measured signal or variable from FPGA module is stored
Processing；
Control module, connects the outer memory module, and chooses the measured signal or variable of storage, completes outside reading, sentences
Shown after the internal logic running status of disconnected FPGA module.
In the FPGA module, logic in FPGA pieces, storage control module and memory interface module are configured with, it is described
Logic, which provides logic in measured signal or variable, the FPGA pieces and is connected to said external by memory interface module, in FPGA pieces deposits
Store up module；Storage control module is directly connected to said external memory module, and storage control module logic in FPGA pieces is carried
The resource composition of confession, for being controlled the data of the outer memory module to write according to logic requirement to be measured.
The storage format of the outer memory module determines with size logic control in FPGA pieces, the outer memory module
The read requests sent by control module are responded, stored data is back to the control module.
The type of the memory interface module is corresponding with the type of outer memory module, if the memory interface module is included
Dry bit data bus and some controlling bus, for providing connecting interface and realizing data storage in FPGA and external storage mould
Transmission between block.
The control module is made up of external microcontroller, communication module and upper computer module, external microcontroller difference
Outer memory module and communication module are connected to, communication module is also connected to outer memory module and upper computer module, wherein,
External microcontroller, for responding the reading instruction from upper computer module, in special time to the external storage mould
Block carry out digital independent, and by communication module be back to upper computer module carry out storage show；
Communication module, the instruction for upper computer module to be sent reaches external microcontroller, while by outer memory module
Data back to upper computer module；
Upper computer module, for responding commissioning staff's demand, in special time by measured signal or variable from outer memory module
Read and show.
A kind of fpga logic method of testing, based on foregoing circuit structure, its test process is：Determining FPGA module first is
It is no normally to run；It is determined that the measured signal or variable of FPGA module are deposited by outer memory module after normal operation
Storage；By control module complete to measured signal or variable reading, shown after judging internal logic running status.
Determine whether normally FPGA module by carrying out structure pretreatment before storing realize by operation：To outer memory module
It is adapted to, according to the type of outer memory module, determines the data/address bus type and controlling bus type of memory interface module,
And logical sum outer memory module in FPGA pieces is connected, while outer memory module is connected with storage control module, by FPGA
Logic sends logical signal to be measured or variable in piece, and when outer memory module is normally received, the FPGA module is normally run.
It is determined that in the step of whether FPGA module is normally run, in addition it is also necessary to determine external storage according to logic in FPGA pieces
The storage format and size of module, are completed after data storage, and the reading that outer memory module response is sent by control module please
Ask, stored data is back in the control module.
The process of judgement and display that control module completes data is：Measured signal or variable are chosen by upper computer module,
Read and show from outer memory module by external microcontroller, for judging internal logic running status.
The detailed process of judgement and display that control module completes data is：
Upper computer module response commissioning staff's demand, sends reading instruction first, and the instruction sent is reached by communication module
In external microcontroller；
Reading instruction of the external microcontroller response from upper computer module, is carried out in special time to the outer memory module
Digital independent；
By communication module by the data back of the reading in outer memory module into upper computer module；
Measured signal or variable are read and shown from outer memory module in special time by upper computer module.
Compared to the prior art a kind of fpga logic test structure and method of the present invention, have the advantages that：
A kind of fpga logic test structure and method of the present invention, is patrolled by adding the external storage controller simplified before comprehensive
Volume, the consecutive variations of measured signal are stored to outer memory module, then read by external microcontroller and return display, can be with
Observation is easily and efficiently tracked to measured signal, verifies FPGA internal logics, significant increase project initial stage and debugging stage
Efficiency, resource occupation is low, relative to instrumentation, can also reduce development cost, practical, applied widely, it is easy to
Promote.
Brief description of the drawings
Accompanying drawing 1 is that structure of the present invention realizes schematic diagram.
Embodiment
In order that those skilled in the art more fully understand the solution of the present invention, with reference to embodiment to this
Invention is described in further detail.Obviously, described embodiment is only a part of embodiment of the invention, rather than all
Embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art institute under the premise of creative work is not made
The every other embodiment obtained, belongs to the scope of protection of the invention.
As shown in Figure 1, a kind of fpga logic test structure, including,
There is provided measured signal inside FPGA or variable for FPGA module；
Outer memory module, connects the FPGA module and inside measured signal or variable from FPGA module is stored
Processing；
Control module, connects the outer memory module, and chooses the measured signal or variable of storage, completes outside reading, sentences
Shown after the internal logic running status of disconnected FPGA module.
In the FPGA module, logic in FPGA pieces, storage control module and memory interface module are configured with, it is described
Logic, which provides logic in measured signal or variable, the FPGA pieces and is connected to said external by memory interface module, in FPGA pieces deposits
Store up module；Storage control module is directly connected to said external memory module, and storage control module logic in FPGA pieces is carried
The resource composition of confession, for being controlled the data of the outer memory module to write according to logic requirement to be measured.
The storage format of the outer memory module determines with size logic control in FPGA pieces, the outer memory module
The read requests sent by control module are responded, stored data is back to the control module.
The type of the memory interface module is corresponding with the type of outer memory module, if the memory interface module is included
Dry bit data bus and some controlling bus, for providing connecting interface and realizing data storage in FPGA and external storage mould
Transmission between block.
The control module is made up of external microcontroller, communication module and upper computer module, external microcontroller difference
Outer memory module and communication module are connected to, communication module is also connected to outer memory module and upper computer module, wherein,
External microcontroller, for responding the reading instruction from upper computer module, in special time to the external storage mould
Block carry out digital independent, and by communication module be back to upper computer module carry out storage show；
Communication module, the instruction for upper computer module to be sent reaches external microcontroller, while by outer memory module
Data back to upper computer module；
Upper computer module, for responding commissioning staff's demand, in special time by measured signal or variable from outer memory module
Read and show.
A kind of fpga logic method of testing, based on foregoing circuit structure, its test process is：Determining FPGA module first is
It is no normally to run；It is determined that the measured signal or variable of FPGA module are deposited by outer memory module after normal operation
Storage；By control module complete to measured signal or variable reading, shown after judging internal logic running status.
Determine whether normally FPGA module by carrying out structure pretreatment before storing realize by operation：To outer memory module
It is adapted to, according to the type of outer memory module, determines the data/address bus type and controlling bus type of memory interface module,
And logical sum outer memory module in FPGA pieces is connected, while outer memory module is connected with storage control module, by FPGA
Logic sends logical signal to be measured or variable in piece, and when outer memory module is normally received, the FPGA module is normally run.
It is determined that in the step of whether FPGA module is normally run, in addition it is also necessary to determine external storage according to logic in FPGA pieces
The storage format and size of module, are completed after data storage, and the reading that outer memory module response is sent by control module please
Ask, stored data is back in the control module.
The process of judgement and display that control module completes data is：Measured signal or variable are chosen by upper computer module,
Read and show from outer memory module by external microcontroller, for judging internal logic running status.
The detailed process of judgement and display that control module completes data is：
Upper computer module response commissioning staff's demand, sends reading instruction first, and the instruction sent is reached by communication module
In external microcontroller；
Reading instruction of the external microcontroller response from upper computer module, is carried out in special time to the outer memory module
Digital independent；
By communication module by the data back of the reading in outer memory module into upper computer module；
Measured signal or variable are read and shown from outer memory module in special time by upper computer module.
By embodiment above, the those skilled in the art can readily realize the present invention.But should
Work as understanding, the present invention is not limited to above-mentioned embodiment.On the basis of disclosed embodiment, the technical field
Technical staff can be combined different technical characteristics, so as to realize different technical schemes.
It is the known technology of those skilled in the art in addition to the technical characteristic described in specification.
Claims (10)
1. a kind of fpga logic test structure, it is characterised in that including,
There is provided measured signal inside FPGA or variable for FPGA module；
Outer memory module, connects the FPGA module and inside measured signal or variable from FPGA module is stored
Processing；
Control module, connects the outer memory module, and chooses the measured signal or variable of storage, completes outside reading, sentences
Shown after the internal logic running status of disconnected FPGA module.
2. a kind of fpga logic test structure according to claim 1, it is characterised in that in the FPGA module, match somebody with somebody
It is equipped with logic in logic in FPGA pieces, storage control module and memory interface module, the FPGA pieces and measured signal or change is provided
Logic is connected to said external memory module by memory interface module in amount, the FPGA pieces；Storage control module is directly connected to
To said external memory module, the storage control module resource composition that logic is provided in FPGA pieces, for being patrolled according to be measured
Volume demand controls the data of the outer memory module to write.
3. a kind of fpga logic test structure according to claim 2, it is characterised in that the outer memory module is deposited
Storage form determines that the reading that outer memory module response is sent by control module please with size logic control in FPGA pieces
Ask, stored data is back to the control module.
4. a kind of fpga logic test structure according to claim 2, it is characterised in that the class of the memory interface module
Type is corresponding with the type of outer memory module, and the memory interface module is total comprising some bit data bus and some controls
Line, for providing connecting interface and realizing transmission of the data storage between FPGA and outer memory module.
5. according to a kind of any described fpga logic test structures of claim 1-4, it is characterised in that the control module by
External microcontroller, communication module and upper computer module composition, external microcontroller are connected respectively to outer memory module and logical
Believe module, communication module is also connected to outer memory module and upper computer module, wherein,
External microcontroller, for responding the reading instruction from upper computer module, in special time to the external storage mould
Block carry out digital independent, and by communication module be back to upper computer module carry out storage show；
Communication module, the instruction for upper computer module to be sent reaches external microcontroller, while by outer memory module
Data back to upper computer module；
Upper computer module, for responding commissioning staff's demand, in special time by measured signal or variable from outer memory module
Read and show.
6. a kind of fpga logic method of testing, based on the circuit structure described in the claims, it is characterised in that it was tested
Cheng Wei：Determine whether FPGA module can normally be run first；It is determined that by the measured signal of FPGA module or change after normal operation
Amount is stored by outer memory module；By control module complete to measured signal or variable reading, judge internal patrols
Shown after collecting running status.
7. a kind of fpga logic method of testing according to claim 6, it is characterised in that determine whether FPGA module is normal
Operation is realized by carrying out structure pretreatment before storing：Outer memory module is adapted to, according to outer memory module
Type, determines the data/address bus type and controlling bus type of memory interface module, and connects in FPGA pieces and deposited outside logical sum
Store up module, while outer memory module is connected with storage control module, in FPGA pieces logic transmission logical signal to be measured or
Variable, when outer memory module is normally received, the FPGA module is normally run.
8. a kind of fpga logic method of testing according to claim 6, it is characterised in that it is determined that FPGA module whether just
Often in the step of operation, in addition it is also necessary to the storage format and size of outer memory module are determined according to logic in FPGA pieces, number is completed
After storage, stored data is back to the control by the read requests that outer memory module response is sent by control module
In module.
9. a kind of fpga logic method of testing according to claim 6, it is characterised in that control module completes sentencing for data
Break and the process of display is：Measured signal or variable are chosen by upper computer module, by external microcontroller from external storage mould
Read and show in block, for judging internal logic running status.
10. a kind of fpga logic method of testing according to claim 9, it is characterised in that control module completes data
Judge and the detailed process of display is：
Upper computer module response commissioning staff's demand, sends reading instruction first, and the instruction sent is reached by communication module
In external microcontroller；
Reading instruction of the external microcontroller response from upper computer module, is carried out in special time to the outer memory module
Digital independent；
By communication module by the data back of the reading in outer memory module into upper computer module；
Measured signal or variable are read and shown from outer memory module in special time by upper computer module.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108920334A (en) * | 2018-07-25 | 2018-11-30 | 郑州云海信息技术有限公司 | A kind of monitoring device of FPGA isomery accelerator card |
| CN109240965A (en) * | 2018-08-01 | 2019-01-18 | 清华大学 | Fpga logic capture processing display external member and its application method |
| CN109444630A (en) * | 2018-11-05 | 2019-03-08 | 西安智多晶微电子有限公司 | FPGA routing cell tests structure and method |
| CN110007218A (en) * | 2018-01-04 | 2019-07-12 | 中国航发商用航空发动机有限责任公司 | Digital circuit product tester |
| CN112255534A (en) * | 2020-10-14 | 2021-01-22 | 天津津航计算技术研究所 | IP core module debugging system based on FPGA |
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| CN109240965A (en) * | 2018-08-01 | 2019-01-18 | 清华大学 | Fpga logic capture processing display external member and its application method |
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| CN112255534A (en) * | 2020-10-14 | 2021-01-22 | 天津津航计算技术研究所 | IP core module debugging system based on FPGA |
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