CN204832267U - Chip test platform - Google Patents

Chip test platform Download PDF

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Publication number
CN204832267U
CN204832267U CN201520615529.4U CN201520615529U CN204832267U CN 204832267 U CN204832267 U CN 204832267U CN 201520615529 U CN201520615529 U CN 201520615529U CN 204832267 U CN204832267 U CN 204832267U
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CN
China
Prior art keywords
test
chip
control unit
main control
platform
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Application number
CN201520615529.4U
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Chinese (zh)
Inventor
孟顺祥
黄苏芳
门长有
Original Assignee
万高(杭州)科技有限公司
国网智能电网研究院
国家电网公司
国网山东省电力公司电力科学研究院
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Priority to CN201520615529.4U priority Critical patent/CN204832267U/en
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Publication of CN204832267U publication Critical patent/CN204832267U/en

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Abstract

The embodiment of the utility model discloses chip test platform, include: the the main control unit that the chip carries out corresponding test is surveyed in control, be connected with the main control unit, produce the vice the control unit that the required incoming signal of chip was surveyed in the test, can dismantle with the main control unit and vice the control unit and be connected, the socket subassembly of being surveyed chip and chip test platform is connected to physics, be connected with the main control unit, open the start -up button of mobile core piece test, be connected with the main control unit, show the LCD display of test procedure and result. Main test item test is accomplished in other part work on the the main control unit control test platform, can change corresponding socket subassembly according to chip model or encapsulation. This chip test platform, can the automatic testing chip of different models, the chip that meets the requirements is judged in the screening, has improved accuracy, reliability and the flexibility of test, the chip of different models can be tested to same platform, has reduced test cost.

Description

A kind of chip test platform

Technical field

The utility model relates to chip testing field, particularly relates to a kind of chip test platform.

Background technology

Along with the development of integrated circuit fabrication process, the integrated level of chip improves constantly, and the function that every chips realizes becomes increasingly complex, the manufacturing cost of single chips is in continuous reduction, but form sharp contrast, the cost proportion shared by the packaging and testing of chip is but more and more higher.

Packaging cost is mainly relevant with packaging technology level with packing material (gold and copper etc.), for chip design enterprise, and the limited space that its cost reduces.The testing cost of chip volume production then reduces by multiple dimensions such as design optimization, chip test tool optimizations.For the exploitation of electric energy computation chip and SoC chip test platform, especially in this segmentation application of electric energy computation chip, user is very high to the requirement of chip yield, and the accuracy that during chip volume production, test platform screens, reliability and dirigibility are most important.

Thus, the hardware and software platform of chip testing how is realized, when testing chip, automatic screening judges satisfactory chip, thus the accuracy of raising test, reliability and dirigibility, reducing testing cost, is the current technical issues that need to address of those skilled in the art.

Utility model content

The purpose of this utility model is to provide a kind of chip test platform, automatic screening can judge satisfactory chip, thus the accuracy of raising test, reliability and dirigibility, reduce testing cost.

For solving the problems of the technologies described above, the utility model provides following technical scheme:

A kind of chip test platform, for testing electric energy computation chip and SoC chip, comprising:

Control chip test platform and chip under test carry out the main control unit of corresponding test;

Be connected with described main control unit, produce the sub-control unit of the input signal of test needed for described chip under test;

Removably connect with described main control unit and sub-control unit, the socket assembly of chip under test described in physical connection and described chip test platform;

Be connected with described main control unit, the startup button of bootrom test;

Be connected with described main control unit, the LCD display of display test process and result.

Preferably, also comprise: be connected with described main control unit and socket assembly, complete the FPGA unit of digital test.

Preferably, also comprise: be connected with described main control unit, the SD storage card of the test performance index result of chip under test described in autostore.

Preferably, also comprise: be connected with described main control unit, the parallel port interface communicated with separator.

Preferably, also comprise: be connected with described main control unit, prompting test process, the hummer that test starts and test terminates.

Preferably, comprise between described sub-control unit and described socket assembly: be controlled by described sub-control unit, power for described chip under test and measure the power circuit of current value and magnitude of voltage.

Preferably, comprise between described main control unit and described socket assembly: transmit described main control unit to a SPI interface of described chip under test configuration data information, UART interface and/or jtag interface.

Preferably, also comprise between described main control unit and described socket assembly: the tension measuring circuit measuring the magnitude of voltage of the pin of described chip under test.

Preferably, described main control unit carries out digital test by FPGA unit described in the 2nd SPI Interface Controller to described chip under test and reads test result and the test data of described FPGA unit.

Preferably, described socket assembly comprises: the card extender connecting the socket interface of chip test platform; Be arranged on described card extender, place the chip pocket of described chip under test.

Compared with prior art, technique scheme has the following advantages:

A kind of chip test platform that the utility model embodiment provides, main control unit is the core controller of chip test platform, control the work of other parts on this chip test platform, and complete main test item test, as ram test, FLASH tests, REG tests, interrupt test, UART test and GPIO test etc., and main control unit can upgrade corresponding test procedure according to the chip model that will test, each test item of automatic test chip under test, test process and test result are shown on an lcd display, and filter out satisfactory chip, sub-control unit assists main control unit to complete test, and for generation of the input signal needed for test chip under test, makes chip under test can simulate actual chip operating condition in test platform, socket assembly is detachable on test platform, can change corresponding socket assembly according to different chip models or different chip packages, operating personnel start whole test platform by startup button and carry out test job.The chip test platform that the utility model provides, automatically can test the chip of different model, satisfactory chip is judged in screening, thus improves the accuracy of test, reliability and dirigibility, identical platform can test the chip of different model, reduces testing cost.

Accompanying drawing explanation

In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is embodiments more of the present utility model, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.

The chip test platform structural representation that Fig. 1 provides for the utility model specific embodiment;

The chip test platform structural representation that Fig. 2 provides for another specific embodiment of the utility model;

The socket modular construction schematic diagram that Fig. 3 provides for the utility model embodiment.

Embodiment

Core of the present utility model is to provide a kind of chip test platform, automatic screening can judge satisfactory chip, thus the accuracy of raising test, reliability and dirigibility, reduce testing cost.

In order to enable above-mentioned purpose of the present utility model, feature and advantage more become apparent, and are described in detail embodiment of the present utility model below in conjunction with accompanying drawing.

Set forth detail in the following description so that fully understand the utility model.But the utility model can be different from alternate manner described here to implement with multiple, those skilled in the art can when doing similar popularization without prejudice to when the utility model intension.Therefore the utility model is not by the restriction of following public embodiment.

Please refer to Fig. 1, the chip test platform structural representation that Fig. 1 provides for the utility model specific embodiment.

A kind of specific embodiment of the present utility model provides a kind of chip test platform, for testing electric energy computation chip and SoC chip, comprising: control the main control unit 1 that chip under test carries out corresponding test; Be connected with described main control unit 1, produce the sub-control unit 2 of the input signal of test needed for described chip under test; Removably connect with described main control unit 1 and sub-control unit 2, the socket assembly 3 of chip under test described in physical connection and described chip test platform; Be connected with described main control unit 1, the startup button 4 of bootrom test; Be connected with described main control unit 1, the LCD display 5 of display test process and result.

Main control unit 1 (MCU) is the core controller of chip test platform, the work of other parts on control chip test platform, outputs signal testing power consumption and LCD display shows etc. as controlled sub-control unit 2.And complete main test item test, as ram test, FLASH test, REG test, interrupt test, UART test and GPIO test etc.Wherein, main control unit 1 can upgrade corresponding test procedure according to the model of the chip that will test.

Sub-control unit 2 assists main control unit 1 to complete test, it is for generation of the analog input signal needed for test chip under test, wherein, the analog input signal of test needed for chip under test comprises power supply, current signal and voltage signal etc., makes chip under test can simulate actual chip operating condition in chip test platform.

Socket assembly 3 physical connection chip under test and chip test platform, realize chip under test pin to be connected with the whole of chip test platform, wherein, user can change corresponding socket assembly 3 according to different chip models or different chip packages, as shown in Figure 3, described socket assembly 3 comprises: the card extender 31 connecting the socket interface of chip test platform; Be arranged on described card extender 31, place the chip pocket 32 (i.e. socket) of described chip under test.

Start button 4 and to be used for when manual test bootrom test.LCD display 5 is for showing in test beginning, test process and testing the every terms of information terminating to comprise, comprising test process and test result.

The specific implementation process of chip test platform for: according to the chip model will carrying out testing or chip package, corresponding test procedure is upgraded to main control unit, chip under test is placed in corresponding socket assembly, press startup button, then chip test platform is tested accordingly to chip under test.Wherein, chip test platform can test the various functions of chip under test automatically according to the main control unit being provided with test procedure, and judge that whether the digital function of chip under test is correct, according to the threshold value preset, judge whether the simulated performance of chip under test reaches standard, after completing test, the indices of synthetic setting, judge that chip is non-defective unit or defective products, test result is shown on an lcd display.

The testable chip of the chip test platform that the present embodiment provides is not limited to electric energy computation chip, general SoC chip can also be tested, the encapsulation of chip under test simultaneously neither be fixed, can according to different classes of, the model of the chip that will test and encapsulation, upgrade the test procedure in the main control unit of chip test platform, and change the socket assembly adapted with chip under test.Thus, the chip test platform in the present embodiment, has autorun, and automatic screening judges the function of good chips, can the testing requirement of each product line compatible.

Please refer to Fig. 2, the chip test platform structural representation that Fig. 2 provides for the utility model specific embodiment.

On the basis of above-described embodiment, the chip test platform that the utility model embodiment provides, also comprises: be connected with described main control unit 1 and socket assembly 3, completes the FPGA unit 6 of digital test.

In the present embodiment, main control unit 1 controls FPGA unit 6, and FPGA unit 6 is mainly used in the high speed of chip under test, the test of complicated digital function, i.e. DFT test, and the simulation ADC signal to noise ratio (S/N ratio) (SNR), pulse capture etc. of test chip under test.

Wherein, described main control unit 1 controls described FPGA unit 6 by the 2nd SPI interface 23, carries out digital test and read test result and the test data of described FPGA unit 6 to described chip under test.

FPGA unit 6 carries out DFT test by DFT interface 24 pairs of chip under test; FPGA unit 6 tests SNR by SNR interface 25; FPGA unit 6 is exported by pulse test interface 26 test pulse.Main control unit 1 controls FPGA unit 6 pairs of chip under test by the 2nd SPI interface 23 and tests, and main control unit 1 also reads test result and the test data of FPGA unit 6 by the 2nd SPI interface 23.

The chip test platform that the utility model embodiment provides, also comprises: be connected with described main control unit 1, the SD storage card 7 of the test performance index result of chip under test described in autostore.

Main control unit 1 control SD storage card 7 storage data, the data such as the test performance index of SD storage card 7 autostore chip under test and test result, user can to the data analysis in SD storage card 7 by instruments such as computers, the overall yield of chip product can be added up, the various performance parameters of analysis chip.Certainly, also can be analyzed test data by the parts such as main control unit 1 grade of chip test platform, can also statistical graph etc. be made, and the data message such as analysis result and statistical graph can be shown on an lcd display, with for reference.

The chip test platform that the utility model provides, can also have data statistics and analytic function, can provide the analysis result of each data test item of chip under test, for product operation and research and development provide strong practice reference.

The chip test platform that the utility model embodiment provides, also comprises: be connected with described main control unit 1, the parallel port interface 8 communicated with separator.

In the present embodiment, when parallel port interface 8 connects the test of one or more separator for chip test platform, as the connecting interface of chip test platform and separator, realize communicating of chip test platform and separator.

The chip test platform of the present embodiment both can work alone, and carried out chip testing, also can coordinate separator collaborative work, converted the efficient volume production tool of production to.Wherein, manual socket assembly is changed into the socket assembly matched with separator, be connected on separator, chip test platform is connected by parallel port interface with separator simultaneously, separator puts into socket assembly needing the chip of test, and separator sends test instruction to chip test platform, after chip test platform completes test by parallel port interface 8, by parallel port interface 8, test result is sent back to separator, carry out next step action for separator analysis.Certainly, when chip test platform is provided with SD storage card, test result also can be stored in SD storage card.Allow chip test platform communicate with separator, namely can be exchanged into the volume production platform of test automatically, improve tested productivity.

The chip test platform that the utility model embodiment provides, also comprises: be connected with described main control unit 1, prompting test process, the hummer 9 that test starts and test terminates.

When testing, user needs to look at LCD display always and carrys out observation test process, serious waste resource, adopt hummer prompting test process, test start and at the end of have auditory tone cues, user can understand the process of test in time.

It should be noted that, when stable batch testing, LCD also can not be needed to show and hummer work, can select to close them.

The chip test platform that the utility model embodiment provides, comprises between described sub-control unit 2 and described socket assembly 3: be controlled by described sub-control unit 2, powers and measure the power circuit 17 of current value and magnitude of voltage for described chip under test.

When after startup test, main control unit 1 sends corresponding instruction to sub-control unit 2, and sub-control unit 2 controls power circuit 17 and powers to chip under test, and power circuit 17 can measure current/voltage value, thus calculates the power consumption number of chip under test.

Also comprise voltage signal circuit 18 and current signal circuit 19 between sub-control unit 2 and socket assembly 3, for the input of current signal and voltage signal, current signal and voltage signal can the sizes of closed loop adjustment output signal.The 2nd GPIO mouth 20 is also comprised, for carrying out GPIO test between sub-control unit 2 and socket assembly 3.

Wherein, the interface priority that main control unit 1 is connected with sub-control unit 2 is UART interface 11.Main control unit 1 sends instruction to sub-control unit 2 by UART interface 11, sub-control unit 2 controls power circuit 17 and powers to chip under test, power circuit 17 can measure current/voltage value, thus calculate the power consumption number of chip under test, the input signal that the metering voltage signal of sub-control unit 2 control voltage signal circuit 18 or the metering current signal of current signal circuit 19 measure as chip under test.

The chip test platform that the utility model embodiment provides, comprises between described main control unit 1 and described socket assembly 3: transmit described main control unit to a SPI interface 12 of described chip under test configuration data information, UART interface 13 and/or jtag interface 16.

Also comprise between described main control unit and described socket assembly: the tension measuring circuit 15 measuring the magnitude of voltage of the pin of described chip under test.Also comprise between described main control unit and described socket assembly: a GPIO mouth 14.

Main control unit 1 is by a SPI interface 12, UART interface 13 or jtag interface 16, enable chip under test is configured to chip under test and starts metering, also can be configured chip under test makes chip under test be in different duties, main control unit 1 also reads whole register values of chip under test by a SPI interface 12, UART interface 13 or jtag interface 16, thus obtain the test values such as the metering of chip under test, measured the magnitude of voltage of the pin of chip under test by tension measuring circuit 15, measure as LDO and REF is equivalent.

In the utility model embodiment, the connecting interface of main control unit 1 and startup button 4 is an I/O mouth 21; The connecting interface of main control unit 1 and LCD display 5 is Three S's PI interface 22; The connecting interface of main control unit 1 and SD storage card 7 is SDIO interface 27; The connecting interface of main control unit 1 and parallel port interface 8 is the 2nd I/O mouth 28; The connecting interface of main control unit 1 and hummer 9 is the 3rd I/O mouth 29.

It should be noted that, just preferably adopt each parts in above interface connection chip test platform in the utility model embodiment, also can adopt other interfaces, as long as ensure the information data transmission do not affected between each parts, the present embodiment is not construed as limiting this, specifically depends on the circumstances.

Also it should be noted that, in this article, the relational terms of such as first and second and so on is only used for an entity or operation to separate with other entities or operational zone, and might not require or imply the relation that there is any this reality between these entities or operation or sequentially.

In sum, a kind of chip test platform that the utility model embodiment provides, testable chip is not limited to electric energy computation chip, general SoC chip can also be tested, the encapsulation of chip under test simultaneously neither be fixed, can according to different classes of, the model of the chip that will test and encapsulation, upgrade the test procedure in the main control unit of chip test platform, and change the socket assembly adapted with chip under test, thus there is autorun, automatic screening judges the function of good chips, can the testing requirement of each product line compatible.

In addition, the chip test platform that the utility model provides, can also have data statistics and analytic function, can provide the analysis result of each data test item of chip under test, for product operation and research and development provide strong practice reference.

Finally, chip test platform both can work alone, and carried out chip testing, also can coordinate separator collaborative work, converted the efficient volume production tool of production to.Only need change manual socket assembly into match with separator socket assembly, be connected on separator, chip test platform is connected by parallel port interface with separator simultaneously, separator puts into socket assembly needing the chip of test, separator sends test instruction to chip test platform by parallel port interface, after chip test platform completes test, by parallel port interface, test result is sent back to separator, carry out next step action for separator analysis.Chip test platform communicates with separator, namely can be exchanged into the volume production platform of test automatically, improves tested productivity.

A kind of chip test platform is provided to be described in detail to the utility model above.Apply specific case herein to set forth principle of the present utility model and embodiment, the explanation of above embodiment just understands core concept of the present utility model for helping.Should be understood that; for those skilled in the art; under the prerequisite not departing from the utility model principle, can also carry out some improvement and modification to the utility model, these improve and modify and also fall in the protection domain of the utility model claim.

Claims (10)

1. a chip test platform, for testing electric energy computation chip and SoC chip, is characterized in that, comprising:
Control the main control unit that chip under test carries out corresponding test;
Be connected with described main control unit, produce the sub-control unit of the input signal of test needed for described chip under test;
Removably connect with described main control unit and sub-control unit, the socket assembly of chip under test described in physical connection and described chip test platform;
Be connected with described main control unit, the startup button of bootrom test;
Be connected with described main control unit, the LCD display of display test process and result.
2. chip test platform according to claim 1, is characterized in that, also comprises:
Be connected with described main control unit and socket assembly, complete the FPGA unit of digital test.
3. chip test platform according to claim 2, is characterized in that, also comprises:
Be connected with described main control unit, the SD storage card of the test performance index result of chip under test described in autostore.
4. chip test platform according to claim 3, is characterized in that, also comprises:
Be connected with described main control unit, the parallel port interface communicated with separator.
5. chip test platform according to claim 4, is characterized in that, also comprises:
Be connected with described main control unit, prompting test process, the hummer that test starts and test terminates.
6. chip test platform according to claim 5, is characterized in that, comprises between described sub-control unit and described socket assembly:
Be controlled by described sub-control unit, power for described chip under test and measure the power circuit of current value and magnitude of voltage.
7. chip test platform according to claim 6, is characterized in that, comprises between described main control unit and described socket assembly:
Transmit described main control unit to a SPI interface of described chip under test configuration data information, UART interface and/or jtag interface.
8. chip test platform according to claim 7, is characterized in that, also comprises between described main control unit and described socket assembly:
Measure the tension measuring circuit of the magnitude of voltage of the pin of described chip under test.
9. chip test platform according to claim 2, is characterized in that, described main control unit carries out digital test by FPGA unit described in the 2nd SPI Interface Controller to described chip under test and reads test result and the test data of described FPGA unit.
10. the chip test platform according to any one of claim 1 to 9, is characterized in that, described socket assembly comprises:
Connect the card extender of the socket interface of chip test platform;
Be arranged on described card extender, place the chip pocket of described chip under test.
CN201520615529.4U 2015-08-14 2015-08-14 Chip test platform CN204832267U (en)

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105913878A (en) * 2016-04-19 2016-08-31 深圳极智联合科技股份有限公司 RAM detection apparatus and detection method thereof
CN107290654A (en) * 2017-06-27 2017-10-24 济南浪潮高新科技投资发展有限公司 A kind of fpga logic test structure and method
CN108037437A (en) * 2017-12-12 2018-05-15 苏州国芯科技有限公司 A kind of system for testing SoC chip electrical characteristic
CN108572312A (en) * 2018-04-12 2018-09-25 中国电子产品可靠性与环境试验研究所((工业和信息化部电子第五研究所)(中国赛宝实验室)) SoC chip test method, device, system and SoC chip test witness plate
CN109239576A (en) * 2018-08-03 2019-01-18 光梓信息科技(上海)有限公司 A kind of high speed optical communication chip test system and method
CN109490749A (en) * 2018-09-13 2019-03-19 深圳市卓精微智能机器人设备有限公司 A kind of eMMC FLASH class chip test system
CN109490747A (en) * 2018-09-13 2019-03-19 深圳市卓精微智能机器人设备有限公司 A kind of LED flashing light class chip test system
CN109490746A (en) * 2018-09-13 2019-03-19 深圳市卓精微智能机器人设备有限公司 A kind of SPI FLASH class chip test system
CN109541430A (en) * 2018-09-13 2019-03-29 深圳市卓精微智能机器人设备有限公司 A kind of NOR FLASH class chip test system
CN109557447A (en) * 2018-09-13 2019-04-02 深圳市卓精微智能机器人设备有限公司 A kind of power management class IC test macro

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105913878A (en) * 2016-04-19 2016-08-31 深圳极智联合科技股份有限公司 RAM detection apparatus and detection method thereof
CN107290654A (en) * 2017-06-27 2017-10-24 济南浪潮高新科技投资发展有限公司 A kind of fpga logic test structure and method
CN108037437A (en) * 2017-12-12 2018-05-15 苏州国芯科技有限公司 A kind of system for testing SoC chip electrical characteristic
CN108572312A (en) * 2018-04-12 2018-09-25 中国电子产品可靠性与环境试验研究所((工业和信息化部电子第五研究所)(中国赛宝实验室)) SoC chip test method, device, system and SoC chip test witness plate
CN109239576A (en) * 2018-08-03 2019-01-18 光梓信息科技(上海)有限公司 A kind of high speed optical communication chip test system and method
CN109490749A (en) * 2018-09-13 2019-03-19 深圳市卓精微智能机器人设备有限公司 A kind of eMMC FLASH class chip test system
CN109490747A (en) * 2018-09-13 2019-03-19 深圳市卓精微智能机器人设备有限公司 A kind of LED flashing light class chip test system
CN109490746A (en) * 2018-09-13 2019-03-19 深圳市卓精微智能机器人设备有限公司 A kind of SPI FLASH class chip test system
CN109541430A (en) * 2018-09-13 2019-03-29 深圳市卓精微智能机器人设备有限公司 A kind of NOR FLASH class chip test system
CN109557447A (en) * 2018-09-13 2019-04-02 深圳市卓精微智能机器人设备有限公司 A kind of power management class IC test macro

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Address after: 310053 Binjiang District, Hangzhou, No. six and road, a building (North), building B4004, room, four

Patentee after: Hangzhou hi tech Limited by Share Ltd

Patentee after: State Grid Smart Grid Institute

Patentee after: State Power Networks Co

Patentee after: Electric Power Research Institute of State Grid Shandong Electric Power Company

Address before: 310053 Binjiang District, Hangzhou, No. six and road, a building (North), building four, B4004,

Patentee before: Wangao (Hangzhou) Technology Co.Ltd

Patentee before: State Grid Smart Grid Institute

Patentee before: State Power Networks Co

Patentee before: Electric Power Research Institute of State Grid Shandong Electric Power Company