CN112255534A - IP core module debugging system based on FPGA - Google Patents
IP core module debugging system based on FPGA Download PDFInfo
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- CN112255534A CN112255534A CN202011099186.2A CN202011099186A CN112255534A CN 112255534 A CN112255534 A CN 112255534A CN 202011099186 A CN202011099186 A CN 202011099186A CN 112255534 A CN112255534 A CN 112255534A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31705—Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318516—Test of programmable logic devices [PLDs]
- G01R31/318519—Test of field programmable gate arrays [FPGA]
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Abstract
The invention relates to an IP core module debugging system based on an FPGA (field programmable gate array), belonging to the field of digital integrated circuits. The auxiliary debugging unit is added in the IP core to be tested, the data storage unit is arranged outside the IP core to be tested, the data storage unit is provided with the data storage area, the preset data area and the self-defined capture condition area, the auxiliary debugging unit can switch the IP core to be tested into a debugging mode and read the preset information and capture conditions in the data storage unit, so that the functional performance of the IP core at the beginning in a state appointed by a designer is observed, the data of the IP core to be tested can be stored in the data storage unit, and the IP core module can be debugged simply and conveniently at low cost. Further, by customizing the capture conditions, the IP core module may be debugged in various forms. Therefore, the problems that the existing IP core module based on the FPGA is complex and tedious to debug, high in cost, resource-occupied, not flexible enough and the like are solved.
Description
Technical Field
The invention belongs to the technical field of digital integrated circuits, and particularly relates to an IP core module debugging system based on an FPGA.
Background
In the prior art, the debugging work of the IP core module based on the FPGA is complex and tedious, and a large amount of professional personnel and development time are required to be invested. The existing FPGA debugging methods mainly comprise two methods, one is to connect signals needing to be checked in the FPGA to FPGA pins, and then to analyze the signals output by the pins by adopting expensive equipment such as a logic analyzer and the like; another method is that an external cable is connected to the FPGA through a JTAG interface, a trigger condition is set through a software logic analyzer provided by FPGA manufacturers such as Xilinx, and when a certain signal reaches the trigger condition, an IP core designer can be helped to analyze existing problems by capturing a waveform. However, both of these methods have certain problems, the first method requires expensive test equipment and is relatively high in cost, and the second method requires inserting a logic analysis unit provided by an FPGA manufacturer into an FPGA logic, which occupies BRAM resources inside the FPGA and can only store a very small amount of field data.
The patent with application number 201110413599.8 discloses an FPGA debugging method, which locates problems by adding a trigger condition circuit unit for debugging and a signal acquisition unit for acquiring key signals. This method has some problems:
1) because the trigger conditions are different, if all possible trigger conditions are covered, a great deal of workload is needed, and if only a part of conditions are covered, the flexibility is not enough.
2) The trigger condition is for the physical layer signal logic such as level, which can help the designer to understand the problem of the underlying timing, but if the designer is concerned about the problem of the higher level logic, it is difficult and tedious to set the condition trigger.
Disclosure of Invention
Technical problem to be solved
The technical problem to be solved by the invention is how to provide an IP core module debugging system based on FPGA, so as to solve the problems of complex and tedious debugging, higher cost, resource occupation, inflexibility and the like of the existing IP core module based on FPGA.
(II) technical scheme
In order to solve the technical problem, the invention provides an IP core module debugging system based on an FPGA, which comprises: the device comprises an auxiliary debugging unit and a data storage unit, wherein the auxiliary debugging unit comprises a mode switching module, a custom capture module, a data storage module and a data loading module, the data storage unit comprises a data storage area of an IP core register and a buffer area, a debugging mode register and buffer area preset value area and a custom capture condition area, and the IP core to be tested comprises the auxiliary debugging unit, a register unit and a buffer area unit for caching data;
the mode switching module is used for switching the IP core to be tested between a normal operation mode and a debugging mode;
the data loading module is responsible for loading preset information in a preset numerical value area and a user-defined capturing condition area of a debugging mode register and a buffer area in the data storage unit into an IP core register unit, an IP core buffer area unit and the user-defined capturing module;
the data storage module is responsible for storing data in an IP core register unit and an IP core buffer area unit into data storage areas of an IP core register and a buffer area in the data storage unit, and when the data storage is controlled by the self-defined capture module;
and the custom capturing module loads custom capturing conditions.
(III) advantageous effects
The invention provides an IP core module debugging system based on FPGA, which is characterized in that an auxiliary debugging unit is added in an IP core to be debugged, a data storage unit is arranged outside the IP core to be debugged, a data storage area, a preset data area and a self-defined capture condition area are arranged in the data storage unit, the auxiliary debugging unit can switch the IP core to be debugged into a debugging mode and read the preset information and capture conditions in the data storage unit, so that the functional performance of the IP core at the beginning in a state appointed by a designer is observed, and the data of the IP core to be debugged can be stored in the data storage unit, so that the IP core module can be debugged simply and conveniently at low cost. Further, by customizing the capture conditions, the IP core module may be debugged in various forms. Therefore, the problems that the existing IP core module based on the FPGA is complex and tedious to debug, high in cost, resource-occupied, not flexible enough and the like are solved.
Drawings
FIG. 1 is a schematic diagram of a debugging system according to the present invention;
FIG. 2 is a diagram of an auxiliary debug unit according to the present invention.
Detailed Description
In order to make the objects, contents and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
The invention provides a debugging system and a method of an IP core module based on FPGA, wherein the system comprises: supplementary debugging unit, data memory cell, DMA control unit, wherein, supplementary debugging unit includes: the system comprises a mode switching module, a user-defined capturing module, a data storage module and a data loading module. The DMA control unit is connected to the auxiliary debugging unit and the data storage unit. The data storage unit comprises a data storage area of an IP core register and a buffer area, a debugging mode register and buffer area preset value area and a user-defined capture condition area, and the IP core to be tested comprises the auxiliary debugging unit, a register unit and a buffer area unit for caching data;
the mode switching module is used for switching the IP core to be tested between a normal operation mode and a debugging mode;
the data loading module is responsible for loading preset information in a preset numerical value area and a user-defined capturing condition area of a debugging mode register and a buffer area in the data storage unit into an IP core register unit, an IP core buffer area unit and the user-defined capturing module;
the data storage module is responsible for storing data in an IP core register unit and an IP core buffer area unit into data storage areas of an IP core register and a buffer area in the data storage unit, and when the data storage is controlled by the self-defined capture module;
and the custom capturing module loads custom capturing conditions.
Further, the data storage unit is a DDR.
Further, in the debug mode, the user stores configuration information in the data storage unit.
Furthermore, the data loading module stores the data storage area of the IP core register and the buffer area, and the start address of the custom capture condition area in the data storage unit.
Further, the data storage module stores the start address of the data storage area of the IP core register and the buffer in the data storage unit.
Further, the custom capture condition is determined by a specific combination of values of the IP core registers, buffers.
Further, custom capture conditions can set the number of cycles for which capture continues.
Further, the system also includes a DMA control unit connected to the auxiliary debugging unit and the data storage unit.
Further, the debug mode includes: the method comprises the steps of firstly, storing information in a register and a buffer area unit in an IP core to a data storage unit, secondly, loading the information in the data storage unit to the register or the buffer area of the IP core, and thirdly, loading a custom capture condition to a custom capture module of an auxiliary debugging unit.
The key points of the invention are as follows:
(1) and adding an auxiliary debugging unit in the IP core to be tested for realizing the function of the debugging system. Any IP core can be abstracted as a logical module including a register unit and a buffer unit for caching data.
(2) And the mode switching module in the auxiliary debugging unit can switch the IP core to be tested between a normal operation mode and a debugging mode. The normal operation mode is a mode when the IP core works normally, and the debugging mode is a mode used in a debugging state.
(3) In debug mode, the user can store configuration information in a data store, typically a DDR (other stores that can provide the same functionality are also possible).
(4) The data storage unit comprises a data storage area of an IP core register and a buffer area, a preset numerical value area of a debugging mode register and the buffer area, a self-defined capture condition area and the like.
(5) The debugging mode mainly comprises three functions, namely, the storage of information in a register and a buffer area unit in the IP core to a data storage unit, the loading of the information in the data storage unit to the register or the buffer area of the IP core, and the loading of a custom capture condition to a custom capture module of the auxiliary debugging unit.
(6) The data loading module is responsible for managing how to load the preset information in the data storage unit into the IP core register unit, the IP core buffer unit and the custom capture module, and stores the initial address of the information in the data storage unit. This function is mainly used to observe the functional behavior of the IP core at the beginning in the state specified by the designer.
(7) And the data storage module is used for managing how to store the data in the IP core register unit and the IP core buffer area into the data storage unit, controlling when the data is stored by the custom capture module, and storing the initial addresses of the IP core register and the IP core buffer area in the data storage unit.
(8) The user-defined capturing module is loaded with user-defined capturing conditions, the user-defined capturing conditions are determined by specific numerical value combination of the IP core register and the buffer area, and the number of cycles of capturing duration can be set, namely the data of the IP core register and the buffer area in one time or a period of time can be recorded.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (9)
1. An IP core module debugging system based on FPGA, which is characterized by comprising: the device comprises an auxiliary debugging unit and a data storage unit, wherein the auxiliary debugging unit comprises a mode switching module, a custom capture module, a data storage module and a data loading module, the data storage unit comprises a data storage area of an IP core register and a buffer area, a debugging mode register and buffer area preset value area and a custom capture condition area, and the IP core to be tested comprises the auxiliary debugging unit, a register unit and a buffer area unit for caching data;
the mode switching module is used for switching the IP core to be tested between a normal operation mode and a debugging mode;
the data loading module is responsible for loading preset information in a preset numerical value area and a user-defined capturing condition area of a debugging mode register and a buffer area in the data storage unit into an IP core register unit, an IP core buffer area unit and the user-defined capturing module;
the data storage module is responsible for storing data in an IP core register unit and an IP core buffer area unit into data storage areas of an IP core register and a buffer area in the data storage unit, and when the data storage is controlled by the self-defined capture module;
and the custom capturing module loads custom capturing conditions.
2. The FPGA-based IP core module debugging system of claim 1 wherein the data storage unit is a DDR.
3. The FPGA-based IP core module debugging system of claim 1 wherein, in a debugging mode, a user stores configuration information in the data storage unit.
4. The FPGA-based IP core module debugging system of claim 1 wherein the data loading module stores the starting address of the data storage area of the IP core registers and buffers, the custom capture condition area in the data storage unit.
5. The FPGA-based IP core module debugging system of claim 1, wherein the data storage module stores a starting address of a data storage area of IP core registers and buffers in the data storage unit.
6. The FPGA-based IP core module debugging system of claim 1 wherein custom capture conditions are determined by specific combinations of values of IP core registers, buffers.
7. The FPGA-based IP core module debugging system of claim 1 wherein the custom capture condition sets a number of cycles for a duration of capture.
8. The FPGA-based IP core module debugging system of claim 1 further comprising a DMA control unit connected to the auxiliary debugging unit and the data storage unit.
9. The FPGA-based IP core module debugging system of any one of claims 1-8, wherein the debugging mode comprises: the method comprises the steps of firstly, storing information in a register and a buffer area unit in an IP core to a data storage unit, secondly, loading the information in the data storage unit to the register or the buffer area of the IP core, and thirdly, loading a custom capture condition to a custom capture module of an auxiliary debugging unit.
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