WO2000062339A1

WO2000062339A1 - Semiconductor integrated circuit, method for testing the same, and method for manufacturing the same

Info

Publication number: WO2000062339A1
Application number: PCT/JP1999/001974
Authority: WO
Inventors: Masayuki Satoh; Isao Shimizu; Hideaki Takahashi
Original assignee: Hitachi, Ltd.
Priority date: 1999-04-14
Filing date: 1999-04-14
Publication date: 2000-10-19
Also published as: JP4147005B2

Abstract

A variable logic circuit, such as an FPGA (Field Programmable Gate Array), comprising basic logic cells (cell logic block) and capable of outputting a signal representing whether or not the circuit is normal for each logic cell and of constituting an arbitrary logic is provided in a semiconductor chip. A memory test circuit for testing a memory circuit instructs a variable logic circuit (FPGA) to perform a self-test, generates a predetermined test signal and an expectation signal referring to the information representing fault portions detected by the self-test according to a predetermined algorithm by means of only normal basic logic cells, feeds the test signal to the memory circuit, compares the output signal (output data) from the memory circuit with the expectation signal (expectation data), generates a signal representing a fault if the output signal does not agree with the expectation signal, and outputs the signal to the outside of the chip.

Description

TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit, a test method therefor, and a manufacturing method.

The present invention relates to a semiconductor integrated circuit (IC: Integrated Circuit) and its test technology and manufacturing technology. For example, the present invention provides a logic LSI (Large Scale Integration) capable of detecting a fault and avoiding a fault location to configure a logic. is there. Background art

As a test method for a logic IC, a method is generally used in which test pattern data is generated by a test device called a test device, input to the IC, and the output data signal is compared with an expected value and detected. Met. However, the number of steps in the test pattern of the logic IC increases as the scale of the logic increases, and the time required to create the test pattern and to perform a test using the test pattern becomes extremely long.

Therefore, as a method of facilitating the test using a tester, a sequential circuit such as a flip-flop that constitutes the original function of the IC is cascaded to design a shift register. A test pattern is serially input (scan-in) at the register and loaded (set), and the test data captured at the shift register is input to a desired combinational logic circuit, and then the output of the logic circuit is output. A so-called scan path method, which is a so-called scan path method that enables a data signal to be taken into a shift register and shifted out (scan out), has been developed and put into practical use.

In the method of inputting a test pattern from the outside, if the logic circuit includes a sequential circuit, the output differs depending on the internal state.Therefore, to test a certain logic circuit, first test the state of the sequential circuit included in it. The test pattern becomes very long because it must be set with a pattern, but the test pattern is input (scan-in) with the flip-flop configuration as a shift register. As a result, the number of test passes can be significantly reduced.

However, in the above scan path method, although the amount of test patterns is smaller than the previous test methods, it is difficult to generate a test pattern, it is difficult to increase a failure detection rate, and the test pattern is input (transferred) serially. Since the test is repeated, there is a problem when the test time is long. Also, if the newly developed logic LSI has memory circuits such as RAM (random 'access' memory) and ROM (read 'only' memory), or large cells (macrocell or IP core: Intellectual Property Core) such as CPU However, if these cells are to be tested, a huge amount of test patterns need to be created and entered, and the test cannot be performed in practice.

On the other hand, a B1ST (Built-in self test) test technique has been proposed in which a pattern generator that generates a random test pattern such as a pseudo-random number generator is built in a logic integrated circuit.

However, the BIST test circuit does not guarantee that the generated test pattern will be a test pattern sufficient to detect a defect. Therefore, there is a problem that it is necessary to separately verify whether a sufficient defect detection rate can be obtained with a test pattern of a test circuit.

Furthermore, none of the LSIs equipped with the conventional test circuit takes any measures against the failure or defect of the test circuit itself. In other words, when the test circuit itself fails, there is a disadvantage that a failure is determined even if the original circuit of the chip is normal. The only countermeasure that can be taken is to minimize the size of the test circuit and suppress the occurrence of failures and defects.This results in inconsistencies with the objective of improving test adequacy, that is, improving the defect detection rate. I will invite you.

An object of the present invention is to provide a test technique capable of testing a circuit inside an LSI without using a high-performance external tester.

Another object of the present invention is to provide a high-yield LSI that can detect a faulty part and repair itself by itself. Another object of the present invention is to provide an LSI having a self-test function with little hardware overhead.

Another object of the present invention is to provide an LSI which is easy for failure analysis. Still another object of the present invention is to provide a manufacturing technology suitable especially for a so-called system LSI having a control circuit such as a central processing unit, a memory circuit, a custom logic circuit, etc. on one chip. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

The outline of typical inventions disclosed in the present application is as follows.

That is, the semiconductor integrated circuit according to the present invention includes a plurality of basic logic cells (cell logic blocks) on a chip, and can output a signal indicating whether the circuit is normal or abnormal for each of the basic logic cells, and performs arbitrary logic. It is equipped with a variable logic circuit such as a configurable FPGA (Field Programmable Gate Array). As a result, it is possible to know that there is a defective portion in the variable logic circuit (FPGA) and its location without using an external tester. In addition, the yield is improved by constructing logic by avoiding defective parts, and when a test circuit is constructed using this variable logic circuit (FPGA) to test other internal circuits, the test circuit itself is tested. It is possible to avoid outputting an incorrect test result due to a failure.

The basic logic cell that can output a signal indicating whether the circuit is normal or abnormal is, for example, a 2-wire line logic (logical AND gate circuit) having complementary outputs and a judging means for judging the presence or absence of an abnormality by comparing its output. (Exclusive OR gate). This configuration of the basic logic cell realizes a variable logic circuit (FPGA) that can output a signal indicating whether the circuit is normal or abnormal and that can configure any logic with a relatively small circuit. can do.

Further, the method for testing a semiconductor integrated circuit according to the present invention includes at least a plurality of substrates. A variable logic circuit (FPGA) consisting of this logic cell (cell logic block) and capable of outputting a signal indicating whether the circuit is normal or abnormal for each basic logic cell and capable of configuring any logic, and a readable and writable memory circuit First, a self-test is performed by the above-described variable logic circuit (FPGA) in a semiconductor integrated circuit with a built-in logic, and a predetermined algorithm is used only with the basic logic cell excluding the defective part using the information indicating the defective part obtained as a result. A predetermined test signal and an expected value signal are generated in accordance with and the test signal is supplied to the memory circuit. As a result, an output signal (output data) obtained from the memory circuit and the expected value signal (expected value data) are obtained. The memory test circuit is configured to generate a signal indicating a failure when the two do not match, and output the signal to the outside of the chip.

Such a memory test circuit can be configured as a test pattern generator called an ALPG (Algorithmic Memory Pattern Generator) that generates a memory test pattern according to a predetermined algorithm. Further, the ALPG is composed of a control unit of a known microprogram control system that decodes an instruction code and controls an arithmetic unit and the like, and an arithmetic unit that generates a test pattern by an arithmetic operation. Then, the instruction code of the test pattern generation program is sequentially supplied to the ALPG built in the FPGA as described above to generate a test pattern, and the test pattern is supplied to the memory circuit which is the circuit under test. The presence or absence of a defect can be inspected.

Further, the test pattern generation program is described using an existing tester language or a test language, and a test pattern (address and data) is generated according to the predetermined algorithm defined by the instruction code. The tester language is regarded as an effective command language for efficiently generating a test pattern including an address and data. The test language is a language used in the tester industry. For example, a language compatible with Advantest's test language is used. As a result, the program data of the existing test pattern can be used. The language for describing the predetermined algorithm is not limited to the test language, but may be any instruction language capable of generating a test pattern including an address and data. Another test method of the semiconductor integrated circuit according to the present invention includes a semiconductor integrated circuit including a custom logic circuit such as a CPU (Central Processing Unit) or a user logic circuit configured with a logic function required by a user together with a memory circuit. In such a case, a test circuit (logic test) that generates test signals and expected value signals for the CPU and custom logic circuits in accordance with a predetermined algorithm in the above-mentioned FPGA and conducts the test is constructed, and it is determined that the test is normal by the above test. Using the configured memory circuit, the test pattern or the test pattern generation program is stored in the memory circuit, and the test circuit built in the FPGA is started to read the test pattern or the test pattern generation program from the memory circuit. It tests CPUs and custom logic circuits.

As a result, the logic circuit inside the LSI can be tested without using a sophisticated external tester.

A test circuit for generating a test signal and an expected value signal of a CPU or a custom logic circuit in accordance with a predetermined algorithm and performing a test includes a micro-instruction-type control unit that decodes an instruction code and forms a control signal; When a test signal and an expected value signal for a CPU or a custom logic circuit are generated based on a control signal output from a control unit, and a signal output from the CPU or a custom logic circuit is compared with an expected value signal and the values do not match. This is achieved by constructing signal formation and comparison means in the FPGA that generate a signal indicating a failure. In this case, a timing generation circuit that forms a plurality of clock signals having different phases and duties from each other based on the reference clock signal is built in the FPGA, and the timing for each test signal is controlled according to the control signal from the control unit. It is good to be able to set.

As described above, the test circuit includes a microprogram control type control unit that forms a control signal for generating a test signal and an expected value signal for the CPU and the custom logic circuit according to a predetermined algorithm, and an output from the control unit. The test signal and expected value signal of the internal logic circuit are generated based on the control signal to be generated, and the signal output from the internal logic circuit is compared with the expected value signal to form a signal indicating a failure if they do not match. Signal formation Therefore, it is not necessary to store all the test patterns in the internal memory, and the configuration of the control unit enables the data compression of the instruction code itself, so that it can be sufficiently built in the FPGA. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram showing an entire configuration of an embodiment of a logic LSI to which the present invention is applied.

FIG. 2 is a circuit configuration diagram showing one embodiment of a variable logic circuit (FPGA) provided in a logic LSI to which the present invention is applied.

FIG. 3 is a block diagram showing a specific example of a crosspoint switch constituting an FPGA.

FIG. 4 is a logic circuit diagram and a conceptual diagram showing a specific example of a cell logic block constituting an FPGA.

FIG. 5 is a logic circuit diagram showing another example of the cell logic block constituting the FPGA.

FIG. 6 is a block diagram showing a configuration example of a test interface circuit provided in a logic LSI to which the present invention is applied.

FIG. 7 is a flowchart illustrating an example of an inspection procedure of the internal circuit in the logic LSI to which the present invention is applied.

FIG. 8 is a flowchart showing the specific contents of the inspection procedure of the FPGA section in steps S1 to S3 of the flowchart of FIG.

FIG. 9 is a flowchart showing specific contents of the inspection procedure of the SRAM section in steps S4 to S5 of the flowchart of FIG.

FIG. 10 is a flowchart showing the specific contents of the inspection procedure of the custom logic circuit and the CPU unit in steps S6 to S8 of the flowchart of FIG.

FIG. 11 is a flowchart showing specific contents of the inspection procedure of the DRAM section in steps S9 to S12 of the flowchart of FIG.

Figure 12 is a block diagram showing the configuration of the ALPG built in the FPGA. O

FIG. 13 is a block diagram illustrating a configuration example of a path when a memory circuit is tested using the ALPG.

FIG. 14 is an explanatory diagram showing a configuration example of the instruction format of the microphone opening instruction stored in the instruction memory of the ALPG.

FIG. 15 is a block diagram illustrating a configuration example of a sequence control unit of the ALPG.

FIG. 16 is a block diagram illustrating a configuration example of an address calculation unit of the ALPG. FIG. 17 is a block diagram illustrating a configuration example of a test data generation operation unit of the ALPG.

FIG. 18 is a flowchart showing an example of a sequence control procedure using an opcode and an operand of a microinstruction when a memory circuit is inspected by ALPG.

FIG. 19 is a flowchart showing an example of a test address and data generation and output procedure using a micro-instruction operation code and a data generation code when a memory circuit is inspected by ALPG.

FIG. 20 is a block diagram showing a configuration example of a logic tester built in the FPGA.

FIG. 21 is a logic circuit diagram showing a specific example of a signal forming / comparing means in a logic test.

FIG. 22 is a waveform diagram showing an example of a test signal waveform formed by a logic test. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a system LSI to which the present invention is applied, and is configured on a single semiconductor chip 100 such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

In FIG. 1, reference numerals 1 to 180 denote internal components formed on the semiconductor chip 100. Circuit, 190 is an interface circuit for inputting and outputting signals between these internal circuits and external devices, and 200 is for connecting the above internal circuits 110 to 180 and between the interface circuit 190 It is an internal bus. Of the internal circuits 110 to 180, 110 and 120 are custom logic circuits such as a user logic circuit that configures a logic function required by a user, and 120 of these logics can be freely configured by a user. It is composed of FPGA. This custom logic circuit may be left as it is without configuring the user logic. 130 is a CPU (central processing unit) that decodes program instructions and executes corresponding processing and operations, 140 is a static RAM (random access memory), and 150 to 180 are dynamic RAMs. Further, although not particularly limited, the system LSI of this embodiment is stipulated by the IEEE 1149.1 standard in order to input and output signals to and from an external tester 500 when testing internal circuits. TAP (Test Access Port) 210 is provided as an interface circuit. The tester 500 does not have to be as sophisticated as a conventional logic LSI or memory tester, but can be a device that can perform data read / write and simple data processing. Can also be used.

The CPU 130 is configured as a microprocessor processor including a so-called microcomputer peripheral circuit such as a program ROM, a marking RAM, a serial communication interface, a timer circuit, and a digital-to-analog conversion circuit, in addition to the CPU in a narrow sense. You may.

The static RAM 140 and the dynamic RAMs 150 to 180 include memory peripheral circuits such as an address decoder for selecting a corresponding memory cell when an address signal is applied via the internal path 200. In addition, the dynamic RAMs 150 to 180 include a refresh control circuit that performs pseudo-selection periodically so that the information charges of the memory cells are not lost even when the non-access time is long. In addition, although not particularly limited, in this embodiment, if there is a defective bit in the memory array, the dynamic RAM 150 to 180 stores a spare memory row or column containing the defective bit in the memory array. If memory row In other words, so-called redundant circuits that replace the spare memory columns are provided.

FIG. 2 shows a specific example of the FPGA constituting the custom logic circuit 120 among the internal circuits 110 to 180 shown in FIG.

The FPGA of this embodiment includes a plurality of cell logic blocks C LB arranged in a matrix, wiring groups 121 and 122 provided between each cell logic block CLB to connect cells, and It is composed of a cross-point switch C SW that can change the state of wiring connection. As shown in FIG. 3, for example, the cross point switch C SW is divided into a horizontal wiring Lx and a vertical wiring Ly, and a switch MOSFET Qsw having a drain connected thereto and a gate of the switch MOSFET Qsw. And a wiring connection information storage memory cell SMC for storing control information applied to the power supply. It is desirable that the wiring groups 121 and 122 be formed in a state where they are insulated from each other by different wiring layers using a multilayer wiring technique. Although FIG. 2 shows two wires between each cell logic block, more wires are actually formed. The number of wires is increased in proportion to the number of cell logic blocks.

Although not particularly limited, an X-decoder circuit, a Y-decoder circuit, a write circuit, and the like for selecting the above-mentioned wiring connection information storage memory cell SMC and writing data are provided around the FPGA block. You may do it. The memory cell SMC for storing the wiring connection information can be provided as an SRAM memory array around the FPGA block instead of being provided as a pair I with the switch MO SFET Qsw.

As shown in Fig. 4 (a), for example, as shown in Fig. 4 (a), the cell logic block CLB has a logical product gate circuit (2-wire linear logic) LG1 having complementary outputs such as AND logic and NAND logic, and its complementary output as an input. And exclusive OR gate circuit (comparing means). The gate circuit LG 2 outputs a low-level output signal when the two input signals have the same logic level, and outputs a high-level output signal when the two input signals have different logic levels. If the output of the AND gate circuit LG1 is defective and the complementary output should be the in-phase output, the output of the gate circuit LG2 goes low, indicating that the gate circuit LG1 is defective.

The output signal of the gate circuit LG2 may be output as it is to the outside of the FPGA block. However, in this embodiment, the signal for storing the wiring connection information constituting the cross point switch C SW shown in FIG. 3 is used. The memory cell is configured so that it can be inputted to the node N2 of the SMC and stored.

Therefore, the power supply voltage is applied to each cell logic block CLB, the output state of the gate circuit LG2 at that time is stored in the wiring connection information storage memory cell SMC, and then the wiring connection information storage memory cell SMC is By reading the stored information to the outside, it is possible to know whether or not the cell logic block CLB operates normally. In addition, by sequentially writing and reading data from the outside of the chip to each wiring connection information storage memory cell SMC, it is also possible to detect whether or not a memory cell has failed. Furthermore, by writing data to the wiring connection information storage memory cell SMC, turning on the desired switch MOSFET Qsw, and inputting a signal from the outside using the wiring groups 121 and 122 and checking, the switch MOSFET Qsw becomes It is also possible to detect whether a failure has occurred.

Note that when the output of the gate circuit LG2 is low level, the gate structure of the MOSFET Q1 or the memory cell circuit that constitutes the wiring connection information storage memory cell SMC to which the output state of the gate circuit LG2 is input is devised. May be configured so that the MOS FET Q1 is not inverted by an external input from outside, that is, does not turn off. This makes it possible to efficiently detect whether or not the cell logic block CLB has a failure.

As a specific method of realizing such a function, for example, as shown in FIG. 4 (b), the MOS FET Q1 constituting the memory cell SMC has a structure having a control gate and a floating gate, and a gate circuit LG2 is provided. The output (low level) is inverted by INV and the high level voltage Vp is applied to the control gate CG of the MOSFET 1 to float. A method is conceivable in which charges are injected into the gate FG so that the state of the memory cell does not change due to external data input.

Also, as the AND gate circuit LG1 having complementary outputs such as the AND logic and the NAND logic shown in FIG. 4 (a), for example, a circuit as shown in FIG. 4 (c) can be considered. That is, the logical product gate circuit LG 1 is composed of a first MOSFET row composed of MOS SFETs Q 11 to Q 13 connected in series between the power supply voltage terminal Vc c and the ground point, and a series MOSFET S 1 A second MOSFET row composed of TQ21 to Q23, and a first input signal X is supplied to the gates of Q12 and Q21, so that input signals X, X are output from the output node N12 of the second M0 SFET row. AND output Z of Y (= ΧY), and inverted output / Z (= / X-Y) of AND output Z of input signals X and Y from output node N 11 of the first MOS FET column To work. The MOSFETs Q11 and Q23 shown in the figure respectively act as loads when the gate and the drain are coupled or a predetermined potential is applied to the gate.

FIG. 5A shows another configuration example of the cell logic block CLB.

The cell logic block CLB of this embodiment is a logic block with a built-in BIST (Built-in self test), which latches two input signals X and Y, respectively, and outputs positive and negative signals X and / X; Flip-flops FF1 and FF2 that output Υ and / Υ, a logic unit ALU that uses these four output signals as input signals and can perform multiple logical operations such as logical sum, logical product, and exclusive logical sum, and this logical unit A flip-flop FF3 for latching the output Z of the unit and outputting the positive and negative phase signals Z and / Z; a readable and writable memory MEM for storing control information for specifying the logical operation of the logic unit; It consists of a well-known LFSR (Linear Feedback Shift Register) that generates test patterns in the form of random numbers and a comparator CMP.

The memory MEM for storing the logic unit control information is configured to allow externally writing control information. The input signals X and Y and the logical unit control information and the logical unit control information are connected to the LFSR via the switches MOSF ET G1 to G7. It can be connected to the output signal 2 of / 3 and the transmission signal line of / Z, and operates in synchronization with the clock CLK.

When the cell logic block CLB of this embodiment is to be subjected to a self-test operation, a control signal CHK is input to the gates of the switches MO SFETs G1 to G7 to be turned on. Then, a random pattern is formed by the LFSR and supplied to the flip-flops FF 1 and FF 2 and the logic unit ALU, and the generated pattern and the output of the flip-flop FF 3 are logically synthesized and compressed. Output to the CMP as a signature pattern

For example, as shown in Fig. 5 (b), the comparator CMP latches from the read 'only' memory ROM where the expected signature pattern is stored, the exclusive OR gate EOR, the output latch OLT, and the clock CLK. It is composed of a timing generation circuit TMG that generates signals. When a signature pattern is input from the LF SR, the CMP compares the expected signature pattern stored in the only ROM with the exclusive OR gate EOR and the output pattern of the LF SR. If they match, a low-level signal is output, and if they do not match, a high-level signal is output. This output is latched by the latch OLT and output as a signal ERR indicating good / bad.

The principle of operation of the LFSR is already known and has been described in various documents, so a detailed description is omitted, but optimization according to the logic circuit to be inspected can be performed according to the principle. In a general logic LSI with a built-in BIST to which LFSR is applied, optimization of the LFSR is required for each logic circuit, which complicates the design.However, in the FPGA of this embodiment, the same cell logic is used. Since the block CLB is used, the optimization can be performed uniformly, and the design burden is reduced. In addition, in conventional LSIs with a built-in BIST, one BIST is a global BIST that inspects all the internal circuits of the LSI, so the test patterns generated do not guarantee test adequacy. BIST is a local B provided in each cell logic block CLB. Because of the IST, test adequacy is also guaranteed.

FIG. 6 shows a specific example of the interface circuit 210 using the TAP shown in FIG.

As described above, TAP is an interface and control circuit for scan test and BIST circuits specified in the IEEE 1149.1 standard, and shifts test data from input ports to output ports. Select the bypass register 211, the data register 212 used to transmit a specific signal to the circuit, the device ID register 213 to set the chip-specific manufacturing identification number, and the data register. And an instruction register 214 used for controlling the internal test method, a controller 215 for controlling the entire TAP circuit, and the like.

The data registry evening 212 is a registration evening treated as an option. In addition, four mandatory instructions and three optional instructions are prepared for the instructions set in the Instruction Registrar. The test mode select signal TMS, the test clock TCK, and the reset signal TRST for specifying the test mode are input to the controller 215 from three dedicated external terminals. Control signals for the registers 211 to 214 and the selector circuits 216 to 218 are formed.

The TAP is provided with an input terminal for the test data TDI and an output terminal for the test result data TD, and the input test data TDI is supplied to each of the registers 211 to 1 through the selector circuit 216. Supplied to 214 or internal scan path Iscan, Bscan. The contents of the registers 211 to 214 and the scanout data from the internal circuit are output to the outside of the chip via the selector circuits 217 and 218. Further, a signal to the internal BIST circuit is formed and supplied to the TAP according to the contents of the data register 212 and the instruction register 214, and a signal indicating the test result output from the BIST circuit is output to the selector circuit 217. , 218 so that it can be output to the outside of the chip.

In the system LSI of the embodiment of FIG. 1, as will be described in detail later, The self-test circuit built on the CPU logic circuit (FPGA) 120 or the CPU 130 is regarded as a BIST circuit, and the signal input / output function for the BIST circuit of the TAP is used to create a custom logic circuit (FPGA) 120 It is configured to input a setting signal for self-test to CPU and CPU 130, and to output test results and data stored in memory cells in FPGA 120 and SRAM 140. ing. The scan test function of the TAP is not used in the system LSI of the embodiment of FIG.

In FIG. 6, "Iscan" is a test for diagnosing the internal logic circuit by using a shift register in which flip-flops constituting the internal logic circuit are connected in a chain as a scan path for the test data. Means a path. The “Bscan” uses a shift register, which is a chain of flip-flops provided in the signal input / output section (the interface circuit 190 in FIG. 1), as a scan path, and uses other semiconductors. It means a test path for diagnosing the connection status with the integrated circuit (boundary scan test).

Next, an example of a test procedure when the test method according to the present invention is applied to the system LSI shown in FIG. 1 will be described with reference to FIGS. FIG. 7 shows an outline of the test procedure of the entire LSI, and FIGS. 8 to 11 show specific examples of the test procedure of each block constituting the LSI.

According to the test method according to the present invention, as shown in FIG. 7, first, the FPGA 120 is inspected using the function of the cell logic block described above, and it is determined whether there is a defect. Avoidance of a defective part is performed (steps S1 to S3). Next, a test circuit (ALPG) for testing the SR AMI 40 is constructed in a portion of the FPGA 120 excluding the defective portion, and the test of the SRAM 140 is executed (steps S 4 and S 5).

If no defective part is found in the SRAM 140, a test circuit (logic test section) for testing the custom logic circuit 110 and the CPU 130 is constructed in the portion of the FPGA 120 excluding the defective part. The tests of the custom logic circuit 110 and the CPU 130 are executed (steps S6 to S8). At this time, a test pattern is created using SRAM that has already been tested. A turn or test pattern generation program is stored.

If no defect is found, a test circuit (ALP G) for testing the DRAMs 150 to 180 is constructed in the portion of the FPGA 120 excluding the above defective parts, and the DRAMs 150 to 180 are sequentially tested. It is performed (Steps S9, S10). If a defective part is found, it is stored in the SRAM 140 or an external storage device, and then the defective bit is rescued by using the redundant circuit provided in the DRAMs 150 to 180. The rescue program is read by the CPU 130, and the program is executed by the CPU 130 to perform bit rescue (steps S11 and S12). After that, a part of the custom logic such as the user logic is formed in a portion of the FPGA 120 excluding the defective portion, and the system is completed as a system LSI (step S13). In step S13, first, the TAP 210 is set to the access mode of the connection information storage memory cell SMC in the FPGA 120, and then the failure is determined by using the information indicating the failure location obtained in step S1. A desired logic is constructed by writing a data which constitutes the user logic so as to avoid the place in the memory cell SMC of the normal crosspoint switch in the FPGA 120.

FIG. 8 shows a more detailed procedure of the self-verification of the custom logic circuit (FPGA) 120 in steps S1 to S3 of the flowchart of FIG. When the power supply voltage is applied to the device (system LSI) of the present embodiment, the logic gate circuits LG 1 and LG 2 of the cell logic block CLB constituting the FPGA 120 are activated, and if there is a defect, the logic is activated. The output of the gate circuit LG1 goes low, and the output state is stored in the connection information storage memory cell SMC (step S111).

Next, using the tester 500, a code to be set in the test mode select signal TMS function register 214 is input to the TAP 210 as the test interface circuit, and the TAP 210 is connected to the FPGA 120. The access mode is set for the memory cell SMC for connection information storage (step S112). Next, data indicating normality for the memory cell SMC (the cell theory The logic level (the logic level opposite to the logic level indicating the defect state by self-verification of the logical block CLB) is written (step S113). Next, data is read from the memory cell SMC (step S114).

Then, by comparing the read data and the write data, it is determined which cell logic block CLB has a defect (step S115). Further, for example, by writing and reading the reverse of the write data, a cross-point switch CSW having a defect in the memory cell SMC itself can also be detected.

Next, at test 500, a map of a normal cross-point switch CSW and a cell logic block CLB is created based on the above determination result (step S116). The created map, that is, the information indicating whether the cross point switch CSW and the cell logic block CLB are normal or abnormal is stored in a storage device or the like in the tester 500. Then, the HDL description of the SRAM test (ALPG) to be built on the FPGA 120 is read from a data pace and the like, and the logic synthesis is performed at the test 500, and the defective crosspoint switch C SW and the cell are determined based on the above map. Data for constructing an ALPG (Algorithmic Memory Pattern Generator) avoiding the logic block CLB is generated (step S117). Then, the generated data is stored in a storage device or the like in the tester 500 (step S118). This data is data for selectively turning on the normal cross-point switch CSW switch MOSFETQsw according to the logic to be configured.

FIG. 9 shows a more detailed procedure for inspecting the SRAM section 140 in steps S4 to S5 of the flowchart of FIG.

In the inspection of the SRAM section 140, first, a control signal is supplied from the tester 500 to the TAP 210 to select the memory cell SMC for storing the crosspoint switch control information in the FPGA 120 (step S121). Then, the data for constructing the ALPG stored in the storage device in step S118 is transferred to the selected memory cell SMC (step S122). This creates a test pattern for testing SRAM in FPGA 120. A test circuit including a possible ALPG is constructed. The structure of the ALPG built in the FPGA 120 and the specific method of building the ALPG will be described later in detail.

Next, a program for operating the ALPG to generate a test pattern is written by the tester 500 into the memory circuit in the FPGA 120 via the TAP 210 (step S123). This memory circuit is composed of the cell logic block CLB and the crosspoint switch CSW constituting the FPGA 120 when the ALPG is constructed in step S122.

Subsequently, the control signal is supplied from the tester 500 to the TAP 210 to set the SRAM section 140 to the selected state (step S124). Then, the ALPG in the FPGA 120 is activated, the test pattern generation program written in step S123 is executed to generate a test pattern, and the generated test pattern is transferred via the bus 200 or the like. The test is supplied to the selected SRAM section 140, and the test result is output to the outside (tester 500) via the TAP 210 (steps S125 and S126).

Then, the tester 500 determines whether there is a defect in the SRAM section 140 from the output test result and sorts out a non-defective product and a defective product (step S127). The write data formed by the ALPG built in the FPGA 120 is output to the outside as an expected value, and the data read from the SRAM is also output to the outside. It is also possible to configure so as to judge the presence or absence of a defect by comparing the read data with the read data. Instead of storing the test pattern generation program in a memory circuit configured in the FPGA, an instruction code for configuring the test pattern generation program may be sequentially input from outside via a TAP.

FIG. 10 shows a more detailed procedure for checking the logic unit, that is, the custom logic unit 110 and the CPU unit 130 in steps S6 to S8 of the flowchart in FIG.

In the inspection of the logic units 110 and 130, first, in the tester 500, a data for constructing a logic test in the FPGA 120 is created. Step S1 3 1). At this time, a logic tester is constructed by using the map of the normal cell logic block CLB and the crosspoint switch CSW generated in step S116 of the FPGA self-verification flow in Fig. 8 to avoid faulty circuits. Is created.

Next, a control signal is supplied from the tester 500 to the TAP 210 to select the memory cell SMC in the FPGA 120 for storing the cross-point switch control information (step S132). Then, the data for constructing the logic test stored in the storage device in the above step S131 is transferred to the selected memory cell SMC (step S133). As a result, a test circuit capable of generating a test pattern for testing a logic part is built in the FPGA 120. At this time, a program memory may be configured in the FPGA, and a program for operating the logic tester may be transferred to the configured memory. The structure of the logic tester built in the FPGA 120 and the specific procedure for building the logic tester will be described later in detail.

Next, a control signal is supplied from the tester 500 to the TAP 210 to select the SRAM section 140 for which the flow inspection in FIG. 9 has been completed (step S134). Then, a program for generating a test pattern for testing the custom logic section 110 prepared in advance in the test section 500 is written into the SRAM 140 via the tap 210 by the test section 500. (Step S135). Like a program that generates a test pattern for an SRAM, storing it in an SRMA that has been inspected without storing it in the memory circuit in the FPGA generally uses a logical circuit test pattern rather than a memory test pattern. This is because the longer one requires a larger memory area.

Subsequently, the logic test in the FPGA 120 is started, and the test pattern generation program written in the SRAM 140 in step S135 is read to generate a test pattern, and the custom logic unit is generated. It is supplied to 110 (step S136). Then, the output signal from the custom logic section 110 is compared with the expected value, and the test result is output to the outside (test section 500) via the TAP 210 (step S137). Then, the tester 500 determines whether or not there is a defect in the custom logic section 140 based on the output test result, and selects a non-defective product and a defective product (step S138).

Next, a test pattern generation program for inspecting the CPU 130 prepared in the tester 500 in advance is transferred to the SRAM 140 (step S139). Subsequently, the logic test in the FPGA 120 is started up, and the test pattern generation program written in the SRAM 140 in step S135 is read and supplied to the CPU 130 while generating a test pattern (step S140). . Then, the output signal from the CPU 130 is compared with the expected value, and the test result is output to the outside (test 500) via the TAP 210 (step S141).

Then, the tester 500 determines whether there is any defect in the CPU 130 based on the output test result and sorts out a non-defective product and a defective product (step S142).

FIG. 11 shows a more detailed procedure of the inspection of the DRAM units 150 to 180 in steps S9 to S12 of the flowchart of FIG.

DRAM section 1.50 ~: In the test of L80, first, at test 500, a test for constructing an ALPG (Algorithmic Memory Pattern Generator) capable of generating test patterns for testing DRAM in FPGA 120 Create (step S151). At this time, using the map of the normal cell logic block CLB and the crosspoint switch CSW generated in step S116 of the FPGA self-verification flow of FIG. 8 to avoid the faulty circuit and construct the ALP G A day is created. Note that ALP G for DRAM inspection is almost the same as ALP G for SRAM inspection, and the refresh operation is normal.

The difference is that processing for judging abnormalities has been added.

Next, a control signal is supplied from the tester 500 to the TAP 210 to select the memory cell SMC in the FPGA 120 that stores the crosspoint switch control information (Step S152). Then, the data for constructing the ALPG created in step S151 is transferred to the selected memory cell SMC (step S153). This allows testing of DRAM in FPGA 120 A test circuit including ALP G is built. The structure of the ALPG built in the FPGA 120 and a specific method of building the ALPG are almost the same as those of the ALPG for inspecting the SRAM, which will be described later in detail.

Next, a program for operating ALPG to generate test patterns is provided by Tester 500? Through 210? The data is written into the memory circuit in the address 120 (step S154). This memory circuit is configured by the cell logic block CLB and the crosspoint switch CSW constituting the FPGA 120 when the ALPG is constructed in step S153. Note that the test pattern generation program may be stored in the SRAM 140, or an instruction code may be sequentially input from the outside to the ALPG in the FPGA at the time of DRAM testing.

Next, a control signal is supplied from the tester 500 to the TAP210 to

140 is selected (step S155), and a fail memory for storing the position of a defective bit detected in a DRAM test (step S159) described later in the SRAM (step S156). ). Next, a control signal is supplied from the tester 500 to the TAP 210 to set the CPU section 130 to the selected state (step S157), and a rescue program for relieving defective bits of the DRAM is stored in the memory in the CPU 130. Transfer (step S158). This rescue program may be stored in the SRAM 140.

This rescue program uses the above DRAM in accordance with a predetermined replacement algorithm.

A replacement address is set in an address conversion circuit in a redundant circuit provided along with 150, and a memory row or a memory column containing a defective bit is replaced with a spare row or a spare column. The redundant replacement algorithm, which selects the most appropriate spare memory row or spare memory column based on the test results and replaces the defective bit, is known per se and can be used for this embodiment. Does not require a new replacement algorithm.

Then, a test signal is supplied to the TAP 210 by the tester 500 to set the DR AML 50 to the selected state. Then, the ALPG in the FPGA 120 is activated, and the test pattern generation program written in step S154 is executed. Then, a test pattern is generated, and the generated test pattern is supplied to the selected DRAM unit 150 to perform a test, and the result, that is, the position of the defective bit is stored in the fail memory configured in the SRAM 140 (step S 159). In the DRAM test in step S159, in addition to the read / write test similar to the SRAM test, a test as to whether a normal refresh operation is performed is also performed.

Next, the CPU 130 is activated to execute the rescue program. Based on the information on the defective bits stored in the fail memory (SRAM 140), the memory row or column containing the defective bit is replaced with the spare row or spare column. Then, a bit rescue process is performed (step S160). Thereafter, a test as to whether or not the rescue has been performed normally is performed as a series of operations of the rescue program (step S161). Then, the test result is output to a tester 500 outside the chip.

Then, the tester 500 determines whether there is a defect in the DRAM section 150 based on the output test result, and sorts out a non-defective product and a defective product (step S162). When the test and bit rescue of the DRAM unit 150 are completed, the process returns to step S159, and the test, the bit rescue and the judgment of the test result are similarly performed on the other DRAM units 160, 170, and 180. Next, the details of the ALPG built in the FPGA 120 when the SRAM 140 is inspected will be described. For example, as shown in FIG. 12, the ALPG is composed of an instruction memory 411 storing a microprogram consisting of a plurality of microgroove instructions described according to a predetermined test pattern generation algorithm, and an instruction memory 411. A program counter 412 for specifying an instruction address of a microinstruction to be read, a control signal for a memory circuit section by decoding an instruction code in a microphone instruction read from the instruction memory 411, a program counter 412, etc. A sequence control circuit 413 for forming a control signal for an internal circuit in the test circuit; and a sequencer for generating a test address according to the microinstruction read from the instruction memory 411. A dress operation circuit 414, a test data generation circuit 415 for generating test data and expected value data in accordance with the read microinstruction, and a data read from the SRAM section 140 by the test address. It is composed of a comparison / determination circuit 416, etc., which compares the data with the expected value data generated by the test data generation circuit 415 to determine whether or not the data has been written normally. .

The judgment result in the comparison judgment circuit 416 is configured to be output to the outside of the chip via the TAP 210 as a judgment signal F indicating data match Z mismatch. The test pattern generation algorithms themselves are known, and by applying them, a new algorithm is not particularly required for this embodiment.

The plurality of microinstructions stored in the instruction memory 411 can be described using an existing test language or test language. A test pattern (address and data) is generated according to the predetermined algorithm defined by the plurality of instructions. The tester language is regarded as an effective instruction language for efficiently generating a test pattern including an address and a data. The test language is a language used in the test industry, for example, a language compatible with Adpantest's test language. This is because the program data of the existing test pattern can be used. The language for describing the predetermined algorithm is not limited to the test language, but may be any instruction language capable of generating a test pattern including an address and a data pattern.

When the instruction memory 411 is constituted by SRAM memory cells, it is necessary to load a program into the instruction memory before performing the test. When the FPGA 120 includes a non-volatile memory, the above program is stored in a part of an address area of the nonvolatile memory, and the above program is stored in response to the shift to the SRAM test mode. It is preferable to load the above program from the address area to be stored to the above instruction memory 411. Instead of providing instruction memory 4 1 1, continuous instruction code The sequence may be sequentially input to the ALPG sequence control unit 414 built in the FPGA 120 to generate a test pattern of the SRM A.

When a CPU 130 and a custom logic circuit 110 are provided in addition to the memory like the system LSI of FIG. 1 to which this embodiment is applied, as shown in FIG. 180), the CPU 130, the custom logic circuit 110, and the FPG A 120 on which the test circuit is built, and a variable bus configuration in which a dedicated bus 220 and a signal switching circuit 230 including switching switches SWl to SWn are provided. Good.

The signal CS for controlling the switching switches SWl to SWn in the signal switching circuit 230 may be generated by an instruction in the ALPG when testing the memory circuit, and may be applied to the switches SWl to SWn. No. Further, the switching control signal CS may be formed based on a test mode designation signal supplied from the outside.

In addition, the above-mentioned switching switches SWl to SWn are connected between the memory circuit 140 and the CPU 130 and the custom logic circuit 110, or are the memory circuits 140 and 800 built? It is preferable that not only the connection switching between the CPU 120 and the custom logic circuit 110 but also the FPGA 120 be connected.

FIG. 14 shows an example of the configuration of the instruction format of the microinstructions stored in the instruction memory 411. As mentioned earlier, the format of this microinstruction is based on the test language.

The microinstruction of this embodiment includes an address field MFa for storing a PC address indicating a jump address of an instruction used in a jump instruction, an operation code field MFb for storing a sequence control code, and instruction repetition. An operand field MF c for storing numbers and the like, a control field MF d for storing a control code for instructing output and read / write of address data, and an address operation code field for storing an address operation instruction code MF e and data storage where the data generation instruction code is stored It consists of a composite code field MF f and so on. Address field MFa is considered as the field that specifies the address of the next instruction to be executed.

The feature of the microinstruction as the test language used in this embodiment is that two instructions are executed in parallel by specifying a test address operation and a data operation with one instruction.

FIG. 15 shows a configuration example of the sequence control circuit 4 13. The sequence control circuit 4 13 according to this embodiment includes an instruction decoding control section 4 30 including a decoder for decoding a control code in the operation code field MFb to form a control signal, and a program counter 4 1. Increment 431 for incrementing the value of 2 to `` +1 '' and either the above increment 431 or the jump address in the address field MFa are selected and supplied to the program counter 412. Multiplexer 432, a plurality of index registers 433 holding the number of repetitions in the operand field MFc, and a decrement register 4-3 for decrementing the value of the index register 433. 4, a working register 435 composed of a plurality of planes or ways holding the value of “1 1”, and a flag indicating the presence / absence of data inversion used in the jXd instruction (see Table 1) described later. Lag 433, a plurality of flags 433 indicating whether or not the operand used in the jindex instruction is transferred to the program counter 412, and the values of the registers 433, 435 are selectively decremented as described above. It is composed of a plurality of multiplexers 4 3 8 to be supplied to 3 4 and a demultiplexer 4 3 9 which distributes the value of the decrement 4 3 4 to one of the planes of the single king register 4 3 5.

Table 1 shows the types and contents of the opcodes used for the sequence control, which are defined and stored in the opcode field MFb in the microinstruction. 【table 1】

In Table 1, the instruction indicated by “nop” is a no-operation instruction that instructs the value of the program counter 412 to “+1” in increments 43 1 and returns to the program count 412, that is, other than the update of the program count. Is an instruction to move to the next instruction without performing any operation.

“Jindexlj to“ jindex4j ”are instructions prepared to turn the loop of the instruction by jumping. In the memory pattern test, the same instruction is repeatedly executed many times using the jump instruction. In some cases, the number of instructions, that is, the program length, can be reduced (for example, writing “1” to all memory cells and reading them out by incrementing the address to the final address). In this embodiment, an index register 433 is provided so that the number of loops (jumps) can be set. In addition, in order to be able to execute multiple types of judgment methods, jump instructions, index registers 433 and working registers 4 35 are provided for each of them.

Since each jump instruction has the same control content, the control operation by “jindexl” will be described below, and the description of other jump instructions “jindex2” to “jindex4” will be omitted. When the jindexl instruction is read from the operation code field MF, it is determined whether it is the first jindexl instruction, and the determination result is reflected in the flag 437. Specifically, the flag jfl = 1 is set for the first jindexl, and jf1 = 1 for the second and subsequent times.

When the jindexl instruction is read when the flag jf 1 = 0, the multiplexer 432 is set so that the PC address as the jump address in the address field MFa of the microphone instruction is set to the program counter 412. Controlled. As a result, the execution sequence of the microinstruction is jumped to that address, and the flag jf1 is set to "1". At the same time, the number of loops defined in the operand field MFc is read into idx of the index register 433.

When the jindexl instruction is read when the flag jfl = l, the PC address in the address field MFa of the microphone instruction is set to the program counter 412. Then, the number of loops in idxl of the index register 433 is supplied to the decrement unit 434 via the multiplexer 438 and decremented to "1". The decremented value is stored in idxwl of the working register 435 via the demultiplexer 439. When the idxwl of the working register 435 becomes “0”, the PC address in the micro-instruction address field MFa is not set to the program counter 412, but the address of the program counter 412 is incremented by 431. The multiplexer 432 is controlled so as to return “+1” to the program counter 412.

Therefore, if the jindex instruction is defined or described in the opcode field MFb of the microinstruction and the PC address as the jump destination address of the microinstruction is defined or described in the address field MFa, the operand field MFc is defined. The same jindex for the number of loops specified in The instruction is repeatedly executed, and finally, the program counter 412 is incremented, and control is performed so as to proceed to the next microinstruction and exit from the loop.

The “j xd” instruction in Table 1 refers to df lg in the flag 436, and is used to operate the value of the program counter according to the value of the df 1 g flag. When the df lg flag in the flag 436 is the first value such as “0”, the “j xd” instruction transfers the operand to the program counter, and transfers the program to the instruction at the jump destination address indicated by the operand. Jump, and set the df 1 g flag to a second value, such as "1". On the other hand, when the df lg flag is a second value such as “1”, the “j xd” instruction increments the value of the program power, returns to the program counter, and df 1 g Reset the flag to a first value, such as "0".

"The jmpj instruction is an instruction that transfers the operand to the program counter and causes the program to jump to the instruction at the jump address indicated by the operand.

The “stop” instruction is a stop instruction that instructs to end the sequence control.

FIG. 16 shows a configuration example of the address calculation circuit 414. The address calculation circuit 414 of this embodiment is roughly composed of an X address calculation section 441 for generating an X address and a Y address calculation section 442 for generating a Y address. Since the X address operation unit 441 and the Y address operation unit 442 have almost the same configuration, the configuration of the X address operation unit 441 will be described below, and the description of the configuration of the Y address operation unit 442 will be omitted. In addition, by providing an impossible Z address operation unit as necessary, it is possible to generate a partial pattern (partial pattern).

The X address calculator 441 selects an initial value register Xhold for storing the initial value of the X address, a zero setting means 443 for holding “0”, and either the initial value of the X address or “0”. Multiplexer MUX 1 and selected The base register Xbase holding the initial value or `` 0j '', the first arithmetic unit ALU1 that adds the value of the register Xbase, and the arithmetic result of arithmetic unit ALU1, or either `` 0 '' or the feedback value A second multiplexer MUX2 for selecting the current value, a current register Xcurrent for holding the selected value, a second arithmetic unit ALU2 for adding or subtracting the value of the register Xcurrent, and a second arithmetic unit ALU2 or It comprises a third multiplexer MUX3 for selecting one of the outputs of the first arithmetic unit ALU1, and an inverter I NV capable of inverting the selected output.

This impulse INV is provided in a memory pattern test because a malfunction due to switching noise of the address signal may be tested. In this case, it is necessary to output an inverted signal of the address signal. By using this impulse signal NV, an inverted signal of the address signal in the above test can be easily formed.

Although not particularly limited, in this embodiment, the X addresses generated by the arithmetic units ALU 1 and ALU 2 of the X address arithmetic unit 441 are sent to the Y address side, and the Y address generated by the Y address arithmetic unit 442 is The third multiplexer MUX 3 is configured to output the data to the X address side.o

Thus, it is configured to be used as a test circuit for any of a plurality of types of memories, for example, an address multiplex type memory and an addressless multiplex type memory. In other words, by simply rewriting the microinstruction stored in the instruction memory 411, it is possible to generate or check a test pattern required for all the memories.

The difference between the X address operation unit 441 and the Y address operation unit 442 is that the first operation unit ALU 1 of the Y address operation unit 442 overflows when the first operation unit ALU 1 of the X address operation unit 441 overflows. On the other hand, the borrow signal BR is supplied.

Table 2 shows the description in the operation code field MFe in the above microinstruction. The types and contents of the operation codes used for the Y address operation (base operation) in the first arithmetic unit ALU 1 of the Y address operation unit 442 where the first definition is stored are shown.

[Table 2]

In Table 2, Ybase-0 is an instruction to set the value of the pace register Ybase to “0”. Ybase — Yhold is an instruction to put the contents of the initial register Yhold into the base register Ybase. Y base Y base + 1 is an instruction to increment (+1) the value of the pace register Y base and return it to the register Y base. Ybase — Y base + 1 (BR) is the base register. If the value of Xbase is not the maximum value, leave the value of Y base as it is, and if the value of Xbase is the maximum value, increment the value of Ybase and register This is an instruction to return to Ybase. At this time, the Porro signal BR is supplied from the first arithmetic unit ALU 1 to the second arithmetic unit ALU 2.

Table 3 shows types and contents of operation codes used for the address operation in the first arithmetic unit ALU1 of the X address operation unit 441.

Table 4 shows the types and contents of operation codes used for the Y address operation (current operation) in the second arithmetic unit ALU2 of the Y address operation unit 442.

Table 5 shows the addresses of the XLU 441 It shows the types of operation codes used in the address operation and their contents.

In Table 4, the left column is the ALPG description described using the tester language, and the right column is the corresponding function operation level description. This description can be described according to the rules of the hardware description language (HDL description) to express the function.

[Table 3]

Xbase operation operation

Xbase <-Xbase on Operation

Xbase <-0 0 → Xbase

Xbase Xhold Xhold → Xbase

Xbase <-Xbase + 1 Xbas9 + 1-→ Xbase

Xbase <-Xbase-1 Xbase-1 → Xbase

[Table 5]

FIG. 17 shows a configuration example of the test data generation circuit 415. The test data generation circuit 415 of this embodiment includes an initial value register Tphold for storing the initial value of write data or an expected value, an impeller INVERT1 capable of inverting the value of the initial value register Tphold, and a test to be output. It comprises a base data register Tp for holding data or a reference data of an expected value, an arithmetic unit ALU having a bit shift function, and an inverter INVERT2 capable of inverting the output of the arithmetic unit ALU. In the above embodiment, the bit width is set to 18 bits. However, if necessary, the test data circuit can be expanded to have a desired bit width.

Table 6 shows the types and contents of the control codes used for the operation control in the test data generation circuit 415 defined or described in the data generation code field MFf in the microinstruction. . In Table 6, instructions represented by the same rules as the instructions in Tables 3 to 5 are almost the same.

Tp Tp * 2 controls the register bit and the arithmetic unit ALU, processes the 18-bit data in the register bit Tp with the arithmetic unit ALU, and shifts the bit string to the MSB side or LSB side by one bit. It is an order to return to Regis Tp. This instruction writes data “1” to memory cells one bit at a time, even if the memory unit is a type of memory that reads and writes data in units such as one word or one byte. The test data can be generated relatively easily. [Table 6]

Table 7 shows an example of a list of microinstructions for a marching test, one of the memory test methods.

The marching test is performed as follows. Of all the bits of the memory cell in memory array 1, one bit is selected in order. The selected memory cell is written with the data of “0 j.” Then, the written data of “0” is read. Subsequently, of all the bits, one bit is selected in order. The data "1" is written to the selected memory cell. After that, the written “1” data is read out, and the presence or absence of a defect is determined by comparing the data with the expected value.

As an example, a marching test assuming a memory array having a 4-bit X address and a 4-bit Y address and a storage capacity of 256 bits will be described.

[Table 7]

In Table 7, the symbols W and R are control codes that indicate read / write to the memory as described or defined in the control field MFd. This control code is represented by bits corresponding to W and bits corresponding to R, that is, two bits. The number described in the “PC address” column indicates the jump destination address. Means to shift to the microphone mouth instruction of the number described in the column and loop or jump. The symbols X «~ Xbase, Y Ybase described in the column of“ Control command etc. ”mean that the values of the pace registers Xbase, Ybase are output as dresses and Y addresses, respectively.

FIGS. 18 and 19 show the microinstruction list of Table 7 when the SRAM140 marching test is performed by the test circuit (ALPG) including the control unit and the arithmetic unit of the microprogram control method. An example of a processing flow according to this is shown. Among them, FIG. 18 shows the flow of sequence control using the obecode and operands in the microphone instruction. Also, FIG. 19 shows test addresses and test data (write data, expected data, etc.) based on address operation codes and data generation codes which are executed in parallel with the sequence control flow shown in FIG. The following figure shows the flow of generating value data. These processes are executed by operating the sequence control circuit 413, the address calculation circuit 414, and the data generation circuit 415 using the instruction codes described in Tables 1 to 6 described above. can do.

Hereinafter, the procedure of the marching test will be described while associating the steps of FIGS. 18 and 19 with each other.

When the address of the first instruction shown in the list of Table 7 is set as a start address in the program counter 4 12 from the outside, the flows in FIGS. 18 and 19 are started. First, when the first microinstruction in Table 7 is read from the instruction memory 4 11 1, the operation code is “nop”, so the sequence control circuit 4 1 3 does nothing and just adds 1 program counter 4 1 2 Proceed only (step S201). On the other hand, the address calculation circuit 4 14 and the data generation circuit 4 15 respectively store the initial value `` 0 '' in the initial value registers Xhold, Yhold and Thold in the base registers Xbase, Ybase and Tp. Set (Step S2 2 1).

Next, the second microinstruction in Table 7 is read out because the program count 412 has been incremented in step S201. Since the opcode of the second microinstruction is "jindex l ι, In the circuit 413, the number of repetitions of the operand is set to the index register idx1 (step S202).

The first set value of the index register idx1 corresponds to the capacity (number of bytes or words) of memory array 1. On the other hand, the address operation circuit 414 outputs the values of the base registers Xbase and Ybase as the X address and the Y address, respectively, using the operation code X—Xbase and YYbase. The data generation circuit 415 outputs the value “0” of the register Tp. At this time, a control signal W (write) is output. As a result, in the memory array 1, the memory cell corresponding to the X, Υ address output from the address operation circuit 414 is selected and data “0” is written (step S222).

The sequence control circuit 413 decrements the value of the index register idx1 by the operation code "jindexlj" and puts it into the working register idxw, and repeats the same instruction until it becomes "0" (steps S203 and S204). .

In addition, the address calculation circuit 414 increments the value of the base register Xbase, that is, the X address, by the operation code Xbase Xbase + 1, and the Y address when the base register Xbase reaches the maximum value by Ybase Ybase + 1 (BR). Increment. Since the initial setting value of the index register idx1 is the same as the capacity of the memory array 1, by repeating the above operation, data `` 0 '' is written to all the memory cells in the memory array 1 in order. (Steps S223, S224) o

When the value of the working register i dxw becomes “0 j”, the sequence control circuit 413 increments the value of the program counter 412 and reads the third microinstruction in Table 7. The opcode is “nop”. Therefore, the sequence control circuit 413 does nothing and advances the program counter 412 by one (step S205).

On the other hand, the address operation circuit 414 increments the X and Y addresses according to the operation code of the third microinstruction, and then sets the pace register X The values stored in base and Ybase are output as X address and Y address, respectively. At this time, the values of the base registers Xbase and Ybase have returned to “0”. At this time, the data generation circuit 415 outputs “0”. Also, a control signal R (read) is output according to the control code of the control field MFd. As a result, the data at the address is read out and compared with the expected value data “0” (steps S225, S226) o

Next, since the program counter 412 has been incremented in step S205, the fourth microinstruction in Table 7 is read. Since the operation code of the fourth microinstruction is “jindex l”, the sequence control circuit 413 sets the number of repetitions of the operand to the index register id x 1 (step S 206). The first set value of the index register id x 1 corresponds to the capacity of memory array 1 (number of bytes or words). However, since the jindex 1 instruction code of the fourth instruction has a different PC address (jump address) from the jindex l instruction code of the second instruction, it returns to the third instruction (opcode is “no op”) after execution.

On the other hand, the address arithmetic circuit 4 14 outputs the values of the pace registers Xbase and Ybase as the X address and the Y address, respectively, using the operation code X Xbase and Y Y base. In addition, the data generation code D invert outputs data “1” obtained by inverting the value “0” of the register Tp from the data generation circuit 415. Then, at this time, the control signal W (write) is output. As a result, in the memory array 1, "1" is written to the memory cell at the output X, Υ address (step S227).

The sequence control circuit 4 13 decrements the value of the index register idxl by the operation code “jindex l” and puts it in the working register id Xw, and returns to the “nop” instruction and repeats until it becomes “0” (step S207, S208) o In the address operation circuit 414, the operation code Xbase—Xbase + 1 increments the value of the base register Xbase, ie, the X address, by the operation code Xbase—Xbase + 1, and Ybase—Ybase + 1 (BX) When the base register Xbase reaches the maximum value, the Y address is incremented. Above Inn Since the initial set value of the dex register i dx 1 is the same as the capacity of the memory array 1, all the memory cells in the memory array 1 are read out in order by the above three steps and compared with the expected value. Thereafter, the operation of writing "1" to the address is repeated (steps S227 and S228). Next, the fifth microinstruction in Table 7 is read. Since the operation code of the fifth microinstruction is "jindexl", the sequence control circuit 413 sets the number of repetitions of the operand to the index register idx1 (step S209). The first set value of index register idx1 corresponds to the capacity of memory array 1 (number of bytes or words). The fifth jindexl instruction code has the same PC address as the second jindex1 instruction code, and is an instruction that repeats the same instruction. On the other hand, the address operation circuit 414 outputs the values of the base registers Xbase and Ybase as the X address and the Y address, respectively, using the operation code X—Xbase and Y-Ybase. In addition, the data generation circuit 415 outputs data “lj” obtained by inverting the value “0” of the register Tp according to the data generation code D invert. At this time, the control signal R (write) is output. As a result, in the memory array 1, data is read out from the memory cell specified by the output X and Y addresses (step S229).

The sequence control circuit 413 decrements the value of the index register idx1 by the opcode "jindexl" and puts it into the king register idxw, and repeats the "jindexl" instruction until it becomes "0" (step S2 10, S11). In addition, the address calculation circuit 414 increments the value of the base register Xbase, that is, the X address, by the operation code Xbase—Xbase + 1, and increments the Y address when the base register Xbase reaches the maximum value by Ybase—Ybase + 1 (BR). . Since the initial setting value of the index register i dxl is the same as the capacity of the memory array 1, by repeating the above operation, all the memory cells in the memory array 1 are sequentially read and the expected value is obtained. It is compared with "1" (steps S230, S231). Next, the sixth microinstruction in Table 7 is read. Since the operation code of the sixth microinstruction is “j xd”, the sequence control circuit 413 jumps to the jump address indicated by the PC address in the address field MFc. In this embodiment, the processing returns to the second instruction “jindexl” in Table 7. Then, when the jindexl instruction is read again, the flag df 1 g is set to “lj.” As a result, in the second sequence processing, “YE S” is determined in step S212 in FIG. To complete the marching test.

On the other hand, at the time of execution of the microinstruction list in the second cycle, in steps S222 to S231 in FIG. 19, the data generation circuit 414 sets the write data and the expected value data to “1”, and continuously writes all bits. After writing, the written data is read one bit at a time, inverted data “0” is written to it, and then all bits are read continuously. In the flow of FIG. 19, in step S232, it is determined whether the writing / reading of data opposite to the first cycle as described above in steps S222 to S231 has been completed (back data end determination). Is performed. Note that the back data generation for performing the inspection using the back data is controlled by Thold INVERT and dflg in FIG.

As described above, the control in accordance with the flow charts of FIGS. 18 and 19 uses the instruction codes described in Tables 1 to 6 to store the microinstructions in the instruction memory 411 in the instruction list in Table 7 below. Thus, a marching test can be performed with only six microphone mouth commands.

Further, in the test circuit (ALPG) of the above embodiment, in addition to the marching test, “0” or “1” is set to all memory cells by using the instruction codes described in Tables 1 to 6. Check whether it can be written All "0" judgment test or all "1" judgment test, or write "1" to a certain bit and check all bits to make sure that other bits are not erroneously written. N ² square pattern test (or gear Rocking test) can also be performed.

Table 8 shows the microinstruction list for N ² square pattern test. Note that ixd is an instruction to generate a back test pattern by controlling INVERT, which is controlled by a flag df lg below the initial value register Tphold. When the flag df1g is 0, the value of the initial value register Tphold is stored in the register Tp as it is, and when the flag dflg is 1, the reverse pattern is set in the register Tp.

[Table 8]

In the above embodiment, the value to be initially set in the program counter evening 4 12, by changing the instruction address of the first microinstruction shown in Table 7 and Table 8, start the marching test or N ² square pattern test Can be done.

Next, the details of the logic test constructed in the FPG A 120 when the custom logic unit 110 and the CPU 130 are inspected will be described.

The logic tester has a configuration similar to the ALPG shown in Fig. 12 for generating a memory test pattern, and is described in accordance with a predetermined test pattern generation algorithm, for example, as shown in Fig. 20 An instruction memory 411 storing a microprogram consisting of a plurality of microinstructions, a program counter 412 for specifying a microinstruction to be read from the instruction memory 411, and a microinstruction read from the instruction memory 411. Decodes the instruction code and sends it to the circuit in the control unit 400 such as the program counter 412. A command decoding control circuit 430 for forming a control signal, a timing generator 420 for forming a timing control signal based on the reference clock 00, and a timing generator 420 based on a timing setting bit MF d (TS bit) in the microinstruction. Data register set 417 that outputs control data to the microcontroller, a decoder 418 that decodes the timing setting bit MF d (TS bit) in the micro instruction and reads control data from the data register set 417 ing.

Also, among the logic circuits to be tested, circuits whose functions are specified (for example, ALU: Arithmetic Logic Unit) often have an appropriate test pattern formation method already established. By using the test pattern assets, it is possible to generate efficient test patterns. For combinational logic circuits, a fault assumption method and a method of generating an efficient test pattern called the D algorithm based on the idea of a single fault, where one circuit has one fault, are known. . By using this method, the microprogram for generating the test pattern can be shortened, and the capacity of the instruction memory 411 can be suppressed to an achievable level.

In this embodiment, although not particularly limited, the timing setting bit TS decoded by the decoder 418 is composed of two bits, and seven control data are stored in the data register set 417. . One of these control data is the data "RATE" that defines the test cycle, and the remaining six control data determine the output timing of the high-level or low-level signal for each signal line of the test-only path. Two types of control data "ACLK 1" and "A CLK 2" to be given, and two types of control data "BC LK 1" and "BC LK 2" to give the rising timing of the pulse signal and the falling edge of the pulse signal There are two types of control data "CCLK1" and "CCLK2" which give the timing and the comparison output timing with the expected value.

When each of these control data is supplied to the timing generation section 420, the control data RATE is converted into a signal RATE having a predetermined timing. The micro instruction code is supplied to the gram counter 412 and the micro instruction code from the instruction memory 411 is fetched. When "ACLK 1" to "CCLK 2" are supplied to the evening timing generator 420 as control data, a clock corresponding to the control code is generated from the timing clocks ACLK 1 to CCLK 2 and a comparator is generated. Output to 300. Connection and selection for use of each clock are appropriately performed as needed.

Further, at the logic test evening, one of the increment address 421 for incrementing the value of the program count 412 to “11” and the jump address 421 in the increment evening 421 or the destination address in the address field MF a A multiplexer 422 for selecting the value of the index register 423 and supplying the same to the program counter 412, an index register 423 for holding the number of repetitions in the operand field MFc, and a decrement register for decrementing the value of the index register 423 to "1". 424, holds the value decremented to "1 1" キング King Register 425, Flag 427 indicating whether or not operands used in a given instruction are transferred to the program counter 412, Register 423, 425 Multiplexer 428, which selectively supplies the value to the above-mentioned decremen 424, decremen 424 A demultiplexer 429 for distributing to some plane is provided.

This logic tester has an operand field MFc for storing the number of instruction repetitions in the micro-instruction code and an index register 423 for holding the number of repetitions, so that the same test signal can be repeatedly generated. In this case, the number of required microinstructions can be reduced and the microprogram can be shortened. Further, in this embodiment, since the index register 423 and the king register 425 and the flag 427 are provided in a plurality of planes (four in the figure), the sub-loop processing within a certain loop processing and the sub-loop processing are further performed. It is possible to easily execute sub-loop processing in the inside, and to shorten the microprogram. FIG. 21 shows an embodiment of the signal forming / comparing unit 300. Note that the circuit in FIG. 21 corresponds to one of the signal lines constituting the test bus 220. Although only the corresponding driver / comparator circuit is shown as a representative, actually, the circuits shown in FIG. 21 are provided for the number of signal lines constituting the test path 220.

As shown in FIG. 21, the driver / comparator circuit of this embodiment includes a driver circuit (signal forming circuit) 340 that forms a signal to be output to a tester dedicated bus, and a signal on the tester dedicated bus and an expected value signal. It is composed of a comparator circuit (comparison circuit) 350 for comparing and comparing the match / mismatch, and a switching circuit 360 for switching between a driver circuit 340 and a comparator circuit 350. The switching circuit 360 includes a transmission gate TG1 provided between the driver circuit 340 and the input / output node Nio, and a transmission gate TG2 provided between the input / output node Ni0 and the comparator circuit 50. One of them is opened according to the input / output control bit IZO supplied from the control unit 400, and the other is shut off.

The driver circuit 340 includes an edge-triggered flip-flop 341 that captures and holds the input / output control bit TP with the timing clock ACLKi supplied from the evening timing generator 420, and a timing clock BCLKi supplied from the timing generator 420. An OR gate 342 for taking a logical sum with CCLKi; a J / K flip-flop 343 having an output of the OR gate 342 and an output of the edge-triggered flip-flop 341 as an input signal; an output of the JZK flip-flop 343 and a control unit An input and output control bit C ONT supplied from 400 and an AND gate 344 as an input signal, and an output of the edge trigger flip-flop 341 and an input / output control bit CON T supplied from the control unit 400 are input. An AND gate 345 used as a signal and a drive for driving a test bus dedicated to the output of these AND gates 344 and 345 And a 346 Metropolitan.

On the other hand, the comparator circuit 350 is provided with an AND gate 351 using the timing clock CCLKi supplied from the timing generation section 420 and the input / output control bit CONT supplied from the control section 400 as input signals, and the D-type flip-flop. The output (expected value) of the Plobb 341 and supplied via the transmission gate TG 2 The exclusive OR gate 352 that receives the signal on the dedicated bus for the tester as an input signal, the AND gate 353 that receives the output of the exclusive OR gate 352 and the AND gate 351 as an input signal, and the output of the AND gate 353 A flip-flop 354 for latching is provided, and a signal obtained by calculating the logical sum of the output circuits of all the comparator circuits 350 is output as a total fail signal TFL. The input / output control bits I / O, TP, and CONT correspond to the control signals.

As shown in FIG. 20, the microinstruction in the test circuit of the present embodiment includes an address field MFa storing a PC address indicating a jump address of an instruction used in a jump instruction, and a sequence control code. The stored opcode field MFb, the operand field MFc for storing the number of instruction repetitions, and the like, and the timing setting bits for reading the control signal from the data register set 14 to the setting unit 420. It comprises a timing setting field MFd in which the TS is stored, and an input / output control field MFe in which the input / output control bits of the signal forming / comparing section 300 are stored. The timing setting bit TS stored in the timing setting field MFd is 2 bits in this embodiment as described above, but may be 3 bits or more. The I / O control bits stored in the I / O control field MFe correspond to the driver's bit TP, I / O bit, and control 'bit CONT corresponding to the n signal lines of the tester dedicated path 220. These three bits are one set, and only n sets are provided. Of these bits, the I / O bit is a control bit that specifies whether it is an input or an output. When this bit is "1", the transmission gate TG1 is opened and TG2 is cut off to output the driver output signal to the dedicated test path. 0 is output on the corresponding signal line, and when it is "0", the transmission gate TG 1 is shut off and TG 2 is opened to input the signal on the corresponding signal line of the test path 220 to the comparison gate 352. . Dryno, * · Bit TP and Control. Bit CONT determines whether the output is high or low, positive or negative pulse output, input invalid state, or output high impedance state according to the combination. specify. Table 9 shows the relationship between the input / output control bits TP, I / O, and CONT and the operation state of the signal forming / comparing unit 300.

[Table 9]

As shown in Table 9, when the input / output control bits TP, I / O, and CONT are “1 1 1”, the driver circuit 340 outputs a high-level signal, and when it is “0 1 1”, The driver circuit 340 outputs a low-level signal, the driver circuit 340 outputs a positive pulse signal when “1 110 j”, and the driver circuit 340 outputs a negative pulse signal when “1 110”. The control is performed so that When the input / output control bits TP, I / O, and CONT are “101”, the comparator circuit 350 expects a high-level input signal, and when it is “001”, the comparator circuit 350 is activated. Expecting a low-level input signal, control is performed so that the input signal is invalidated when "100".

In the signal forming / comparing section 300 of this embodiment, the state in which the control bits TP, 1/0, and CONT are "000" has no meaning. However, when the control bits TP, I / O, and CONT are “000”, for example, the transmission gate TG 1 is closed and TG 2 is opened, and the exclusive OR gate 352 is between the high level and the low level. As a Schmitt circuit that operates at two levels, signal formation is performed so that the state where the potential of the input / output node Nio connected to the dedicated tester path 220 exists between the two levels (high impedance state) can be compared. · Comparison section 300 can be configured. FIG. 22 shows an example of the evening clocks ACLK1 to CCLK2 supplied from the timing generator 420 and the signals output from the comparator 300 on the test evening path 220 in the above embodiment. I have. In FIG. 22, (a) shows the reference clock 00 supplied from the outside, (b) to (g) show the waveforms of the timing clocks ACLK1 to CCLK2, and (h) shows the output of Table 9. Shows the waveform of the output signal from the pin where "1" is specified as the test signal and ACLK 1 is selected as the clock. (I) shows the waveform of the output signal of the terminal for which “0j” is specified as the output test signal of Table 9 and ACLK2 is selected as the clock. (J) shows the output test signal of Table 9. Shows the waveform of the output signal at the pin where “P” is specified as the clock and BCLK 1 and CCLK 1 are selected as the clock. Further, (k) shows the waveform of the output signal of the terminal where “N” is specified as the output test signal in Table 9 and BCLK2 and CCLK2 are selected as the clock.

As can be seen from Fig. 22, the input / output control bits TP, I / O, and CONT are set to “1 1 1” and the clock ACLK 1 is specified from the terminal designated by clock ACLK 1 as shown in Fig. 22 (h). A high-level signal is output, and TP, I / O, and CONT are set to “01 1” and the clock ACLK 2 is specified from the terminal designated by the clock ACLK 2 according to the clock ACLK 2, as shown in Figure 22 (i). Is output, and TP, I / O, and CONT are set to “1 10”, and the clocks A CLK 1, B CLK 1, and CCLK 1 are output from the specified pins according to the data set by the clock ACLK 1. , CCLK1 as an edge, a positive pulse is output as shown in Figure 22 (j), and TP, I / O, and CONT are set to “010j” and the clock ACLK2, BCLK2, and CCLK2 are specified from the specified terminal. According to the data set by the clock ACLK2, a negative pulse is output as shown in Fig. 22 (k) with BCLK2 and CCLK2 as edges.

Although not shown, the input / output control bits TP, I / O, and CONT are set to “10 1” and the clock CCLK 1 is specified at the pin where the expected value is set to the high level, and the clock CCLK in FIG. Comparison is performed using 1 as the strobe signal, TP, I / O, and CONT are set to “001” and the clock CCL At the terminal where K2 is specified, the expected value is set to the low level, and the comparison is performed using the clock CCLK2 in FIG. 22 (g) as the strobe signal. The selection of the clock is not limited to the above, and may be any combination. As described above, in the above embodiment, a plurality of basic logic cells (cell logic blocks) are provided on a semiconductor chip, and a signal indicating whether the circuit is normal or abnormal can be output for each of the basic logic cells and an arbitrary logic can be output. It is equipped with a variable logic circuit such as an FPGA (Field Programmable Gate Array) that can be configured. As a result, it is possible to know that there is a defective portion in the variable logic circuit (FPGA) and its location without using an external tester. In addition, the yield is improved by constructing logic while avoiding defective parts, and when a test circuit is constructed using this variable logic circuit (FPGA) to test other internal circuits, the test circuit itself is tested. There is an effect that it is possible to avoid outputting an incorrect test result due to a failure.

In addition, the method for testing a semiconductor integrated circuit according to the present invention includes a variable logic circuit (FPGA) that can output a signal indicating whether the circuit is normal or abnormal and that can configure an arbitrary logic, and a readable and writable memory circuit. First, a self-test is performed by the above-described variable logic circuit (FPGA) in a semiconductor integrated circuit having a built-in logic circuit. A memory test circuit for inspecting a memory circuit is constructed according to the above-mentioned method, and the memory circuit is inspected. This has the effect that the memory circuit inside the LSI can be tested without using a sophisticated external tester.

Further, another test method of the semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit in which a custom logic circuit such as a CPU (Central Processing Unit) or a user logic circuit in which a logic function required by a user is configured together with a memory circuit. In such a case, a test circuit (original test) that generates test signals and expected value signals for the CPU and custom logic circuits in the above-mentioned FPGA according to a predetermined algorithm and performs tests, Is determined The test circuit or test pattern generation program was stored in the memory circuit using the memory circuit, and the test circuit built in the FPGA was started to test the CPU and the custom logic circuit. This has the effect that the CPU and the logic circuit inside the LSI can be tested without using a sophisticated external tester.

Further, in the method of manufacturing a semiconductor integrated circuit according to the present invention, first, a self-test is performed by the above-described variable logic circuit, and a defective portion is identified in the variable logic circuit by using information indicating a defective portion obtained as a result. Constructing a memory test circuit for testing the first memory circuit according to a predetermined algorithm only with the removed basic logic cells, and testing the first memory circuit;

Next, in the variable logic circuit, a logic test circuit for testing a custom logic circuit or a central processing unit according to a predetermined algorithm only with the basic logic cells excluding the defective part is constructed, and the logic test circuit is also constructed in the first memory circuit. Storing a test pattern or a test pattern generation program to inspect the custom logic circuit or central processing unit,

Thereafter, in the variable logic circuit, a memory test circuit for inspecting the second memory circuit according to a predetermined algorithm only with the basic logic cells excluding the defective part is constructed, and the second memory circuit is inspected.

Then, based on the inspection result of the second memory circuit, a bit rescue is performed by replacing a defective bit in the second memory circuit with a spare bit by using a long circuit associated with the second memory circuit. Since the processing is performed, the bit relief of the memory circuit can be performed automatically, and the yield and productivity of the semiconductor integrated circuit can be improved.

In the method of manufacturing a semiconductor integrated circuit according to the present invention, the desired logic is configured in the variable logic circuit after the bit rescue processing of the second memory circuit. Since there is no useless circuit, there is an effect that it is possible to reduce hardware overhead due to providing a test circuit inside the LSI.

Furthermore, the method for manufacturing a semiconductor integrated circuit according to the present invention is characterized in that: Since the information indicating the position of the defective bit is stored in the first memory circuit at the time of the path inspection, the information stored in the first memory circuit is read out to cause a failure. There is an effect that analysis can be easily performed. Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it is needless to say that various modifications can be made without departing from the gist of the invention. Nor. For example, in the above embodiment, the output state of the exclusive OR gate circuit LG2 which detects whether or not the circuit in the cell logic circuit CLB is normal and outputs it is stored in the memory cell SMC in the cross-point switch circuit CSW. However, it may be configured to output to the outside of the LSI chip.

Further, in the above embodiment, the fail memory for storing the position of the defective bit when testing the DRAMs 150 to 180 is configured in the SRAM 140, but the fail memory is stored in an external test memory. May be provided. Further, in the above embodiment, the TAP specified by the IEEE is used as the test interface circuit. However, the present invention is not limited to this, and a dedicated interface circuit suitable for this embodiment is used. It may be designed and provided separately. Industrial applicability

In the above description, the invention made by the present inventor has been mainly described by taking as an example a self-verification method in a system LSI provided with a CPU, an SRAM, a DRAM, and a custom logic circuit, which is a field of application which is the background. However, the present invention is not limited to this.Logic LSI with CPU and SRAM and custom logic circuit, logic LSI with CPU and DRAM and custom logic circuit, logic LSI with CPU and custom logic circuit, SRAM and DRAM and The present invention can be used for a logic LSI having a custom logic circuit, and also for a semiconductor integrated circuit having an analog circuit in addition to the above-described digital circuit.

Claims

The scope of the claims

1. A variable logic circuit consisting of a plurality of basic logic cells on a semiconductor chip, capable of outputting a signal indicating whether the circuit is normal or abnormal for each of the basic logic cells, and arbitrarily configuring logic can be mounted. A semiconductor integrated circuit characterized by the above-mentioned.

2. The variable logic circuit is a basic logic cell comprising a two-line logic circuit capable of outputting a complementary signal and a determination means for comparing the output signal of the two-line logic circuit to determine the presence or absence of an abnormality. And a plurality of variable switch circuits capable of switching connection of signal lines between these basic logic cells. Arbitrary logic can be configured by switching connections by the variable switch circuits. The signal output from the line logic circuit is supplied to the two-line logic circuit in another basic logic cell, and the output signal of the determination means is used as a signal indicating whether the circuit is normal or abnormal. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is configured to be output from the semiconductor integrated circuit.

3. The variable switch circuit includes a switch element capable of disconnecting and connecting signal lines crossing each other, and a readable and writable storage element for storing information for controlling the state of the switch element. 3. The semiconductor integrated circuit according to claim 2, wherein a signal indicating whether the circuit output from the storage device is normal or abnormal is stored in the storage element.

4. Built-in variable logic circuit consisting of at least a plurality of basic logic cells, capable of outputting a signal indicating whether the circuit is normal or abnormal for each basic logic cell, and configurable to any logic, and a readable and writable memory circuit In the inspection method of the semiconductor integrated circuit,

First, a self-test is performed by the above-described variable logic circuit, and a predetermined test signal and an expected value are obtained only in normal basic logic cells according to a predetermined algorithm in the variable logic circuit by using information indicating a defective portion obtained as a result. A value signal is generated and a test signal is supplied to the memory circuit. As a result, an output signal obtained from the memory circuit is compared with an expected value signal. Build a memory test circuit to output An inspection method for a semiconductor integrated circuit, wherein the inspection is performed.

5. The method according to claim 4, wherein the memory circuit is a static random access memory.

6. The method according to claim 4, wherein the memory circuit is a dynamic random access memory.

7. A variable logic circuit comprising at least a plurality of basic logic cells and capable of outputting a signal indicating whether the circuit is normal or abnormal for each of the basic logic cells and capable of configuring an arbitrary logic; a readable and writable memory circuit; In a method of inspecting a semiconductor integrated circuit including a logic circuit or a central processing unit,

First, a self-test is performed by the above-described variable logic circuit, and a predetermined test signal and an expected value are obtained only in normal basic logic cells according to a predetermined algorithm in the variable logic circuit by using information indicating a defective portion obtained as a result. A value signal is generated and a test signal is supplied to the memory circuit. As a result, an output signal obtained from the memory circuit is compared with an expected value signal, and when they do not match, a signal indicating a failure is formed and output to the outside of the chip. A memory test circuit is constructed, and the memory test circuit is used to inspect the memory circuit.

Next, in the variable logic circuit, a predetermined test signal and an expected value signal are generated by only a normal basic logic cell according to a predetermined algorithm, and the test signal is supplied to the custom logic circuit or the central processing unit. As a result, the output signal obtained from the custom logic circuit or the central processing unit is compared with the expected value signal, and if they do not match, a signal indicating a failure is formed and a port test circuit for outputting the signal to the outside of the chip is constructed. Inspection of a semiconductor integrated circuit characterized in that a test pattern or a test pattern generation program is stored in a circuit, and the logic test circuit is activated to inspect the custom logic circuit or the central processing unit. Method.

8. The method according to claim 7, wherein the memory circuit is a static random access memory.

9. The method for testing a semiconductor integrated circuit according to claim 7, wherein the memory circuit is a dynamic random 'access' memory.

10. No variable logic circuit consisting of at least a plurality of basic logic cells and capable of outputting a signal indicating whether the circuit is normal or abnormal for each basic logic cell and capable of configuring any logic, and no redundant circuit A method for manufacturing a semiconductor integrated circuit including a first memory circuit, a second memory circuit including a redundant circuit, and a custom logic circuit or a central processing unit.

First, a self-test is performed by the above-described variable logic circuit, and a predetermined test signal and an expected value are obtained only in normal basic logic cells according to a predetermined algorithm in the variable logic circuit by using information indicating a defective portion obtained as a result. A value signal is generated and a test signal is supplied to the first memory circuit. As a result, an output signal obtained from the first memory circuit is compared with an expected value signal to form a signal indicating a failure if they do not match. To construct a memory test circuit for outputting to the outside of the chip, inspecting the first memory circuit by the memory test circuit,

Next, in the variable logic circuit, a predetermined test signal and an expected value signal are generated according to a predetermined algorithm only in the normal basic logic cell, and the test signal is supplied to the custom logic circuit or the central processing unit. Result The output signal obtained from the custom logic circuit or the central processing unit is compared with the expected value signal, and if they do not match, a signal indicating a failure is formed and output to the outside of the chip. A test pattern or a test pattern generation program is stored in the memory circuit of Step 1, and the logic test circuit is activated to inspect the custom logic circuit or the central processing unit.

Thereafter, a predetermined test signal and an expected value signal are generated according to a predetermined algorithm only in the normal basic logic cells in the variable logic circuit, and the test signal is supplied to the second memory circuit. By comparing the output signal obtained from the memory circuit and the expected value signal, if they do not match, a signal indicating a failure is formed and a memory test circuit for outputting the signal to the outside of the chip is constructed. Inspect,

After that, based on the inspection result of the second memory circuit, a defective bit in the second memory circuit is set as a spare using a redundant circuit associated with the second memory circuit. A method for manufacturing a semiconductor integrated circuit, wherein a bit rescue process for replacing a bit is performed.

11. The device according to claim 10, wherein the first memory circuit is a static random access memory, and the second memory circuit is a dynamic random 'access' memory. The manufacturing method of the semiconductor integrated circuit described in the above.

12. The manufacturing method of the semiconductor integrated circuit according to claim 10, wherein a desired logic is configured in the variable logic circuit after the bit rescue processing of the second memory circuit. Method.

13. The information indicating the position of a defective bit at the time of inspection of the second memory circuit is stored in the first memory circuit. 3. The method for manufacturing a semiconductor integrated circuit according to 2.