WO1999030176A1

WO1999030176A1 - Semiconductor integrated circuit and method for diagnosing logic circuit

Info

Publication number: WO1999030176A1
Application number: PCT/JP1998/005564
Authority: WO
Inventors: Masayuki Satoh; Isao Shimizu; Hiroshi Fukiage; Hideaki Takahashi
Original assignee: Hitachi, Ltd.
Priority date: 1997-12-09
Filing date: 1998-12-09
Publication date: 1999-06-17

Abstract

A test circuit is mounted on a logic LSI chip. The test circuit generates a prescribed test signal and an expected value signal in accordance with an instruction described in a test language. Supplies the test signal to an internal logic circuit through a bus, compares the output signal of the logic circuit with the expected value signal. When the output signal does not coincide with the expected value, the test circuit generates and outputs a signal representing defect to the outside of the chip.

Description

Description: Diagnostic method for semiconductor integrated circuits and logic circuits

The present invention relates to a diagnostic technique for a semiconductor integrated circuit (IC-n integrated circuit), and also to a technique effective when applied to fault detection of a logic IC, for example, to provide a logic LSI (Large Scale Integration) with a test function. Background art

As a diagnostic method of a logic IC, a method of generating test pattern data by a test device called a tester, inputting the test pattern data to the IC, and comparing the output data signal with an expected value to compare the data is generally used. . However, in logic IC, the number of test pattern steps increases as the scale of the logic increases, and the time required for creating a test pattern and using the test pattern becomes extremely long.

Therefore, as a method for facilitating diagnosis by a tester, as shown in Fig. 11, cascading of sequential circuits FF1, FF2, and FFn, such as flip-flops, that constitutes the original function of the IC The shift register is designed so as to be configurable, and at the time of diagnosis, a test pattern is serially input (scanned in) to the shift register and fetched (set), and a desired combinational logic circuit CL 1, CL 2 The so-called scan path method is used in which the test data input to the logic circuit (CL1, CL2) is input to the shift register, and the output data signal is shifted to the outside (scanout). Test facilitation design technology has been developed and put into practical use. If a logic circuit contains a sequential circuit, the output will differ depending on the internal state.Therefore, in order to test a certain logic circuit, the state of the sequential circuit contained in it must first be set using a test pattern. Although the pattern becomes very long, the test can be performed by inputting (scanning in) a test pattern using a flip-flop as a shift register. Patterns can be greatly reduced.

The present inventors have found the following problems prior to the present invention. That is, in the scan path method described above, although the amount of test patterns is smaller than the conventional diagnostic methods, it is difficult to generate test patterns, it is difficult to increase the defect detection rate, and the test patterns are input serially. (Transfer) is repeated, so that the test time becomes longer. In addition, the newly developed logic LSI uses memory circuits such as RAM (random access memory) and ROM (read only memory) and large cells (macrocells or IP cores: Intellectual Property Core) such as CPUs. In the case of preparing, there is a problem that it is practically impossible to make a diagnosis because an enormous amount of test patterns need to be created and input if a diagnosis is to be made for such senor.

In addition, an address counter, ROM storing test data, expected value data, test instructions, etc., and a comparison circuit are provided on the LSI chip. Test data is input to the internal logic circuit to be diagnosed, and the output is compared with the expected value. Japanese Patent Application Laid-Open No. Hei 6-242187 discloses a technique that can perform a self-diagnosis by performing the self-diagnosis.

However, in such a self-diagnosis method, the test instruction is not disclosed, and the test pattern cannot be changed by the user, so the defect detection rate is low, and it occurs after the system is implemented in the system. There is a problem that it is difficult to detect a defect.

In a general diagnostic method in which test pattern data is input to an LSI using a tester, the LSI that constitutes the tester is manufactured using a technology one or several generations earlier than the LSI to be tested. The next-generation LSI will be inspected using a tester composed of such an old-generation LSI. As a result, the specifications required for testers that test LSIs are extremely strict, and in order to achieve the desired speed, multiple identical circuits are prepared and parallel processing is performed. There was a problem that it had to be large.

An object of the present invention is to provide a diagnostic technique capable of diagnosing a circuit inside a logic LSI without using an external tester. Another object of the present invention is to provide a technology capable of executing a diagnosis of a logic LSI in a short time.

Another object of the present invention is to provide a diagnostic technique capable of performing a logical LSI diagnosis even after being mounted on a system.

It is another object of the present invention to provide a test circuit architecture (basic configuration) that can be mounted on a logic LSI.

It is still another object of the present invention to provide a diagnostic technique capable of executing a newly designed logical LSI diagnosis on a workstation-level computer.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

The outline of a typical invention disclosed in the present application is as follows.

That is, a predetermined test signal and an expected value signal are generated on a logic LSI chip according to a predetermined algorithm, and the test signal is supplied to a logic circuit inside the logic LSI chip via a bus. A test circuit that compares the output signal (output data) obtained from the circuit with the expected value signal (expected value data) and forms a signal indicating a failure when they do not match, and outputs the signal to the outside of the chip has been installed. It was done.

The internal logic circuit to be inspected by the above test circuit is divided into a plurality of blocks or macrocells (IP cores), and a test signal and its output signal are applied between each block (macrocell or IP core) and the test circuit. A bus for signal transmission and a signal switching circuit are provided, and a test signal is supplied to the internal logic circuit in a non-scan manner. The block (macrocell or IP core) divided by the bus may not be a sequential circuit and a combinational logic circuit as in the scan method, but may be a circuit block in which a part of the combinational logic circuit is incorporated in the sequential circuit. The above IP core is a hardware description language that is independent of the process and circuit system. Generally refers to cores that can be used and reused as intellectual property (design assets) by constructing a macro (macro cell). Furthermore, in other words, a hardware (software) function (block) that is necessary to configure a logic circuit or a memory circuit is called an IP core, and is referred to as an IP core. Includes the implications of a functional block and the drivers-software, firmware, etc. that operate the functional block. The test circuit proposed as an invention in the present application can also be made into an IP core.

In addition, the test circuit includes a micro-instruction-type control unit that forms a control signal for generating a test signal and an expected value signal of the internal logic circuit according to a predetermined algorithm, and a control output from the control unit. A signal that generates a test signal and an expected value signal of the internal logic circuit based on the signal, and forms a signal indicating a failure if the signal output from the internal logic circuit and the expected value signal do not match with each other. Forming and comparing unit (signal forming circuit and comparing circuit). A timing generation circuit for forming a plurality of clock signals having different phases and duties from each other based on a reference clock signal is provided so that timing can be set for each test signal in accordance with a control signal from the control unit. .

Further, the control unit of the test circuit is configured such that one instruction corresponds to one test signal, so that the instruction code forming the test signal can be compressed. In addition, the test circuit is provided with a power supply voltage level detection circuit so that diagnosis is started automatically each time the power supply voltage rises. The instruction code is described using an existing tester language or test language. A test pattern (address and data) is generated according to the predetermined algorithm defined by the instruction code. The tester language is regarded as an effective instruction language for efficiently generating a test pattern including an address and data. The tester language is a language generally used in the tester industry. For example, it is preferable that the tester language be a language that is compatible with the tester language of Advantest. This is because the program data of the existing test pattern can be used. The language for describing the above predetermined algorithm is not limited to the tester language, but any instruction language capable of generating a test pattern including an address and data. Good.

Further, it is desirable that the test circuit has a self-test function for performing a logic test of itself.

According to the above-described means, it is possible to diagnose the internal logic circuit of the IC chip without using an external (outside the IC chip) tester, and it is not necessary to provide an external terminal (pin) for inputting a test pattern. . In addition, since the test circuit formed on the same semiconductor chip as the internal logic circuit is formed by the same manufacturing technology as that of the internal logic circuit, that is, the same generation circuit, the same test circuit as the internal logic circuit to be tested is used. Since the operating speed can be easily realized, the diagnosis of the circuit can be performed in a short time, and the parallel processing by multiple identical circuits is not required.Therefore, the scale of the test circuit can be made smaller than that of a conventional external tester. On-chip implementation is relatively easy.

Further, the test circuit includes a microprogram control type control unit that forms a control signal for generating a test signal and an expected value signal of the internal logic circuit in accordance with a predetermined algorithm, and a control signal output from the control unit. A signal generation circuit that generates a test signal and an expected value signal for the internal logic circuit based on the control signal and compares the signal output from the internal logic circuit with the expected value signal to form a signal indicating a failure if they do not match. Since it is composed of a comparison unit, it is not necessary to store all test patterns in the internal memory.In addition, the configuration of the control unit makes it possible to compress the instruction code itself and increase the area occupied by the test circuit. And on-chip operation becomes easy.

In addition, a test circuit is mounted on the logic LSI chip, a power supply voltage level detection circuit is provided in the test circuit, and diagnosis is automatically started each time the power supply voltage rises, so that the system can be configured. Logic LSIs can be diagnosed dynamically even after mounting, improving the reliability of the system and making it easier to find and repair faulty locations.

Furthermore, since the test circuit can be described in a computer-understandable language (HDL: Hardware Description Language), a virtual tester can be constructed by expressing the test circuit on a workstation. development of The logic LSI design data can be described in HDL and input to a workstation, enabling diagnosis by logic simulation. In addition, a hardware emulator can be configured using an FPGA (Field Programmable Gate Array) to perform pre-verification, thereby shortening the LSI development period. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram showing the overall configuration of one embodiment of a logical LSI to which the present invention is applied.

FIG. 2 is a circuit configuration diagram showing an embodiment of a signal switching circuit provided between divided circuit blocks.

FIG. 3 is a block diagram showing a first embodiment of the test circuit according to the present invention. FIG. 4 is a logical circuit diagram showing a specific example of the signal forming / comparing unit in the test circuit of the first embodiment.

FIG. 5 is a waveform diagram showing an example of a test signal waveform formed by the test circuit of the embodiment.

FIG. 6 is a block diagram showing a second embodiment of the test circuit according to the present invention. FIG. 7 is a logic circuit diagram showing a specific example of the signal forming / comparing circuit in the test circuit of the second embodiment.

FIG. 8 is a block diagram showing an example of a system to which a logic LSI incorporating a test circuit according to the present invention is applied.

FIG. 9 is a block diagram showing a configuration example of the LSI in the case of constructing a new logical LSI using the logic LSI equipped with the test circuit according to the present invention.

FIG. 10 is a flowchart showing an outline of a procedure for developing a logic LSI according to the present invention.

FIG. 11 is a block diagram showing an overall configuration of an example of a logical LSI to which a conventional test method is applied.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of a logic LSI to which the present invention is applied, and is configured on one semiconductor chip 100 such as a single-crystal silicon. In FIG. 1, reference numeral 110 denotes an input terminal (input pad) group for the original input signal of the semiconductor chip 100, and reference numeral 120 denotes an output terminal (output) for the original output signal of the semiconductor chip 100. Pad) group, 130 A, 130 B, 130 C, 140 A, 140 B are the original functions of the logic LSI (logical operation function, address data input / output function, data A circuit block (IP core) that realizes the storage function [memory function]) and 150 is a test circuit for inspecting these circuit blocks. In this embodiment, the circuit blocks 13A, 13OB, 13OC, 14OA, 14OB and between the input terminal group 110 and the circuit block 13OA as well as Signal switching circuit 16 0 A, 16 0 B, 16 0 C, 16 0 D, 16 0 E, 16 0 between circuit block 13 0 C and output terminals 12 0 F is provided.

As shown in FIG. 2, each of the signal switching circuits 160A to 160F is composed of a tester dedicated bus 170 and switching switches SW1 to SWn, respectively. One end of the tester dedicated bus 170 is connected to the test circuit 150, and a signal for controlling the switching switches SW1 to SWn is configured to be supplied from the test circuit 150. As will be described in detail later, the test circuit 150 mainly includes a controller 10, a timing generator 20, and a signal generator / comparator 30.

In the LSI internal logic circuit diagnostic method of the present embodiment, a test signal is input to a desired circuit block (IP core) via a tester dedicated bus 170, and the output is thereby output from the circuit block (IP core). In this method, a signal to be output is input to a test circuit 150 via a tester dedicated bus 170 and compared with an expected value. Therefore, the circuit blocks 130 A, 130 B, 130 C, 140 A, and 140 B in the present embodiment correspond to the conventional method (scan path method) shown in FIG. Unlike combinational logic circuits CL 1 and CL 2 in logic LSIs, only combinational logic circuits may be used, or sequential logic circuits and combinational logic circuits, or large-scale units such as ALUs (arithmetic logic units) and decoders It may be a cell (macro cell, IP core). Therefore, according to the present embodiment, it is also possible to achieve a fault detection rate of 100% by arbitrarily dividing the circuit block.

Although not particularly limited, in this embodiment, as shown in FIG. 2, a power supply voltage level detecting circuit 70 and a switching control signal forming circuit 80 are provided in a test circuit 150, and when the power is turned on, When the voltage Vcc rises, it is detected and a signal switching circuit A switching control signal CS for 160A to 160F is formed, and when the inspection of one circuit block (IP core) is completed, the control unit is controlled. A switching control signal CS supplied to a signal switching circuit connected to the next circuit block is formed based on an end signal END supplied from 10 and is output.

The logic LSI of this embodiment shown in FIGS. 1 and 2 has a clock input terminal 111 for inputting a reference clock signal 00 supplied to the test circuit 150, and a failure as a result of diagnosis. (Hereinafter referred to as a total fail signal). An output terminal 121 for outputting a TFL is provided. Instead of the clock input terminal 111, an oscillation circuit may be provided in the test circuit 150, and a terminal for connecting an oscillator for determining the oscillation frequency of the oscillation circuit may be provided.

In the test circuit 150 of this embodiment, a test pattern (a collection of test signals corresponding to a tester dedicated bus) and an expected value for an internal logic circuit (circuit block, macrocell, IP core) are generated according to a predetermined algorithm. 10 based on a microprogram control method for forming a control signal for generating a control signal CT and a control clock CT output from the control unit 10 and a reference clock signal ø0 supplied from the outside. A timing generator 20 for forming a plurality of different timing blocks, and a control signal CC output from the controller 10 and a timing clock TC output from the timing generator 20 are used for internal control. It generates the test signal and expected value signal of the internal logic circuit, outputs the test signal to the tester dedicated bus 170, and outputs the internal logic circuit. The signal output on the dedicated tester bus 170 from the tester and the expected value signal are compared, and if they do not match, a signal indicating a defect is formed and output to the output terminal 1 2 1 0 is provided. FIG. 3 shows an embodiment of the control unit 10 of the test circuit 150. The control unit 10 of this embodiment includes an EEPROM (Read Only Memory) that stores a microprogram consisting of a plurality of microinstructions described according to a predetermined test pattern generation algorithm. Memory), a random instruction memory (RAM), a program counter 12 that specifies a microinstruction to be read from the instruction memory 11, and a microinstruction read from the instruction memory 11 The instruction decoding control circuit 13 that decodes the instruction code inside and forms a control signal for the circuits in the control unit 10 such as the program counter 12 above. The timing setting bit MF d (TS bit) in the micro instruction A data register set 14 that outputs control data to the timing generator 20 based on the It decodes the door MF d (TS-bit) reads the control data from the data register set 1 4 and a like decoder 1 5.

Also, among the internal logic circuits to be diagnosed, circuits whose functions are specified (for example, ALU: Arithmetic Logic Unit) often have an appropriate test pattern formation method already established. By using the test pattern assets, efficient test pattern generation is possible. For combinatorial logic circuits, a fault assumption method and an efficient test pattern generation method called the D-algorithm based on the idea of a single fault where one circuit has one fault are known. I have. By using this method, the microprogram for generating a test pattern can be shortened, and the capacity of the instruction memory 11 can be suppressed to a practicable level.

In this embodiment, although not particularly limited, the timing setting bit TS decoded by the decoder 15 is composed of two bits, and the data register set 14 stores seven control data. One of these control data is a test cycle data "RAT E", and the remaining six control data are output signals of high or low level for each signal line of the tester dedicated bus. Two types of control data "AC LK 1" and "AC LK 2" that give the timing and two types of control data "BC LK 1" and "BC LK 1" that give the rising timing of the pulse signal Two types of control data "CCLK1" and "CCLK2" that provide "BCLK2" and the output timing for comparison with the falling timing and expected value of the pulse signal.

When each of these control data is supplied to the timing generation section 20, the control data RATE is supplied to the program counter 12 with a signal RATE having a predetermined timing, and the microphone R from the instruction memory 11 is supplied. An instruction code is taken. When "AC LK 1" to "CC LK 2" are supplied to the timing generator 20 as control data, a clock corresponding to the control code from the timing clocks AC LK 1 to CC LK 2 forms a signal. Output to comparator 30. Connection and selection for use of each clock are appropriately performed as needed.

Further, the control unit 10 includes an incrementer 21 for incrementing the value of the program counter 12 to “11”, and a destination address in the incrementer 21 or the address field MFa. , A multiplexer 2 that supplies the number to the program counter 12, an index register 23 that holds the number of repetitions in the operand field MFc, and a decrementer 2 that decrements the value of the index register 23. 4.Working register 25 holding the value decremented to `` 1 1 '', flag 26 indicating the presence / absence of data inversion used in the specified instruction, and program counter 12 of the operand used in the specified instruction. Multiplexer that selectively supplies the flag 27 indicating the presence / absence of data transfer and the values of the registers 23 and 25 to the decrementer 24 A demultiplexer 29 for distributing the value of the decrementer 28 and the decrementer 24 to one of the planes of the working register 25 is provided.

In this embodiment, an operand field MFc for storing the number of instruction repetitions is provided in the microphone opening instruction code, and an index register 23 for holding the number of repetitions is provided in the control unit 10. Therefore, when the same test signal is repeatedly generated, the number of necessary microphone opening instructions can be reduced and the microprogram can be shortened. In this embodiment, the index register 23, the working register 25, and the flag 27 are provided in a plurality of planes (four in the figure). As a result, it is possible to easily execute a sub-loop process in a certain loop process and a sub-loop process in the sub-loop process, and to shorten a microprogram.

Note that the control unit 10 of this embodiment is designed in common with a test circuit control unit that performs memory testing, and includes functions that are not necessarily required for logic circuit testing. . For example, a flag 26 indicating whether data is inverted is equivalent to this.

Note that the above EPROM, ROM, and RAM should have a structure that relaxes the semiconductor design standards, so that consideration is given to preventing defects. That is, a semiconductor manufacturing process that can reduce the defect occurrence rate is applied.

FIG. 4 shows an embodiment of the signal forming / comparing unit 30. In the circuit of FIG. 4, only the driver / comparator circuit corresponding to one of the signal lines constituting the tester dedicated bus 170 is representatively shown. The circuits shown in FIG. 4 are provided as many as the number of signal lines constituting 170.

As shown in FIG. 4, the driver Z comparator circuit of this embodiment includes a driver circuit (signal forming circuit) 40 for forming a signal to be output to a dedicated tester path, a signal on a dedicated tester bus, and an expected value signal. And a switching circuit 60 that switches between a driver circuit 40 and a comparator circuit 50. The switching circuit 60 includes a transmission gate TG1 provided between the driver circuit 40 and the input / output node Nio, a transmission gate TG2 provided between the input / output node Nio and the comparator circuit 50. One is opened according to the input / output control bit IZO supplied from the control unit 10, and the other is turned off.

The driver circuit 40 includes an edge-triggered flip-flop 41 that captures and holds the input / output control bit TP supplied from the control unit 10 by the timing clock ACLKi supplied from the timing generation unit 20. An OR gate 42 for ORing the timing clocks BC LK i and CC LK i supplied from the timing generator 20, and an output of the OR gate 42 and an output of the edge-triggered flip-flop 41. J / K flip-flops 43 as input signals, An AND gate 44 using the output of the JZK flip-flop 43 and the input / output control bit C Ο 供給 supplied from the control unit 10 as an input signal, and an output of the edge trigger type flip-flop 41 Consists of an AND gate 45 that uses the input / output control bit CNT supplied from the control unit 10 as an input signal, and a driver 46 that drives a dedicated tester bus by the output of these AND gates 44 and 45 It has been.

On the other hand, the comparator circuit 50 includes an AND gate 51 that uses the timing clock CCLKi supplied from the timing generation section 20 and the input / output control bit CNT supplied from the control section 10 as input signals. An exclusive OR gate 52 that receives the output (expected value) of the D-type flip-flop 41 and a signal on the tester dedicated bus supplied via the transmission gate TG 2 as input signals; An AND gate 53 having the output of the AND gate 51 as an input signal and a flip-flop 54 for latching the output of the AND gate 53 are provided. The signal obtained by ORing the output circuits is output as the total fail signal TFL. The input / output control bits I0, TP, and CONT correspond to the control signal CC. As shown in FIG. 3, the microinstruction in the test circuit of the present embodiment includes an address field MFa storing a PC address indicating a jump address of an instruction used in a jump instruction, and a sequence control code. Field MFb that stores the number of instruction repetitions, etc., and a timing setting bit for reading the control signal for the timing generator 20 from the data register set 14 It comprises a timing setting field MF d in which TS is stored, and an input / output control field MF e in which input / output control bits of the signal forming / comparing section 30 are stored.

The timing setting bits TS stored in the timing setting field MFd are two bits in this embodiment as described above, but three or more bits may be provided. The input / output control bits stored in the input / output control field MF e correspond to the dry bit TP and the 1/0 bit corresponding to the n signal lines of the tester dedicated bus 170. Mouth bitCont 3 bits are one set, Only n sets are provided. Of these bits, the IZO bit is a control bit that specifies input or output. When "1", the transmission gate TG1 is opened and ΤG2 is shut off to output the driver output signal to the tester dedicated bus 170 When the signal is "0", the transmission gate TG 1 is shut off and TG 2 is opened, and the signal on the corresponding signal line of the tester dedicated bus 170 is sent to the gate 52 for comparison. Input. Dryno bit TP and control bit CONT specify high or low output, positive or negative pulse output, input invalid state, or output high impedance state according to the combination. I do.

Table 1 shows the relationship between the input / output control bits TP, I / Q, and CONT and the operation state of the signal forming / comparing unit 30.

As shown in Table 1, when the I / O control bits TP, I / O, and CONT are “1 1 1”, the driver circuit 40 outputs a high-level signal and the “0 1 1” In this case, the driver circuit 40 outputs a low-level signal, when “1 10”, the driver circuit 40 outputs a positive pulse signal, and when “1 10”, the driver circuit 40 outputs a negative pulse signal. Control is performed so as to output a pulse signal. When the input / output control bits TP, I / O, and CNT are “101”, the comparator circuit 50 expects a high-level input signal. Expect an input signal, and if "100", disable the input signal Control is performed.

In the signal forming / comparing unit 30 of this embodiment, the state in which the control bits TP, IO, and CONT are "0 0 0" has no meaning. However, when the control bits TP, I / O, and CONT are “0 0 0”, for example, the transmission gate TG 1 is closed and TG 2 is opened, and the exclusive OR gate 52 is connected to the high-level control. As a Schmitt circuit that operates with two levels between the loops, the state where the potential of the input / output node Nio connected to the tester dedicated bus 170 exists between the two levels (high impedance state) It is also possible to configure the signal forming / comparing unit 30 so that the signals can be compared.

FIG. 5 shows the timing clocks AC LK1 to CC LK2 supplied from the timing generator 20 in the above embodiment and signal formation.The signals output from the comparator 30 to the tester dedicated bus 170. An example is shown. In FIG. 5, (a) shows the reference clock Φ0 supplied from the outside, (b) to (g) show the waveforms of the timing clocks AC LK1 to CCLK2, and (h) shows the output test of Table 1. Shows the waveform of the output signal from the pin where "1" is specified as the signal and ACLK 1 is selected as the clock. (I) shows the waveform of the output signal of the terminal in which “0” is specified as the output test signal in Table 1 and the ACLK2 is selected as the clock. (J) shows the waveform of the output signal of the terminal in which “P” is specified as the output test signal in Table 1 and BCLKI and CCLK1 are selected as the clock. Further, (k) shows the waveform of the output signal of the terminal in which "N" is designated as the output test signal in Table 1 and BCLK2 and CCLK2 are selected as the clock.

As can be seen from Fig. 5, the input / output control bits TP, I / O, and CONT are set to "1 1 1" and the clock AC LK 1 is specified. A high-level signal is output, and TP, I / O, and C 設定 are set to “0 1 1” and the clock AC LK 2 is specified. A low-level signal is output, TP, I / O, and CONT are set to “1 1 0” and clocks AC LKl, BC LK1, and CCLK 1 are set at the specified terminal by clock AC LK 1. According to the data, the positive path shown in Fig. 5 (j) with BC LKl and CC LK1 as edges Pulse is output, TP, I / O, and CONT are set to “0 1 0”, and the clock ACLK 2, BCLK 2, and CCLK 2 are designated by the clock ACLK 2 from the specified terminal. , CCLK 2 is output as a negative pulse as shown in FIG. 5 (k). Although not shown, the input / output control bits Τ Ρ, Ι / Ο, ΟΟΝΤ are set to “101” and the clock CCL Κ1 is set to the expected value, and the expected value is set to the high level. The comparison is performed using the clock CC LK1 as the strobe signal, and TP, I / O, and CONT are set to "01" and the expected value is set to the low level at the pin where the clock CC LK 2 is specified. The comparison is performed using the clock CCLK2 of this as a strobe signal. Note that the selection of the clock is not limited to the above, and may be any combination. Next, a second embodiment of the test circuit according to the present invention will be described with reference to FIGS. FIG. 6 shows the configuration of the control circuit 210 used in the second embodiment, and FIG. 7 shows the configuration of the signal formation / comparison circuit 230 used in the second embodiment.

In the first embodiment, a common control unit 10 and a timing control unit 20 for controlling generation of output signals or expected value signals for all signal lines of the tester dedicated bus 170 are provided, and one microphone port is provided. In contrast to a case where a plurality of signals are formed by instructions, the second embodiment provides a control circuit 210 and a timing control circuit 220 for each signal line of the tester dedicated bus 170. With this arrangement, the bit length of the microphone instruction is shorter than that of the first embodiment, and the microprogram can be compressed.

The difference between the configuration of the control circuit 210 in the present embodiment shown in FIG. 6 and the control unit 10 of the first embodiment shown in FIG. The point that the control data for the timing generation circuit 220 is directly stored in the timing setting field MFd of the opening instruction, and the data register set 14 for storing the control data are omitted accordingly The timing generator circuit 220 has a configuration corresponding to the configuration of the control data in the timing setting field MFd, and the I / O control field MFe contains one signal of the tester dedicated bus 170 The point that only three control bits related to the line are stored, and the driver circuit 40 (shown in Fig. 7) of the signal formation / comparison circuit 230 is the timing generation circuit 220 There is a point that the configuration is in accordance with the timing clock output from the. The above difference will be described in more detail. The control data for the timing generation circuit 220 stored in the timing setting field MFd of the microinstruction in this embodiment is the test cycle, that is, the frequency or frequency of the test signal. It consists of a cycle control code CYCLE that specifies the cycle, a control code RISE that specifies the rising timing of the clock signal, and a control code FALL that specifies the falling timing of the clock signal.

On the other hand, the timing generation circuit 220 is composed of three down counters operating with the reference clock 00, and has three clock signals CTG, R having the timing specified by the three control codes in the timing setting field MFd. Outputs TG and F TG. Of these clock signals, CTG is supplied to a program counter 12 to provide read timing of a microinstruction, and clock signals RTG and FTG are supplied to a signal forming / comparing circuit 230, and a rising edge corresponding to the RTG is provided. It is used to form a signal having a falling edge corresponding to the FTG and to provide comparison timing.

The difference between the signal forming / comparing circuit 230 of the second embodiment shown in FIG. 7 and the signal forming / comparing circuit 30 of the first embodiment shown in FIG. In this embodiment, the point that the flip-flop 41 that performs a latch operation with the clock ACLK in the circuit of the first embodiment is omitted, and the clock that is input to the OR gate 42 in the circuit of FIG. In this embodiment, only the clocks RTG and FTG output from the timing generation circuit 220 in FIG. 6 are input instead of the BC LK and CC LK. Signal formation · The relationship between the input / output control bit sets TP, I / O, and CONT input to the comparison circuit 230 and the operation state of the comparison circuit 230 is the same as that of the first embodiment. Signal formation · Same as Table 1 shown for the comparison circuit 30.

In the second embodiment, the control circuit 210, the timing generation circuit 220, and the signal generation / comparison circuit 230 are configured as described above. Although the microphone opening instruction needs to be stored in the instruction memory of the control circuit 210 for each line, each microphone opening instruction is completely different from the first embodiment. Since the bit length of the field becomes shorter and the number of repetitions and loops can be set freely for each signal, the advantage is that it is possible to compress the microprogram, that is, to reduce the number of macro instructions. is there.

FIG. 8 shows an example of a system to which the logic LSI equipped with the test circuit according to the present invention is applied. In the figure, 300 is a printed circuit board, 310 is a clock generation circuit for generating a reference clock φ 0, 100 A, 100 B, and 100 C are test circuits 150 0 of the above embodiment, respectively. It is a logic LSI equipped with. In the system of the embodiment shown in FIG. 8, the light-emitting diodes D1 and D2 are respectively connected to the output terminals 121 of the total fail signal TFL provided in the logic LSIs 100A, 100B, and 100C. , D2 and D3 are connected, and the LED is turned on when a defect is detected. This makes it possible to easily find out which LSI has a defect when a failure occurs in one of the LSIs after being mounted on the system and the system breaks down.

As described above, in the above embodiment, a predetermined test signal and an expected value signal are generated on a logic LSI chip according to a predetermined algorithm, and the test signal is supplied to an internal logic circuit via a bus. Since an output signal from the internal logic circuit is compared with an expected value signal and a signal indicating a failure is formed when the values do not match, a test circuit that outputs the signal to the outside of the chip is mounted. Test can be performed on the same semiconductor chip as the internal logic circuit without using the same manufacturing technology, that is, the same generation circuit. Since the same operation speed as the target internal logic circuit can be easily achieved, the test of the internal logic circuit can be executed in a short time in actual operation, and multiple Since it reduced compared with the case according to the scale of a conventional tester test circuit since the parallel processing by the circuit becomes unnecessary, there is an effect that on-chip operation can be relatively easily realized.

Further, the test circuit includes a microprogram control type control unit that forms a control signal for generating a test signal and an expected value signal of the internal logic circuit according to a predetermined algorithm, and a control unit output from the control unit. The test signal and expected value signal of the internal logic circuit are generated based on the signals, and output from the internal logic circuit. And the expected value signal, the signal is formed by a signal forming / comparing unit that forms a signal indicating a failure when the signal does not match.The instruction code itself can be compressed by the configuration of the control unit. This has the effect of suppressing an increase in the area occupied by the test circuit and facilitating on-chip implementation.

Furthermore, a test circuit is mounted on the logic LSI chip, a power supply voltage level detection circuit is provided in the test circuit, and diagnosis is started automatically each time the power supply voltage rises. This makes it possible to diagnose the logic LSI dynamically later, improving the reliability of the system and making it easier to find and repair faulty locations.

The logic LSI 100A to which the test circuit of the above embodiment is applied is shown in FIG. 9 when it is incorporated as a single macro cell or IP core in the development of another larger logic LSI. As shown in the figure, the logic circuit section 100 and the test circuit 150 are included as they are, mounted on a new LSI chip 400, and newly added to the logic circuit sections 4100 and 420. By constructing a test circuit 430 suitable for it and mounting it on a chip, the already verified logic circuit section 100 and test circuit 150 can be used as is with the conventional design assets. It is sufficient to design only the test circuit 430 for the new logic circuit sections 410 and 420 by utilizing the above, so that the overall test facilitation design becomes possible.

Furthermore, since the test circuit can be described in a language that can be understood by a computer (such as HDL), a virtual tester can be constructed by expressing the test circuit on a workstation. Therefore, when developing a logic LSI, as shown in Fig. 10, a logic LSI designed according to the initially determined LSI specifications is described in HDL, input to a workstation, and synthesized with the tester described in HDL above. By doing so, it is possible to make a diagnosis by logic simulation, and if a failure is detected during the logic verification, the LSI development period can be shortened by changing the LSI specifications. It is also possible to configure a hardware emulator using FPGA and perform pre-verification.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and the present invention is not limited thereto. It goes without saying that various changes can be made. For example, in the embodiment, the power supply voltage level detection circuit is provided in the test circuit, and the test circuit is automatically activated when the power supply voltage rises. A mode terminal for inputting a signal may be provided, and the internal logic circuit may be tested only when the operation of the test circuit is instructed from the mode terminal. In the above description, the invention made by the present inventor has been mainly described by taking as an example a test circuit in a logic LSI, which is a use field as a background, but this invention is not limited to this, and a digital circuit and an analog circuit are mixed. It can also be used for semiconductor integrated circuits. Industrial applicability

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

In other words, it is possible to diagnose internal logic circuits without using an external tester, apply a non-scan-type test simplification design, greatly improve the failure detection rate, and improve the test pattern steps. The smaller the number, the faster the memory diagnosis can be completed.

Claims

The scope of the claims

— 1. A logic circuit generates a test input signal and an expected value signal for testing the logic circuit according to a predetermined algorithm, and compares the logic circuit with a signal output from the logic circuit. A semiconductor integrated circuit, wherein a test circuit for outputting the signal to an external terminal is formed on the same semiconductor chip.

2. The above logic circuit is divided into any number of circuit blocks, and between each circuit block is a tester that transmits a test input signal to each circuit block and a signal output from the circuit block in response to the test input signal. 2. The semiconductor integrated circuit according to claim 1, further comprising: a bus; and signal switching means for switching between a bus dedicated to the tester and a signal path between the circuit blocks.

3. The test circuit generates a control signal that forms a control signal in accordance with the micro-instruction code, and generates a cook signal at a specified timing based on the control signal from the control section and a reference cook signal. The test input signal and the expected value signal based on the control signal from the control unit and the timing clock signal from the timing generation unit, and from the logic circuit or the circuit block. 3. The semiconductor integrated circuit according to claim 1, further comprising: a signal forming / comparing unit that performs a comparison with an output signal and forms a defective signal when they do not match.

4. The test circuit includes a control circuit that forms a control signal in accordance with the microphone instruction code in accordance with the signal line of the tester dedicated path, a control signal from the control circuit, and a reference clock signal. A timing generation circuit for generating a clock signal having a designated timing based on the above-mentioned test input signal and the expected signal based on the control signal from the control unit and the timing clock signal from the timing generation unit. 2. A signal generating / comparing circuit for generating a value signal and comparing with a signal output from the logic circuit or the circuit block to form a defective signal when they do not match, and Or the semiconductor integrated circuit according to 2.

5. Equipped with a power supply voltage level detection circuit, when the power supply voltage exceeds a predetermined level 5. The semiconductor integrated circuit according to claim 1, wherein the test circuit is activated when the logic circuit or the circuit block is inspected.

6. The semiconductor integrated circuit according to any one of claims 1, 2, 3, 4 and 5, further comprising an external terminal for the reference cook signal.

7. The semiconductor integrated circuit according to claim 1, 2, 3, 4, 5, or 6, wherein the test circuit has a self-test function of performing a logic test of itself. circuit.

8. A signal forming circuit for generating a test pattern of a logic circuit according to a predetermined algorithm and logic design data of the logic circuit are described in a test language, and the logic circuit is described by the test pattern formed by the signal forming circuit. A method for diagnosing a logic circuit, characterized by performing a logic simulation on a computer.

9. A signal forming circuit for generating a test pattern of a logic circuit in a hardware description language according to an algorithm of a tester language and a logic design data of the logic circuit are described in the test language, and a test pattern generated by the signal generation circuit is described. A method for diagnosing a logic circuit, characterized in that the logic circuit is inspected on a computer by logic simulation according to turns.