JPH0587890A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To shorten the designing time and permit the high speed test by permitting the test with a macro single body, in a semiconductor integrated circuit in macro constitution. CONSTITUTION:When a macro A20 is a tested macro, the test pattern and the output expected value pattern of the macro A20 are inputted from an input/ output terminal 50 and temporarily stored in a test pattern memory 41 and an expected value pattern memory 42, and a selector 10 inputs the test pattern supplied from the test pattern memory 41 into the macro A20 under the control of a control circuit 40, and a driver 30 inputs the output pattern of the macro A20 into a comparison circuit 43. The comparison circuit 43 compares the output pattern and the output expected value pattern memorized in the expected value pattern memory 42, and the result of the comparison is outputted into the input/output terminal 50. item. The fail memory 5 memorizes the judgement result 107 of the comparison judging circuit 3 successively into the address 106 supplied from the pattern generating circuit 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in semiconductor integrated circuits, and in particular, in digital large-scale integrated circuits (hereinafter referred to as LSIs).
That. ) Functional test circuit.

[0002]

2. Description of the Related Art An LSI test is carried out to detect a failure, and an LSI tester is generally used to test a target L
A functional test is performed by applying an appropriate input series to SI and comparing the resulting output series with the expected series.

A test pattern composed of the input series and the expected series is created by adding a pattern for increasing the failure detection rate of the LSI to a logic simulation pattern designed for logic verification. It is becoming difficult to predict the expected value of the entire circuit and create a test pattern with a high failure detection rate as the logic circuit of FIG.

In order to solve this problem, in the conventional semiconductor integrated circuit, the cut end of the macro is connected to the bus so that it can be directly accessed from the outside, or the scan path method or the BIST (Built In Self) method.
There are testability designs such as Test).

As an example of the method of directly accessing from the outside by connecting the cut end of the macro to the bus, as shown in FIG. 3, the test pattern input from the input terminal 54 is input to the selectors 10 to 10.
By selecting in 12, the macro to be tested is input to, for example, the macro A20, the output result of the macro A20 is selected by the driver 30, output from the output terminal 55, and externally compared with the expected value. Here, the control circuit 40a
Is for selecting a macro under test.

In the scan path system, the states of all the flip-flops (FF) in the sequential circuit are directly set from the outside, and a circuit for directly outputting the states to the outside is provided. The test pattern design of the sequential circuit is replaced with the test pattern design of the combinational circuit to enable automatic pattern generation.

In BIST, a test pattern is internally generated by a pseudo-random pattern generator, the output pattern is compressed by feature extraction and compared with an expected value to perform a self-test.

[0008]

In many cases, an LSI divides a circuit into several macros and is designed by a plurality of people to perform logic verification for each macro. However, a logic simulation pattern designed for logic verification is When macros are combined to form an entire circuit, the macro pattern must be corrected because the macro cuts disappear.

Therefore, as shown in FIG. 3, in the conventional semiconductor integrated circuit, a cut is provided between the macros to connect to the external terminals,
Although this problem is dealt with by making a comparison outside the LSI, there are drawbacks that the number of terminals of the LSI increases and the test speed decreases due to an increase in delay of the test path.

Further, in the test facilitation design such as the scan path method and BIST, not only the design considering the additional circuit for simplification of the test pattern is necessary from the beginning of the logic design, but also the design is restricted. In many cases, there was a drawback that the design could not be done unless the engineer was proficient in the test circuit.

It is an object of the present invention to provide a semiconductor integrated circuit which eliminates the above-mentioned drawbacks and enables testing by a macro unit, shortening the design period and speeding up the test. ..

[0012]

SUMMARY OF THE INVENTION The present invention includes a plurality of macros, a plurality of selectors for respectively selecting an output pattern of a preceding macro as a pattern input to each macro or a test pattern separately input, and each selector. In a semiconductor integrated circuit including a plurality of drivers for respectively taking out and driving macro outputs, an input / output unit and a test pattern input from the input / output unit are temporarily stored and are respectively input to one input of each pattern selector. Test pattern storage means for inputting, expected value pattern storage means for temporarily storing the output expected pattern of the macro under test input from the input / output means, and output expected value pattern stored in this expected value pattern storage means And the output pattern of the macro under test output through the driver, and the comparison result is input / output. Characterized in that it comprises a comparator circuit for outputting a stage, and a control circuit for controlling the test.

Further, in the present invention, it is preferable that the input / output means is one input / output terminal that serves both as an input of the test pattern and the expected output value pattern and as an output of the comparison result.

Further, in the present invention, the input / output means includes a first input terminal for inputting the test pattern, a second input terminal for inputting the expected output value pattern, and an output terminal for outputting the comparison result. Is preferred.

[0015]

When testing the macro, the test pattern and the expected output value pattern of the macro under test are stored in advance in the test pattern storage means and the expected value pattern storage means, respectively, and the test is performed under the control of the control circuit. The test pattern stored in the pattern storage means is input to the macro under test through the selector. Then, the output of the macro under test is input to the comparison circuit via the driver. The comparison circuit compares the output pattern of the macro under test with the expected output value pattern stored in the expected value pattern storage means, and outputs the comparison result via the input / output means.

Therefore, the macros can be tested in sequence for each macro, which simplifies the macro division design and increases the test speed. further,
By performing the speed conversion of the test pattern by the storage means, it is possible to further increase the test speed.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention, showing a test circuit part.

In the first embodiment, a plurality of macros A20, B21 and C22 and each macro A2 are provided.
A plurality of selectors 10, 11 and 12 for selecting the output pattern of the preceding macro or the separately input test pattern as patterns to be input to 0, B21 and C22, and outputs of the macros A20, B21 and C22, respectively. A plurality of drivers 30 to drive,
In a semiconductor integrated circuit including 31 and 32, an input / output terminal 50 as an input / output means and a test pattern input from the input / output terminal 50, which are the features of the present invention, are temporarily stored and each pattern is stored. A test pattern memory 41 as a test pattern storage unit which is input to one input of each of the selectors 10, 11 and 12, and an output expected value pattern of a macro under test (for example, macro A20) input from the input / output terminal 50 is temporarily stored. Value pattern memory 42 as expected value pattern storage means for storing the expected value pattern, output expected value pattern stored in the expected value pattern memory 42, and output of the macro under test output via the driver 30, 31 or 32. A comparison circuit 43 that compares the pattern and outputs the comparison result to the input / output terminal 50.
And a control circuit 40 for controlling the test.

Next, the operation of the first embodiment will be described.

The test pattern and the expected output value pattern for the macro under test are input from the input / output terminal 50 in advance at an arbitrary speed and stored in the test pattern memory 41 and the expected value pattern memory 42. The control circuit 40 uses a macro under test (in the following description, the macro under test is macro A
Perform as 20. ) Selector 10 selects the test pattern of the test pattern memory 41, and the macro A2
Driver 3 so that the output of 0 is input to comparison circuit 43
0 is controlled so that the comparison result can be observed outside the LSI by setting the input / output terminal 50 in the output mode.

Next, in the control circuit 40, the test pattern memory 41 and the expected value pattern memory 42 are the macro A20.
Control to output the test pattern at the test speed of. At this time, the comparison circuit 43 uses the expected value pattern memory 42.
The expected output value pattern, which is the output of, is compared with the output pattern of the macro A 20, and the comparison result is output through the input / output terminal 50.

Here, when the test speed of the macro A 20 is high and the IC test cannot be read, the expected value pattern memory 42 or the third memory may be provided and temporarily stored. In this way, after the test of the macro A20 is completed, the contents of the test pattern memory 41 and the expected value pattern memory 42 are rewritten, and the macro B21 is sequentially changed.
And test C22.

In FIG. 1, the test pattern memory 41 and the expected value pattern memory 42 are described separately for the sake of convenience, but it is not necessary to clearly distinguish them, and the memory area is determined according to the capacity of the input pattern and the output expected value pattern. Should be changed. The number of input / output terminals 50 does not have to be the same as the number of bits of the test pattern memory 41 and the expected value pattern memory 42, and serial / parallel conversion may be performed internally.

FIG. 2 is a block diagram showing the main part of the second embodiment of the present invention, showing the test circuit part. The second embodiment is different from the first embodiment shown in FIG. 1 in that the test pattern memory 4 is used as an input / output means, which is a feature of the present invention.
1. The expected value pattern memory 42 and the comparison circuit 43 are each provided with an input terminal 5 for exchanging data with the outside.
1, an input terminal 52 and an output terminal 53 are provided.

In the second embodiment, the number of external terminals for the test is increased, but the time for writing the pattern data in the test pattern memory 41 and the expected value pattern memory 42 can be shortened, and when the test is performed at a slow rate or the test pattern is used. It is suitable for a large quantity, and if a FIFO memory or the like is used as the test pattern memory 41 and the expected value pattern memory 42, the pattern can be replenished even while the macro under test is being tested, which has the advantage of shortening the test time.

[0027]

As described above, according to the present invention, the pattern memory for storing the test patterns is provided inside so that the test can be performed by the macro unit. The designed test pattern can be used as it is, and the design period can be shortened.

In addition, pattern speed conversion can be performed in the pattern memory unit, and a high-speed test that exceeds the limit of the test speed of the IC tester can be performed, and high reliability can be obtained, and without using the IC tester. There is an effect that a defect of the LSI internal circuit can be analyzed with an emulator having a simple mechanism.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a main part of a first embodiment of the present invention.

FIG. 2 is a block diagram showing a main part of a second embodiment of the present invention.

FIG. 3 is a block configuration diagram showing a main part of a conventional example.

[Explanation of symbols]

 10-12 selector 20 macro A 21 macro B 22 macro C 30-32 driver 40, 40a control circuit 41 test pattern memory 42 expected value pattern memory 43 comparison circuit 50 input / output terminals 51, 52, 54 input terminal 53, 55 output terminal

Claims (3)

[Claims] 1. A plurality of macros, a plurality of selectors for respectively selecting an output pattern of a preceding macro or a test pattern separately input as a pattern input to each macro, and an output of each macro is taken out and driven. In a semiconductor integrated circuit including a plurality of drivers, an input / output unit, a test pattern storage unit for temporarily storing a test pattern input from the input / output unit and inputting it to one input of each pattern selector, The expected value pattern storage means for temporarily storing the expected output pattern of the macro under test input from the input / output means, the expected output value pattern stored in the expected value pattern storage means, and the output expected value pattern output by the driver. And a comparison circuit for comparing the output pattern of the macro under test and outputting the comparison result to the input / output means. The semiconductor integrated circuit which comprises a control circuit for controlling the test. 2. The semiconductor integrated circuit according to claim 1, wherein the input / output unit is one input / output terminal that serves as both an input of the test pattern and the expected output value pattern and an output of the comparison result. .. 3. The input / output unit is a first input terminal for inputting the test pattern, a second input terminal for inputting the expected output value pattern, and an output terminal for outputting the comparison result. 1. The semiconductor integrated circuit according to 1.