JPH05312921A - Integrated circuit - Google Patents

Abstract

PURPOSE:To obtain an integrated circuit, especially a high-density integrated circuit (VLSI), which requires the short time for preparing a test pattern and the short time the test itself and does not decrease the space of a chip substrate, which regard to the integrated circuit, whose diagnosis is made easy. CONSTITUTION:A plurality of functional blocks 10a, 10b and 10c are divided for every function and arranged on a chip substrate 1. Intermediate diagnostic terminals 40 are provided in correspondence with the lines for connecting the functional block at the front stage and the functional block 10 at the rear stage. Switching functions connect and disconnect the lines for connecting the functional block 10 at the front stage and the functional block 10 at the rear stage. Other switching functions guide the signals of the test results from the output sides of the functional blocks 10 to the intermediate diagnostic terminals 40. Other switching functions input the test pattern signals into the functional blocks 10 from the intermediate diagnostic terminals 40. These parts are provided. Switching means 30 are arranged on the chip substrate 1 in correspondence with the intermediate diagnostic terminal 40 in this constitution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit, and more particularly to a high density integrated circuit (VLSI) for facilitating diagnosis.
It is about.

[0002]

2. Description of the Related Art An integrated circuit is one of the most important circuit elements forming a computer system, and its high density has been studied in order to expand the function of the computer system and further downsize it. There is. An integrated circuit (LSI) or a high-density integrated circuit VLSI (hereinafter abbreviated as LSI) has been realized to satisfy this purpose.

In a logic element having a small number of gates, whether or not the logic element operates normally can be easily determined by observing a waveform with an oscilloscope, for example. However, LSI
Is composed of, for example, tens of thousands of gates of logic elements, and it is impossible to make a detailed test as to whether or not this is operating normally by diagnosis using an oscilloscope or the like as described above.

Therefore, in the diagnosis of such a multi-gate logic element, a pin is set up at the input end of the gate, a predetermined test pattern signal is input, and a predetermined test result corresponding to the test pattern signal is output from the output end. Diagnosis is performed by a method of determining whether or not a signal is obtained (first method).

Further, the test pattern is generated on the LSI chip substrate, and the test pattern is set to L.
A method called a built-in self-diagnosis method is also used in which a diagnostic circuit having a function of determining suitability of a test result signal obtained by supplying the SI is provided.

In this built-in self-diagnosis method, for example, as disclosed in Japanese Unexamined Patent Publication No. 52-83082, a plurality of modules of the same circuit are formed in a logic circuit of an LSI divided into functional blocks. There is a method in which a test module is added to each module unit and only non-defective modules are selected to function.

There is also a diagnosis system as described in Japanese Patent Laid-Open No. 54-27784, which is a combination of the first conventional system and the built-in self-diagnosis system. That is, a unit operation designating register and a block controller are provided for each functional block of an LSI divided into functional block units,
A master controller that integrally controls all block controllers is provided outside the LSI to perform functional diagnosis in block units.

[0008]

In the diagnostic test according to the first method, the number of test patterns becomes enormous and it takes a lot of time to create the test patterns.
This test pattern is created while simulating with software equivalent to the LSI to be diagnosed, but if the number of gates reaches hundreds of thousands, the simulation time may reach 100 hours.

In addition, an increase in the number of test patterns naturally extends the diagnosis time, and the test pattern can be applied only for a short time so as not to damage the element to be diagnosed and the surrounding elements. In (test), the test time is further increased due to the time constraint.

Further, in the above built-in self-diagnosis method, since the diagnostic circuit itself is incorporated in the chip substrate, the space of the chip substrate is pressed and the incorporated diagnostic circuit itself may be damaged. This drawback is disclosed in JP-A-54-
It naturally occurs even when only the block controller and the register shown in Japanese Patent No. 27784 are incorporated in the chip substrate.

The present invention has been proposed in view of the above-mentioned conventional circumstances, and the test pattern creation time is short, therefore the test time itself is short, and further, the integrated circuit which does not press the space of the chip substrate, particularly high density It is intended to provide an integrated circuit (VLSI).

[0012]

The present invention employs the following means in order to achieve the above object. That is, as shown in FIG. 1, a plurality of functional blocks 10 divided for each function and arranged on the chip substrate 1, and a functional block 10 in the preceding stage and a functional block 10 in the subsequent stage are connected between the functional blocks 10. Intermediate diagnosis terminal 40 provided corresponding to each line, a switch function for connecting and disconnecting each line connecting the preceding functional block 10 and the subsequent functional block 10, and a test result from the output side of each functional block 10. The chip board 1 is provided with a switch function for deriving a signal to the intermediate diagnosis terminal 40 and a switch function for inputting a test pattern signal to each functional block 10 from the intermediate diagnosis terminal 40. The switch means 30 is arranged on the upper side.

The switch means 30 is composed of the following three-state circuits. That is, the three-state circuit 31 that connects the output side of the preceding functional block 10 and the input side of the following functional block 10 and each functional block 1
The three-state circuit 32 connects the output side of 0 with the intermediate diagnosis terminal 40, and the three-state circuit 33 connects the input side of each functional block 10 with the intermediate diagnosis terminal 40.

In addition to the intermediate diagnosis terminal 40,
A control terminal 41 for inputting a control signal for commonly controlling the three-state circuits 31, 32, 33 provided between the functional blocks 10 is provided.

In the surface mount type integrated circuit, the intermediate diagnosis terminal 40 is arranged on the outer peripheral upper surface of the package 20 of the chip substrate 1, and the package 2 of the chip substrate 10 is provided.
It is provided below 0.

[0016]

As described above, the switch means 30 is made up of three sets of three-state circuits 31, 32, and 33 as described above. For example, by turning on the control signal supplied from the control terminal 41, the front and rear stages are connected. Function block 10
Three-state circuit 31 inserted in the line connecting
When the three-state circuit 32 inserted between the output side of the preceding stage and the terminal 40 for intermediate diagnosis is ON, the three-state circuit 33 inserted between the input side of the latter stage and the terminal 40 for intermediate diagnosis is It turns off (state I).

Next, the control signal supplied from the control terminal 41 is turned off, for example, so that the three-state circuits 31 and 32 are turned off and the three-state circuit 33 is turned off.
N (state II).

Here, the input side switch means 30 of the functional block 10 is set to the state II, and the output side switch means 30.
When the test pattern is input from the input side intermediate diagnosis terminal 40 of the function block 10 in the state I, the test result signal can be obtained from the output side intermediate diagnosis terminal 40 of the function block 10, and the function block 10 is used independently. Can be diagnosed.

In the surface mount type component, the pad-like intermediate diagnosis terminal 40 is provided on the upper side of the LSI package 20, and the diagnosis pin is set up there. In the insertion part, the lead-like intermediate diagnosis terminal 40 is formed on the lower side of the LSI package 20, and the diagnosis test is performed in a state where the lead-like intermediate diagnosis terminal 40 is inserted into the through hole.

[0020]

FIG. 1 is a block diagram showing an embodiment of the present invention. A plurality of function blocks 10 (10a, 10b ...) Divided according to functions are arranged on the chip substrate 1, and switch means 30 (30a, 30b ...) In the middle of a line connecting adjacent function blocks 10. Is provided. The switch means 30 (for example, 30a) is provided in the number corresponding to the line connecting the adjacent functional blocks 10, and the switch means 30 (for example, indicated by a hyphen and a suffix of number k after 30a) is as shown in FIG. It is composed of a set of three three-state circuits.

The switch means 30a- ₁ will be described below as an example. First, the line connecting the functional block 10a in the preceding stage and the functional block 10b in the succeeding stage is a three-state circuit 31.
It is designed to be intermittent at a _-1 .

On the other hand, as shown in FIG.
The switch means 30a is provided around the outside of the package 20._-1Against
Accordingly, the intermediate diagnosis terminal 40a_-1Are arranged. That
The three-state circuit 31a_-1Input side (previous stage
Branch from the output side of function block 10a)
Circuit 32a_-1Intermediate diagnosis terminal 40a_-1To
Line is provided. Furthermore, the above three-state
Circuit 31a_-1Output side (input of the function block 10b in the latter stage
Branch from the input side) and the three-state circuit 33a _-1Through
The above-mentioned intermediate diagnosis terminal 40a_-1The line leading to
ing.

Of course, each switch means 3
0a _-k , 30b _-k, ... Corresponding to the intermediate diagnosis terminal 4
0a _-k , 40b _-k, ... And three-state circuits (31a _-k , 32a _-k , 33a _-k ) (31
b- _k , 32b- _k , 33b- _k ) ... are provided.

Further, each switch means 30a_-k, 30b_-k
, Which are provided with common control terminals 41a, 41b ...
Has been. From the control terminal 41a, the above three
A control signal for controlling the control signal to 0N or OFF is applied.
And the control signal is ON, the three-state circuit 3
1a _-kAnd three-state circuit 32a_-kIs turned on,
Lee state circuit 33a_-kTurns off (state I).
In addition, the control signal input from the control terminal 41a is OF
If it is F, the three-state circuit 31a_-kAnd three stee
Circuit 32a_-kTurns off and the three-state circuit
33a_-kTurns on (state II).

In the above configuration, for example, the switch means 30a- _k on the input side of the functional block 10b is set to state II,
When the switch means 30b _-k on the output side of the functional block 10b is set to state I and a test pattern is input from the intermediate diagnostic terminal 40a _-k on the input side of the functional block 10b, the intermediate means of the switch means 30b on the output side of the functional block 10b is input. A test result signal can be obtained from the diagnostic terminals 40b- _k . In this case, the switch means 30c- _k , 30 that follow the latter stage
By setting all d- _k ... To the state I, it is possible to diagnose each of the functional blocks 10c, 10d ... In a continuous state.

The input terminal 42 of the LSI package 20
When diagnosing the functional block 10 (10a in FIG. 1) closest to the function block 10 (10c in FIG. 1), the test pattern signal is applied from the input terminal 42 and conversely the functional block 10 (10c in FIG. 1) closest to the output terminal 43 of the LSI package 20. At the time of diagnosis, the test result signal is derived from the output terminal 43.

The number of test patterns is remarkably reduced by performing the diagnosis by dividing the function into each function.
Moreover, the diagnosis time can be shortened. Further, since the diagnostic circuit other than the switch circuit is not provided on the chip substrate, the area of the chip substrate can be effectively used.

It is needless to say that such a diagnosis can be performed by the LSI alone, but even when the LSI is arranged on the printed circuit board, in order to diagnose the suitability of the connection between the printed circuit board and the LSI. Done.

FIG. 3 shows an arrangement structure of the intermediate diagnosis terminal 40 and the control terminal 41 of the present invention on the package 20. The surface mount component is formed as a pad on the upper surface of the component as shown in FIG. 3A, and the insert component is formed as shown in FIG.
It is formed as a lead on the lower surface of the component as shown in FIG. This facilitates diagnosis of the connection state of the LSI mounted on the printed circuit board.

[0030]

As described above, according to the present invention, an intermediate diagnostic terminal is provided between each functional block, a test pattern signal is applied to the intermediate diagnostic terminal, and a test result signal is output from the intermediate diagnostic terminal. Since the switch means for deriving the test pattern is provided, the test pattern can be given to each functional block for diagnosis, the test time can be shortened, and the space of the chip substrate can be effectively used. it can.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram showing details of the switch means of the present invention.

FIG. 3 is an external view of an integrated circuit to which the present invention is applied.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 chip substrate 10 functional block 20 package 30 switch means 31 three-state circuit 32 three-state circuit 33 three-state circuit 40 intermediate diagnosis terminal 41 control terminal

Claims (5)

[Claims] 1. A plurality of functional blocks (10) divided on a chip substrate (1) for each function, and a functional block (10) in a preceding stage and a functional block in a subsequent stage between the functional blocks (10). Intermediate diagnostic terminal (40) provided corresponding to each line connecting (10), the above-mentioned functional block (10) in the preceding stage and functional block (10) in the subsequent stage
The switch function that connects and disconnects each line that connects to, the switch function that derives the test result signal from the output side of each function block (10) to the intermediate diagnosis terminal (40), and each function block (1
0) is provided with a switch function for inputting a test pattern signal from the intermediate diagnosis terminal (40), and switch means (30) provided on the chip substrate (1) corresponding to the intermediate diagnosis terminal (40). ) And an integrated circuit. 2. A three-state circuit (31) in which the switching means (30) connects and disconnects the output side of the preceding functional block (10) and the input side of the following functional block (10), and each functional block (1).
Three-state circuit (32) that connects the output side of (0) to the intermediate diagnosis terminal (40), and three-state circuit (33) that connects the input side of each functional block (10) to the intermediate diagnosis terminal (40) The integrated circuit according to claim 1, further comprising: 3. A three-state circuit (31) provided between the functional blocks (10) in addition to the intermediate diagnosis terminal (40).
The integrated circuit according to claim 1, further comprising a control terminal (41) for inputting a control signal for commonly controlling the (32) and (33). 4. The intermediate diagnostic terminal (40) is a chip substrate
The integrated circuit according to claim 1, which is of a surface mounting type and is arranged on the outer peripheral upper surface of the package (20) of (1). 5. The intermediate diagnosis terminal (40) is a chip substrate.
The integrated circuit according to claim 1, which is an insertion type provided on the lower side of the package (20) of (1).