JPS604238A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To perform circuit check of a printed wiring board easily and rapidly by providing the constitution wherein the signals of input points can be selectively outputted from the output points of the function circuit part which are predetermined to correspond. CONSTITUTION:When checking a circuit pattern including the input and output circuit in the LSI chip 10, low-level signals are selectively applied to a control signal input pin 15 through a contact pin of an in-circuit tester. Consequently, the AND/OR circuits 141-14n become the selection mode that the signals of input points I1-In of a function circuit part 11 are outputted as they are from the output points O1-On which are predetermined to correspond. Namely, at this time, O1=I1, O2=I2..., On=In. Thus, because of the low level of the control signal input pin 15, the input signals supplied to the input points I1-In are outputted from the corresponding output points O1-On with by-passing through the function circuit part 11, and accordingly circuit checking of the printed wiring board on which the LSI chip 10 is mounted is substantially simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention particularly relates to a semiconductor integrated circuit device having a functional circuit that facilitates circuit checking of a printed wiring board after circuit components are mounted.

[Technical background of the invention and its problems]

In general, semi-custom LSIs such as gate arrays are
By incorporating into the LSI a circuit according to the function desired by the designer, an LSI having a desired logical function configuration can be obtained.

Generally speaking, in this type of LSI, the states of each of the plurality of outputs 1 and 7 form a complex logical function i.e.
When checking a printed wiring board on which I is mounted using an in-circuit tester, even if a single input signal is simply applied to the input terminal (input bin) of the mounted LSI, the correctness of each output terminal can be determined from that signal. 7 of the input signal.
- Since it is necessary to create a circuit board and check the circuit on the board, it is necessary to check whether the circuit is correct or not due to component mounting errors, poor solder contact, short circuits or disconnections, etc. on the board. This method requires a lot of labor and time, resulting in the inconvenience that efficient testing cannot be carried out.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a semiconductor integrated circuit device having a function of easily and quickly checking the circuit of a printed wiring board after circuit components are mounted.

[Summary of the invention]

The present invention provides an output signal of a functional circuit section within a chip,
Alternatively, a gate circuit that selectively outputs a specific input signal to the corresponding output pin may be provided corresponding to each output pin, and these valley gate circuits may be simultaneously and selectively switched by a specific input pin signal. It is possible to selectively supply input signals associated with each other in advance. As a result, after mounting an LSI having the above selection switching function, such as a gate array LSI, on a printed wiring board, when checking the circuit of the board, the input signal applied to the input end (input pin) of the gate array can be transferred to the chip. Since it is possible to selectively output the output terminal (output bin) while bypassing the internal functional circuit section, it is possible to easily check the circuit on the "2" board.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In the figure, 10 is an LSI chip such as a gate array, and 11 is a predetermined functional circuit section (
Function Logic).

121HI 22+..., 12n are input bins correspondingly connected to each input point 11+I2+..., In of the above-mentioned 4 geometric circuit sections 1, IJ 1+ 132+...'
+ I Jn is an output bin correspondingly connected to each of the same output points 01+02, . 141.

142,..., 14n are the above output points O and 0□,...+
An AND-OR circuit 15 is provided corresponding to the ON signal. ..., 14n
The specific control signal input pin 16 to which the selection control signal (SC) of is applied is an inverter. The AND-OR circuits 741.14□, . . . , 14n each output the pre-corresponding output points (01+021, . . .
・, On) signal or input point (■l+I2+"'+I
n) signal i is selectively output to the LSIS edge 1θ output bin 13 and 132 . ..., which simultaneously outputs to 13n,
Here, when the selection control signal (SC) is in a high level state (no low level signal is input), the functional circuit section 1
1 output point (0,,,0□,...+'J) n)
Output bins 13 . ．． 132.・
..., 13n, and when the selection control No. 1.1 (SC) is in a low level state, the input point (I
, , I2+ . . . , In) signals are output from the output bins 13 . ．． 132
．． ..., 13nVCJ4.

The operation of one embodiment will now be described with reference to the drawings. When performing a circuit check using an in-circuit tester on a printed wiring board on which the illustrated LSI chip 1o is mounted, a signal such as f=I is not applied to the control signal input bin 15 of the LSI chip 1o, and the input When the (Fj state of bin 15 is at a high level due to the action of the sol-up resistor (R), the AND-OR circuits 141+ 142 +..., 14
n is each output point 01+021... of the functional circuit section 11,
"1-" of "On" is selected, and the signals are output to the corresponding output bins 131.1.?2°..., 13n.Therefore, in this case, as in the past, one output consisting of 1r is selected. Bin l 3i (i=1, 2.

. . , n) are simply applied to the input bins 121, 12□, . . . , 12n. It is determined by the combination. 1Qll et al., l-, iJ
L each mold □n 131+J 321...+13n each 1, -7 j7. j? ir, t l! lJj
Logic function of IF2 circuit part 1 and each human power point 1. , I2.
....

It is constant depending on the state of (ffi) of In, and 01 =
=11(11+I2+”'+In)02
= f2 (11, I2 + -, In C0n=fn
(11+I2+"'+In), each output point 0
1,0□,... (the signal state of month 1 cannot be determined simply from the input signal). Therefore, even if you input a specific signal to the pin/21 (=i, 2..., n) of the mounted LSI chino: 7"10 from the contact bin of the in-circuit tester, the signal will be output from the output bin 1. .9i's signal state is not uniquely determined, and each output pin 13..13
□.

..., 13n attachment j1.・9 on each turn
[If you want to output the desired signal, use LSI Chinoflo
A sea fence of l time-determined input signals is created taking into consideration the logic capability of the functional circuit unit 1) in the input bins 121, l22. ..., I have to give it to 12n.

Therefore, when I checked the circuit pattern including the input/output circuits in the LSI f, 1θ, I tested the 1tll j! A low-level signal is selectively applied to the signal cabinet 15. This causes an AND-OR circuit 141 in the LSI chip 10.

I42. , 14n are each input point I of the functional circuit section 11,
, I2. . . , In signals are output as they are to respective output points Ol+ 02 + . That is, here, 0,=1°0□=12 On=In. By setting the control signal input bin 15 to a low level in this way, the input points I, , I2 . ....

In the state where the input signal supplied to In pinoses the termination circuit section Il, the corresponding output points 01, 02 +...
.

Since the output is output from ON, the circuit pattern of the printed wiring board mounted with the LSI chip 10 is simplified, and the desired circuit pattern can be checked easily and in a short time. can.

In addition, in the above-mentioned actual jifi example, for convenience of explanation,
The number of input points and the number of output points of the functional circuit section 1) are shown as the same number (n), but for example, the number of output points is equal to the number of input points (■
I+I7+”'+In) less than m(01+02
+ ”' + Om), then it, 01 nies 2-I2 0m = Im, each output point 0..o2...., 01n corresponds to the input point ■1゜■2...., Im Attach, input point Ii
(, Y, p5 may be selectively output to the output point Oi, or conversely, if the number of input points is the number of output points n(OH).

021−・+ On ) less than m(II + I
2 + “” + Im), then 01″=I.

0,, = I2 0m 0m + 1 = I.

As On = I (1, 2, -, m), input each output point 01 + 021...+On, 曵II.

It is associated with r, .

〔Effect of the invention〕

As detailed above, the semiconductor integrated circuit device (6゛,
According to the above, it is possible to selectively output signals from input points associated with each other in advance from each output point of a functional circuit section, and thereby the circuit of the printed wiring board formed by mounting the above-mentioned semiconductor integrated circuit device (1'L). Checking can be done easily and quickly.

[Brief explanation of drawings]

The figure is a block diagram 1 showing one embodiment of the present invention. 10...LSI chip, 11...machine (chemical circuit section, 1
21゜122,..., 12n...Input pin, 131
,132+... 13n...Output pin, 141+I (21..., 14
n...AND OR circuit, 15...Control I 11Y signal input bin, ■. I21...HIrr+ ・=input point, 01 + 0
21 ...+ On +++ i3 emphasis.

Claims (1)

[Claims] In a semiconductor integrated circuit device provided with a functional circuit section having a plurality of input points and output points, each of the output points and each signal derivation line specific to this output point are associated with each other in advance. A semiconductor integrated circuit device having a structure in which a plurality of gate circuits are provided for selectively outputting an input point signal or a corresponding output point signal, and each gate circuit is simultaneously and selectively switched and controlled by a specific input bin signal.