JPH0325382A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the circuit from malfunctioning owing to the simultaneous operation of many output buffers by making comparisons with output expected values by an internal comparing circuit and outputting only decision result signals to an external circuit when the function of a logic circuit is tested. CONSTITUTION:The logic circuit 10 operates with an input signal from the external circuit, the signal direction of a two-way buffer 11 is controlled with a two-way buffer control signal line 13 supplied from the logic circuit 10, and when a two-way buffer control signal is at high level, the output signal of the circuit 10 is outputted to the external circuit. When the two-way buffer control signal is at low level, on the other hand, the expected value signal as a logic circuit output corresponding to the current input signal is inputted from the external circuit. The circuit 12 receives and compares the output signal of the circuit 10 and the expected value signal read out of the buffer 11 with each other and outputs their coincidence/dissidence decision result signal to the external circuit.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor integrated circuits.

[Conventional technology]

Conventionally, this type of semiconductor integrated circuit directly outputs the output signal of the logic circuit 9 during a functional test of the logic circuit 9, and compares the output signal with an expected value signal in an external comparator 8, as shown in FIG. He was making a judgment.

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuit described above, when a large number of output buffers and buffers operate simultaneously, the current for driving the load flows in the power supply and ground lines in a concentrated manner for a short period of time, causing noise and damaging the circuit. There is a risk of malfunction. During actual use, it is possible to take measures such as strengthening the power supply and ground lines of the mounted printed circuit board, but during testing, it is difficult to strengthen the power supply and ground lines of the LSI tester, and circuit malfunctions occur due to the simultaneous operation of many output buffers. There is a drawback.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit in which the above-mentioned drawbacks are solved and a functional test can be performed without malfunction.

[Means to solve the problem]

The structure of the semiconductor integrated circuit of the present invention includes a logic circuit that operates according to an input signal from an external circuit, and an output signal of the logic circuit is output to the external circuit during normal use, and when performing a functional test of the logic circuit. , a bidirectional buffer that functions to take in an expected value signal of the output of the logic circuit corresponding to a given input signal from an external circuit, and an output signal of the logic circuit and an expected output value taken in from the bidirectional buffer. The present invention is characterized by comprising a comparison circuit that compares the signals and outputs a determination result signal of coincidence or mismatch to the external circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a functional block diagram showing a semiconductor integrated circuit of the present invention. In FIG. 1, in this embodiment, a logic circuit 10 operates with an input signal from an external circuit, and a bidirectional buffer 1
The direction of the signal is controlled by the bidirectional buffer control signal line l3 given by logic circuit 10, and when the bidirectional buffer control signal is at a high level, the output signal of logic circuit 10 is sent to an external circuit (not shown). When the bidirectional buffer control signal is at a low level, the expected value signal of the logic circuit output corresponding to the input signal at that time is input from the external circuit. Comparison circuit 12 receives and compares the output signal of logic circuit 10 and the expected value signal read from bidirectional buffer 11, and outputs a determination result signal of coincidence or mismatch to an external circuit.

FIG. 2 is a circuit diagram showing a specific structure of a part of the bidirectional buffer and comparison circuit of FIG. 1 for one signal. In FIG. 2, a test/normal mode switching signal given as one of the input signals from an external circuit is used as the bidirectional buffer control signal. When the test/normal mode switching signal is at a high level, that is, during normal use, the bidirectional buffer 14 outputs an output signal from the logic circuit to an external circuit as an output signal from the semiconductor integrated circuit. On the other hand, exam/
When the normal mode switching signal is at a low level, that is, during a functional test of the logic circuit, the bidirectional buffer 14 enters the input state and reads the expected value signal of the output of the logic circuit corresponding to the input signal at that time. The read expected value signal is applied to one input of an exclusive OR circuit 15, which constitutes a part of the comparison circuit.

The other input of the exclusive OR circuit 15 is given an output signal from the logic circuit. Here exclusive disjunction 15
The output signal (coincidence signal) of is low level when the two input signals, that is, the output signal from the logic circuit and the expected value signal match, and is high level when they do not match.

In reality, the number of circuits shown in FIG. 2 is equal to the number of output signals of the logic circuit 10, and the output signal (coincidence signal) of the exclusive OR circuit 15 in each circuit is the output signal of the multi-input OR circuit. given to the input. In other words, the comparator circuit 12 has the configuration shown in FIG. The output signal, that is, the output signal of the comparator circuit l2 becomes low level. On the other hand, if there is even one mismatch between the output signal of the logic circuit 10 and the expected value signal given from the external circuit, O
The output signal of the R circuit 16, that is, the output signal of the comparator circuit is at a high level, and the output signal of the comparator circuit 12 is at a low level if the output signal of the logic circuit 10 and the expected value signal completely match.
If they do not match, it is output to an external circuit as a determination result signal that goes high.

As described above, during normal use, the semiconductor integrated circuit of the present embodiment outputs the output signal of the logic circuit to the external circuit in the same manner as the conventional semiconductor integrated circuit. On the other hand, when testing the functionality of a logic circuit, the output signal of the logic circuit is not output to the external circuit, but a comparison with the expected value signal is performed using a built-in comparison circuit, and only the judgment result signal is output to the external circuit. . In this case, no matter how many output signals there are from the logic circuit, since the only output signal from the semiconductor integrated circuit is the determination result signal, malfunction of the circuit will not occur due to simultaneous operation of a large number of output buffers.

Further, in order to create test patterns for functional testing of logic circuits, it is sufficient to create expected value patterns of outputs corresponding to respective input patterns, as in the case of conventional semiconductor integrated circuits. During testing, the expected value pattern is applied as an input pattern to the target terminal, and only the determination result signal, which is the only output signal, is observed.

Next, as a second embodiment of the present invention, a case will be described in which the exchange of signals between the logic circuit and the external circuit is bidirectional. FIG. 4 is a circuit diagram showing a specific structure of a part of a bidirectional buffer and a comparator circuit for one signal in a second embodiment of the present invention. In FIG. 4, in this embodiment, the test/normal mode switching signal is at a high level during normal use. The bidirectional buffer 17 outputs an output signal from the logic circuit to an external circuit, and provides a signal from the external circuit to the logic circuit. The direction of operation of the bidirectional buffer 17 at this time is controlled by a direction switching signal of a logic signal output from a logic circuit. When the direction switching signal of the logic signal is at a high level, the output signal of the AND circuit 18 in the figure becomes a high level, and the bidirectional buffer 17 outputs the output signal from the logic circuit to an external circuit. When the direction switching signal of the logic signal becomes low level, the output signal of the AND circuit 18 becomes low level, and the signal from the external circuit passes through the bidirectional buffer 17 and is applied to the logic circuit.

During a functional test of the logic circuit, the test/normal mode switching signal is at a low level, and the output signal of the AND circuit 18 is at a low level regardless of the state of the direction switching signal of the logic signal. Then, when the direction switching signal of the logic signal is at a high level, the expected value signal is applied to the exclusive OR circuit 20 through the bidirectional buffer 17 and compared with the output signal from the logic circuit. In the case of the second embodiment, the output signal of the AND circuit 19 becomes a coincidence signal. Since the direction switching signal of the logic signal, which is one input of the AND circuit 19, is at a high level, the coincidence signal is in the same state as the output signal of the exclusive OR circuit 20, which is applied to the other input of the AND circuit 19. . In other words, the match signal becomes low level if the output signal from the logic circuit and the expected value signal match, and becomes high level if they do not match.

On the other hand, when the direction switching signal of the logic signal is at a low level, that is, when the direction of the target signal is input from the external circuit to the logic circuit, the coincidence signal that is the output of the AND circuit 19 is always at a low level. Become.

〔Effect of the invention〕

As explained above, the present invention does not output the output signal of the logic circuit to an external circuit during a functional test of the logic circuit, but compares it with the expected output value using the built-in comparison circuit, and only outputs the judgment result signal. Since it is output to an external circuit, there is an advantage that malfunction of the circuit does not occur due to simultaneous operation of a large number of output buffers.

1 is a functional block diagram showing a conventional semiconductor integrated circuit.

8... Comparator, 9... Semiconductor integrated circuit, lO... Logic circuit, 11, 14.17...
... Bidirectional buffer, 12 ... Comparison circuit, 1
3...Bidirectional buffer control signal line, 15.20
...Exclusive OR circuit, 16...OR
Circuit, 18...AND circuit, 19...
AND circuit.

Claims (1)

[Claims] a logic circuit that operates based on input signals from an external circuit;
During normal use, the output signal of the logic circuit is output to an external circuit, and when performing a functional test of the logic circuit, an expected value signal of the output of the logic circuit corresponding to a given input signal is taken from the external circuit. and a comparison circuit that compares the output signal of the logic circuit with the output expected value signal fetched from the bidirectional buffer and outputs a match/mismatch determination result signal to the external circuit. A semiconductor integrated circuit characterized by: