JPH08146091A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To perform a high speed operation test without using a frequency divider circuit in a semiconductor integrated circuit requiring high speed operation exceeding the standards of an LSI tester. CONSTITUTION: Output terminals 102, 104 are directly connected to input terminals 105, 113 on a test board. A comparison circuit 107 performs the comparison of the coincidence/non-coincidence of the logic of the output data signal (a) of a circuit to be inspected and an expect value signal (c). A latch circuit 110 stores the output comparison result of the comparison circuit 107 and holds a memory state at the time of a high level showing non-coincidence even once in the comparison result. By this constitution, a high speed operation test exceeding the standards of an LSI tester can be performed within a semiconductor integrated circuit even when the LSI tester is not used. The memory content of the latch circuit 110 can be judged by the LSI tester through an output terminal 116.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit that requires a high-speed operation and that includes a circuit for a non-defective product determination test.

[0002]

2. Description of the Related Art Semiconductor integrated circuits generally use a tester for large-scale semiconductor integrated circuits (LSI) to select good products. An operation speed test may be performed as one of the items for determining the non-defective product. Conventionally, when a semiconductor integrated circuit to be measured is required to operate at a high speed exceeding the guaranteed standard of the LSI tester, the LSI tester performs a test only at a low-speed test cycle within the standard, and the high-speed operation is tested by each test. It was carried out by mounting the semiconductor integrated circuit on a separate test panel.

However, since a test panel is required to test the high-speed operation of the semiconductor integrated circuit, conventionally, a test circuit as shown in FIG. 3 is provided to test the high-speed operation. A semiconductor integrated circuit has been proposed (Japanese Patent Laid-Open No. 2-45971).

In this conventional semiconductor integrated circuit, the output buffer is replaced with a bidirectional buffer in which an output buffer 301 and an input buffer 302 are connected in series.
The signal output from 01 to the output terminal 303 is also input to the input buffer 302, the output signal of the input buffer 302 is supplied to the selector circuit 305 together with the logic signal via the frequency dividing circuit 304, and the selector circuit 305 selects the signal. The signal selected based on the signal is output to the output buffer 30.
It is a configuration for outputting to the output terminal 307 via 6.

According to this conventional semiconductor integrated circuit, the selector circuit 305 selects the output signal of the frequency dividing circuit 304 by the select signal at the time of test, and the frequency dividing circuit 304 reduces the speed of the signal due to the high speed operation. A signal is output to the output terminal 307 via the selector circuit 305 and the output buffer 306, and a pass / fail judgment test is performed based on this output signal.

[0006]

However, in the conventional semiconductor integrated circuit in which the LSI tester performs the test only in the low-speed test cycle, only the test at a speed slower than the actual operation can be performed, which causes a problem in the high-speed operation. A solid may be determined as a good product. Therefore, it is necessary to mount it on the test panel again to test the high-speed operation.

Further, in the conventional semiconductor integrated circuit shown in FIG. 3, since it is not possible to verify the output waveform after frequency division for every cycle of the test pattern before frequency division, the output waveform after frequency division can be verified. However, there is a problem in that detection may not be possible even if a logical error of several patterns occurs immediately after the change.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a semiconductor integrated circuit capable of performing a high speed operation test without using a frequency dividing circuit in a semiconductor integrated circuit which requires a high speed operation exceeding the standard of an LSI tester.

Another object of the present invention is to provide a semiconductor integrated circuit capable of accurately obtaining a test result of high-speed operation even when the phase of an expected value signal and the phase of a data signal are different. is there.

[0010]

In order to achieve the above object, the present invention provides a comparison circuit for determining whether or not the output data signal of the circuit under test and the expected value signal given from the first input terminal are in logic. And the output comparison result of the comparison circuit is stored for each pattern cycle of the test pattern given to the circuit to be verified, and when the comparison result indicating a mismatch even in the one pattern cycle is stored, the stored content is kept retained. The first latch circuit and the first output circuit output the output signal of the first latch circuit to the outside.

Further, according to the present invention, the output signal of the first latch circuit is stored for each predetermined number of patterns and is output to the first output terminal, and the comparison result showing a coincidence even once is shown. Has a second latch circuit that keeps the stored contents when the output signal of the latch circuit is stored, and the phase of the expected value signal is gradually increased from the first phase to the second phase by a predetermined pattern every predetermined number of patterns. The result of comparison is obtained by changing the value each time.

Further, according to the present invention, a second output terminal for outputting the output data signal of the circuit to be verified to the outside, a third output terminal for outputting a clock signal of one pattern period of the test pattern to the outside, and In a semiconductor integrated circuit having a second input terminal to which the output data signal of the verification circuit is externally input and a third input terminal to which the latch signal of the first latch circuit is externally input, a second output The terminals and the second input terminals and the third output terminals and the third input terminals are directly connected on the test board.

[0013]

[Operation] Generally, the output load capacity of an LSI tester is several tens of p
This is one of the reasons why this load makes verification of high-speed operation impossible. Therefore, in the present invention, in a semiconductor integrated circuit which is not provided with an output terminal for taking out the output data signal of the circuit to be verified, the comparison circuit compares the logics of the data signal and the expected value signal, and the comparison is performed. Since the comparison result is obtained from the first latch circuit by inputting the result to the first latch circuit, the comparison result can be obtained without using the frequency dividing circuit or the LSI tester.

Further, according to the present invention, the comparison result obtained by gradually changing the phase of the expected value signal from the first phase to the second phase by a predetermined phase for each predetermined number of patterns is stored in the second latch circuit. Moreover, when the comparison result shows a comparison result showing a match even once, since the stored contents are kept retained, it is possible to determine whether or not a mismatch occurs in any phase of the expected value signal. It can be taken out from the second latch circuit.

Further, according to the present invention, in the semiconductor integrated circuit having the second output terminal for taking out the output data signal of the circuit to be verified to the outside, the output data signal of the circuit to be verified is inputted from the outside. Since the two input terminals are directly connected on the test board, it is possible to obtain the comparison result of the logic match / mismatch of the data signal and the expected value signal without interposing the LSI tester.

[0016]

Next, an embodiment of the present invention will be described. FIG. 1 shows a circuit diagram of a first embodiment of a semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit 100 according to the present embodiment originally has output buffers 101 and 103 and output terminals 102 and 104.
In the semiconductor integrated circuit having the
08 and 113, input buffers 106, 109 and 11
4, a comparison circuit 107, a latch circuit 110, an output buffer 115, and a test circuit including an output terminal 116 are provided. The latch circuit 110 is a 2-input OR circuit 11
1 and a flip-flop 112 to which an output signal of the OR circuit 111 is applied to an input terminal.

Next, the operation of this embodiment will be described. In the semiconductor integrated circuit 100, the output data signal a obtained by the test pattern given to the circuit under test is output via the output buffer 101 to the output terminal. It is output from 102 to the outside. Further, the clock signal b of one pattern cycle of the test pattern, which is synchronized with the data signal a, is output from the output terminal 104 to the outside via the output buffer 103. When the LSI tester operates at a low speed within the standard, the output signals a and b of the output terminals 102 and 104 are input to the LSI tester and compared with an expected value to determine pass / fail.

However, when testing a high-speed operation that exceeds the standard of the LSI tester, disconnect the connection with the LSI tester,
Output terminals 102 and 104 on the DUT board (test board for interface between LSI tester and LSI)
Are connected to the input terminals 105 and 113, respectively. It is also possible to set a load condition in actual operation for this connection. The output terminal 116 is connected to the LSI tester, but this is not for comparison with the expected value signal, but merely for identifying the comparison result, as described later.

As described above, the output load capacitance of an LSI tester is generally as large as several tens of pF, and this load is one of the reasons why verification of high-speed operation is impossible. Therefore, in this embodiment, when verifying the high-speed operation, the data signal in the LSI tester cannot be accurately compared with the expected value, so that the output terminals 102 and 104 of the semiconductor integrated circuit 100 as described above.
And the LSI tester are disconnected and the output terminals 102 and 104 are directly connected to the input terminals 105 and 113 on the DUT board, thereby eliminating the delay due to the load capacitance and verifying high-speed operation. I am trying.

The data signal a output from the output terminal 102 is supplied to one input terminal of the comparison circuit 107 via the input terminal 105 and the input buffer 106.
On the other hand, the expected value signal c is input to the input terminal 108, and is supplied to the other input terminal of the comparison circuit 107 via the input buffer 109. As a result, the comparison circuit 107 outputs a high level when the data signal a and the expected value signal c do not match, and outputs a low level when they match.

Output signal of comparison circuit 107 (comparison result)
Is ORed with the output signal of the flip-flop 112 by the OR circuit 111 in the latch circuit 110 and then applied to the input terminal of the flip-flop 112. Also,
The clock signal b output from the output terminal 104 is applied as a latch signal to the clock terminal of the flip-flop 112 via the input terminal 113 and the input buffer 114. As a result, OR is performed in synchronization with this clock signal b.
The output signal of the circuit 111 is latched by the flip-flop 112.

Therefore, the latch circuit 110 makes a determination in the cycle of the clock signal b (one pattern cycle of the test pattern given to the circuit to be verified), and the output signal of the comparison circuit 107 is at a high level (that is, inconsistency) even once. ), Even if the output signal of the comparison circuit 107 becomes low level thereafter, the output signal of the flip-flop 112 becomes high level, and the output signal of the OR circuit 111 also becomes high level. The output signal of (the output signal of the flip-flop 112) always holds the high level. Here, the reset signal d is a signal that initializes the output signal of the latch circuit 110 and the internal state to a low level.

The output signal of the latch circuit 110 shows the result of comparison between the data signal a and the expected value signal c. The output signal passes through the output buffer 115 and the output terminal 116 and the external LS.
It is input to the I tester (not shown) and the comparison result of the high speed operation test is judged. Thus, according to the present embodiment,
High speed operation of the semiconductor integrated circuit 100 by directly connecting the output terminals 102 and 104 to the input terminals 105 and 113 in the immediate vicinity and comparing and collating the data signal a with the expected value signal c in the comparison circuit 107. The time verification can be performed without using the frequency dividing circuit.

In the above description, the data signal a synchronized with the clock signal b has been described, but it is also effective in the case of an asynchronous circuit. In this case, the latch circuit 11 is used.
The latch signal of 0 may be used as another clock signal synchronized with the pattern period.

Further, in the semiconductor integrated circuit which does not require external output of the high speed data signal a and the clock signal b, the data signal a is directly supplied inside the semiconductor integrated circuit.
And the clock signal b may be connected so as to be input to the comparison circuit 107 and the latch circuit 110, respectively.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 2 shows a circuit diagram of the second embodiment of the present invention. In the figure, the same components as those in FIG.
The description is omitted. In the first embodiment shown in FIG. 1, the data signal a input from the input terminal 105 and the input terminal 1
If the phases of the expected value signals c input from 08 are significantly different from each other, the comparison circuit 10
7 and the latch circuit 110 may be determined to be inconsistent.

Therefore, in the semiconductor integrated circuit 200 of the second embodiment shown in FIG. 2, the second latch circuit 201 is provided on the output side of the latch circuit 110, and the second latch circuit 201 is provided.
Output signal of the output terminal 20 via the output buffer 204
5, the phase of the expected value signal c is gradually changed, and when there is no discrepancy in any of the phases, it is determined that there is no problem in the high speed operation.

Here, the second latch circuit 201 described above is used.
Is a 2-input AND circuit 202 and a flip-flop 203
And the AND circuit 202 causes the latch circuit 110 to
Of the output signal of the flip-flop 203 and the signal of the output signal of the flip-flop 203 are input to the data input terminal of the flip-flop 203. The latch signal f is input to the clock terminal of the flip-flop 203, and the set signal g is input to the set terminal.

Next, the operation of this embodiment will be described.
First, the phase (delay amount) of the expected value signal c is set to P1, the comparison circuit 107 compares the expected value signal c with the data signal a, and the obtained comparison result is input to the first latch circuit 110. It is latched by the clock signal b. As described above, the comparison result latched by the latch circuit 110 outputs a high level when they do not match, and outputs a low level when they do match, so that the comparison circuit 10 outputs even once.
When the output signal of 7 becomes high level, the latch circuit 110
The output signal of (the output signal of the flip-flop 112) always holds the high level.

The output signal e of the latch circuit 110 is supplied to the AND circuit 202 in the latch circuit 201. Here, since the flip-flop 203 is set to the set state by the set signal g when the latch circuit 201 is initialized, the AND circuit 202 is in the gate “open” state in the initial state, and thus the output of the latch circuit 110 described above. The signal e is input to the data input terminal of the flip-flop 203 through the AND circuit 202.

An expected value signal c of the phase (delay amount) P1 for a predetermined number of patterns by the comparison circuit 107.
And the data signal a are compared, the flip-flop 203 latches the signal e input to the data input terminal by the latch signal f. Here, the output signal e of the latch circuit 110 is at a high level if the comparison result of the expected value signal c of the phase (delay amount) P1 and the data signal a does not match even once for the above-mentioned predetermined number of patterns. , Low level only when all match.

The signal latched by the flip-flop 203 is output to the output terminal 205 via the output buffer 204, and is also input to the AND circuit 202. Therefore, even if the output signal e of the latch circuit 110 becomes low level even once, even if the output signal e of the latch circuit 110 subsequently becomes high level, the flip-flop 112
Output signal is low level, the AND circuit 202
Since the output signal of the latch circuit 201 also becomes low level, the latch circuit 201
Output signal (output signal of the flip-flop 203) holds a low level.

Next, after the flip-flop 112 is reset by the reset signal d, the phase (delay amount) of the expected value signal c is switched to P2, and the predetermined number of patterns is again compared with the data signal a. Comparing circuit 1
The comparison result is latched in the flip-flop 203. Hereinafter, the same operation as above is performed with the expected value signal c
Is repeated while changing the phase (delay amount) of Pn to Pn.

In this way, the latch circuit 201, the output buffer 204, and the output terminal are provided only when the output signal of the latch circuit 110 is at a high level in all the phases (delay amounts) of the expected value signal c from P1 to Pn. The comparison result output via 205 becomes a high level indicating a non-coincidence, which causes the LSI tester to output the semiconductor integrated circuit 20.
0 is determined to be defective.

On the other hand, the phase (delay amount) of the expected value signal c is P
When the output signal of the latch circuit 110 becomes low level in any of 1 to Pn (that is, the expected value signal c
(When the data signal a matches the expected value signal c in any one of the phases), the latch circuit 201, the output buffer 2
The comparison result output via 04 and the output terminal 205 becomes a low level indicating coincidence, and the LSI tester determines that the semiconductor integrated circuit 200 is a non-defective product with no problem in high-speed operation.

[0036]

As described above, according to the present invention,
Since it is possible to obtain the result of comparison of the logic match / mismatch between the output data signal of the circuit under test and the expected value signal without using the frequency divider circuit or the LSI tester, it is possible to perform high-speed operation exceeding the guaranteed standard of the LSI tester. In addition to being able to carry out the test, it is possible to eliminate the inconvenience in the case of using the frequency dividing circuit, and when the above comparison result is input to the LSI tester, the above high speed operation test can be performed on the LSI tester.

Further, according to the present invention, the comparison result obtained by gradually changing the phase of the expected value signal from the first phase to the second phase by the predetermined phase for each predetermined pattern number is stored in the second latch circuit. The result of judgment whether or not a mismatch occurs in any phase of the expected value signal by storing and holding the stored content when the comparison result shows a comparison result showing a match even once. Therefore, even if the phase of the expected value signal and the phase of the data signal are different, the high-speed operation test result can be accurately obtained.

Further, according to the present invention, the output terminal for taking out the output data signal of the circuit to be verified to the outside and the input terminal for inputting the output data signal of the circuit to be verified from the outside are directly connected on the test board. By doing so, the comparison result of the logic match / mismatch of the data signal and the expected value signal is obtained without interposing the LSI tester.
A high-speed operation test that exceeds the guarantee standard of the SI tester can be performed.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional example.

[Explanation of symbols]

 100, 200 Semiconductor integrated circuits 101, 103, 115, 204 Output buffers 102, 104, 116, 205 Output terminals 105, 108, 113 Input terminals 106, 109, 114 Input buffer 107 Comparison circuit 110 First latch circuit 112, 203 Flip-flop 201 Second latch circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/822 H01L 27/04 T

Claims (3)

[Claims] 1. A comparison circuit for obtaining a logic match / mismatch between an output data signal of a circuit to be verified and an expected value signal given from a first input terminal, and an output comparison result of the comparison circuit to the circuit to be verified. Store for each pattern cycle of the given test pattern, and
A first latch circuit that keeps the stored content when the comparison result indicating a mismatch even in one pattern period is stored, and a first output terminal that outputs the output signal of the first latch circuit to the outside. A semiconductor integrated circuit having. 2. The output signal of the first latch circuit is stored for each predetermined number of patterns and output to the first output terminal,
In addition, the first result showing a comparison result indicating a match even once
When the output signal of the latch circuit is stored, it has a second latch circuit that keeps the stored content, and the phase of the expected value signal is gradually increased from the first phase to the second phase for each predetermined pattern number. 2. The semiconductor integrated circuit according to claim 1, wherein the comparison result is obtained by changing the phase by a predetermined phase. 3. A second output terminal for outputting the output data signal of the circuit to be verified to the outside, and 1 of the test pattern.
A third output terminal for outputting a clock signal of a pattern cycle to the outside, a second input terminal for receiving the output data signal of the circuit to be verified from the outside, and a latch signal for the first latch circuit from the outside. A third input terminal for inputting, and directly connecting between the second output terminal and the second input terminal and between the third output terminal and the third input terminal on a test board The method according to claim 1 or 2, wherein
The semiconductor integrated circuit described.