JPH0688862A - Semiconductor integrated circuit device and device and method for testing the same - Google Patents

Abstract

PURPOSE:To measure the real access time of the storage circuit of an object to be tested so as to make the performance evaluation of the object highly reliable by providing a circuit for dummy test which processes test clock signals in a dummied state separately from a circuit for test. CONSTITUTION:When a register clock RCK is inputted to a circuit 12 for dummy test, a test clock signal TCK and test output data DOUT are respectively held in a dummy register and data output register. In addition, a dummy output signal DTCK fed back from a gate array 26 incorporating a RAM and the data Dout are inputted to a data controller 25 through a test signal input section 24, but the signal DTCK and data DOUT are outputted from the dummy output buffer and test output buffer of the array 26. The controller 25 obtains dummy information regarding the delay time obtained by interposing the apparent access time of a RAM macro Mn containing delay time into the apparent access time of the macro Mn based on the signal DTCK based on the data DOUT and finds access time TAA from the two time lags.

Description

Detailed Description of the Invention

[Table of Contents] Industrial Application Field of the Prior Art (FIGS. 8 and 9) Problems to be Solved by the Invention Means for Solving the Problems (FIGS. 1 and 2) Action Embodiments (FIGS. 3 to 7) The invention's effect

[0002]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit device,
The present invention relates to a test apparatus and a test method thereof, and more specifically, to an improvement of a circuit for testing a semiconductor memory circuit built in a chip such as a gate array or a standard cell and an improvement of the test method.

In recent years, as semiconductor devices have been highly integrated and highly densified, RAMs have been mounted on chips such as gate arrays and standard cells.
A large-scale semiconductor integrated circuit (hereinafter referred to as LSI) device having a built-in (writable / readable memory at any time) macro tends to be developed. Further, with the demand for higher performance and higher performance of LSI devices, the access time of RAM tends to be further increased.

According to this, in order to facilitate the test of a large-scale LSI device, a test circuit including a test input buffer, a test output buffer, a test clock input buffer, etc. is provided inside the LSI device. A test input buffer and a test clock input buffer are commonly provided for a plurality of RAM macros.

However, since the test input / output wiring and the test clock wiring are laid long inside the chip, a very large wiring capacitance and stray capacitance are parasitic there, and
Because of the interposition of the test input / output buffer, it can adversely affect the RAM macro access time measurement.

Therefore, a new test auxiliary circuit is added to the object to be tested, and the influence of the delay of the test input / output wiring for transmitting the test input / output data and the test clock signal, the test clock wiring, and the test input / output buffer. There is a need for an apparatus and method that can eliminate the noise and measure the true access time.

[0007]

2. Description of the Related Art FIGS. 8 and 9 are explanatory views of a conventional example. FIG. 8 shows a block diagram of a gate array with built-in RAM according to a conventional example. For example, a gate array with built-in RAM, which is an example of the device under test 16 having a test circuit having a test assisting function, has a plurality of RAM macros 1, a gate array 2, a test input buffer 3A, and a test output buffer 3B in FIG. , A test clock input buffer 4, a test mode input buffer 5, a normal input buffer 6A, a normal output buffer 6B, and their input / output terminals.

Note that the test input buffer 3A, the test output buffer 3B, the test clock input buffer 4 and the test mode input buffer 5 are used only for the functional test of the entire chip.
Since it is difficult to test all the memory cells of the RAM macro 1, this test circuit is provided to assist the LSI tester that tests the RAM built-in gate array. As a result, the RAM macro 1 can be separated from the peripheral logic circuit and the access time of the RAM can be measured independently.

The internal structure of one RAM macro 1 is R connected to the input register 1C as shown in FIG.
AM 1A, test switching circuit 1B connected to normal input port Pin, test input wiring Lin, etc., and switching circuit 1
It consists of an input register 1C connected between B and RAM 1A.

For example, in the case of measuring the access time of the RAM of the RAM macro 1 and the like, in FIG. 9, first, the test switching circuit 1B via the test mode input buffer 5 is used.
Is supplied with the test mode signal T / A, and it is set to the "H" level to put the RAM macro 1 in the test mode. As a result, the test switching circuit 1B disconnects the normal input port Pin and selects the test input wiring Lin side.

Here, the test clock signal TCK is supplied to the input register 1C via the test clock wiring Lt connected to the test clock input buffer 4, and also via the test input wiring Lin connected to the test input buffer 3A. Necessary test data DIN such as address and data are given to the input register 1C. As a result, the test output data DOUT can be obtained from the test output buffer 3B connected to the normal output port Pout as in the case of a general single unit RAM.

During normal use, the test mode signal T / A = "L" level is supplied to the test switching circuit 1B to put the RAM macro 1 in the normal mode. This allows
The test switching circuit 1B disconnects the test input wiring Lin side and selects the normal input port Pin.

As a result, when the RAM macro 1 is connected to the gate array 2 and the input data is input to the predetermined input port PIN, the output data processed by the gate array 2 is output from the predetermined output port POUT. .

[0014]

By the way, the conventional R
According to the gate array with built-in AM, a plurality of RAM macros 1
A test input buffer 3A and a test clock input buffer 4 are provided in common, and the test data DIN and the test clock signal TCK are transmitted between the RAM macros 1 through the test input wiring Lin and the test clock wiring Lt. It

If the test input buffer 3A and the test clock input buffer 4 are individually provided to the RAM macro 1, a huge number of test input terminals are required, so that the number of normal input or output terminals is reduced. I have no choice but to do it. Therefore, one set of test input wiring Lin and test clock wiring L
A large number of RAM macros 1 are connected to t to reduce the number of test input terminals.

However, when the test input wiring Lin, the test clock wiring Lt, and the test output wiring Lout are laid inside the chip for a long time, the test input buffer 3A and the test clock input buffer 4 are viewed from the input register 1C of the RAM macro 1. When the test output buffer 3B is viewed from the normal output port Pout, a very large input wiring capacitance, output wiring capacitance and stray capacitance are parasitic there.

Further, according to the conventional method of measuring the access time of the RAM macro 1, the test clock buffer TBC is input to the test clock input terminal to which the test clock input buffer 4 is connected, and then the test output buffer 3B is input. This is performed by measuring the time difference between the output of the test output data DOUT to the test output terminal connected to.

Therefore, in addition to the delay time of the test input buffer 4 and the test output buffer 3B, the test data DIN, the test clock signal TCK, and the test output by the test clock wiring Lt and the test output wiring Lout which are laid long inside the chip are provided. The delay time of the data DOUT will interfere with the true access time of the RAM macro 1. Therefore, if the semiconductor integrated circuit device is highly functionalized and has high performance, the delay time cannot be neglected when the true evaluation is attempted with respect to the access time of the RAM 1A, which is further increased in speed. .

As a result, as the semiconductor integrated circuit device becomes highly integrated and highly densified, the delay time becomes much larger than the access time of the RAM 1A, making it difficult to measure the accurate access time. Become. Further, there is a problem that a true evaluation cannot be performed by the measuring method as in the conventional example.

The present invention was created in view of the problems of the conventional example, and adds a new test auxiliary circuit to an object to be tested to transmit test input / output data and a test clock signal. / A semiconductor integrated circuit device capable of measuring the true access time by removing the influence of the delay of the output wiring, the test clock wiring, and the test input / output buffer, and improving the accuracy of the device, The purpose is to provide a test device and a test method thereof.

[0021]

[Means for Solving the Problems] FIGS. 1 (a) and 1 (b) are
2 is a principle diagram of a semiconductor integrated circuit device according to the present invention, and FIG.
2A and 2B respectively show principle diagrams of a semiconductor integrated circuit device test apparatus and a test method therefor according to the present invention.

The semiconductor integrated circuit device of the present invention is shown in FIG.
As shown in (a), in the semiconductor integrated circuit device in which the test circuit 11A for assisting the test of the internal integrated circuit 11 operating based on the clock signal is incorporated, the test clock signal TCK is provided separately from the test circuit 11A. The dummy test circuit 12 for performing the dummy process is provided.

In the semiconductor integrated circuit device of the present invention, the dummy test circuit 12 has a test auxiliary clock input means 12A for inputting a test auxiliary clock signal RCK and the test auxiliary as shown in FIG. 1B. Dummy holding means 12B for holding the test clock signal TCK based on the clock signal RCK and test data holding means 12C for holding the test output data DOUT based on the test auxiliary clock signal RCK.
And a dummy output means 12D for outputting the test clock signal TCK held by the dummy holding means 12B as a dummy output signal DTCK.

Further, in the semiconductor integrated circuit device of the present invention, the dummy holding means 12B and the test data holding means 12C are provided.
Are composed of the same circuit, and the internal integrated circuit 11 and the dummy holding means 12B are arranged close to each other.

Further, the semiconductor integrated circuit device testing device of the present invention is a device for testing the semiconductor integrated circuit device of the present invention, and as shown in FIG.
Non-test / test mode signal T / A, test clock signal TC
K, test data DIN, and test signal output means 13 for outputting the test auxiliary clock signal RCK, and the dummy output signal D
The test signal input means 14 for inputting the TCK and the test output data DOUT and the control means 15 for controlling the input / output of the test signal output means 13 and the test signal input means 14 are provided, and the control means 15 is under test. Dummy output signal DTC returned from the dummy test circuit 12 provided in the target 16
The present invention is characterized in that the delay time of the internal integrated circuit 11 is controlled based on K.

The semiconductor integrated circuit device testing method of the present invention is a method of testing the semiconductor integrated circuit device of the present invention, in which the non-test / test mode signal T / A, test The clock signal TCK, the test data DIN, and the test auxiliary clock signal RCK are supplied, the dummy output signal DTCK and the test output data DOUT are acquired, and are provided separately from the test circuit 11A of the device under test 16. It is characterized in that the delay time of the internal integrated circuit 11 is calculated based on the dummy output signal DTCK fed back from the dummy test circuit 12.

In the method of testing a semiconductor integrated circuit device according to the present invention, in the process of calculating the delay time of the internal integrated circuit 11, the expected value of the device under test 16 is compared with the test output data DOUT. Under the condition, the time difference between the test clock signal TCK and the test auxiliary clock signal RCK is reduced,
Acquisition processing of the first time difference data D1 relating to the limit at which the test output data DOUT matches the expected value of the DUT 16 is performed, and the expected value of the DUT 16 is compared with the dummy output signal DTCK. Under the condition, the time difference between the test clock signal TCK and the test auxiliary clock signal RCK is reduced, and the second time difference data D2 relating to the limit at which the dummy output signal DTCK matches the expected value of the DUT 16 is acquired. The difference between the first and second time difference data D1 and D2 is calculated, and the above object is achieved.

[0028]

[Operation] According to the semiconductor integrated circuit device of the present invention, FIG.
As shown in (a), in the semiconductor integrated circuit device in which the test circuit 11A is incorporated, a dummy test circuit 12 for performing dummy processing of the test clock signal TCK is provided separately from the test circuit 11A.

Therefore, in the case of testing the internal integrated circuit 11 including the memory circuit M, the test circuit 11A is commonly provided for a plurality of memory circuit elements M as in the conventional example, and the test is performed. Even when the clock wiring and the test output wiring are laid long inside the chip, it is possible to provide the dummy information regarding the delay time and the like from the dummy test circuit 12 to an external test device or the like.

As a result, the memory circuit M of the device under test 16 is
The true access time can be measured, and the reliability of performance evaluation of the device can be improved. Further, according to the semiconductor integrated circuit device testing apparatus of the present invention,
As shown in FIG. 2, a test signal output means 13, a test signal input means 14 and a control means 15 are provided.
5, the access time TAA of the memory circuit M is value-controlled based on the dummy output signal DTCK fed back from the dummy test circuit 12 of the device under test 16 and the test auxiliary clock signal RCK.

For example, when the access time of the memory circuit M of the device under test 16 is measured, the test circuit
The test object 16 in which 11A is incorporated includes a non-test / test mode signal T / A, a test clock signal TCK, and test data D.
IN and the test auxiliary clock signal RCK are test signal output means 1
3 is output to the test circuit 11A and the dummy test circuit 12.

At this time, as shown in FIG. 1B, when the test auxiliary clock signal RCK is input to the test auxiliary clock input means 12A of the dummy test circuit 12, the test auxiliary clock signal RCK is tested based on the test auxiliary clock signal RCK. The clock signal TCK is held by the dummy holding means 12B, and similarly, the test output data DOUT is held in the test data holding means 12C based on the test auxiliary clock signal RCK.

Further, the test clock signal TCK fed back from the device under test 16, that is, the dummy output signal DTCK and the test output data DOUT are input to the control means 15 via the test signal input means 14. At this time, the dummy holding means
Dummy output signal DTCK through 12B and data output means 12C
And test output data DOUT are output from the dummy output means 12D and the test circuit 11A.

As a result, the control means 15 first compares the test output data DOUT with its expected value, and if they match, the test clock signal TCK and the test auxiliary clock RCK under the condition of path (Pass). The apparent access time of the memory circuit M is measured by reducing the time difference of Ps and obtaining the limit time difference of Pass.

Next, the dummy output signal DTCK is compared with its expected value, and if they match, the time difference between the dummy output signal DTCK and the test auxiliary clock RCK is reduced under the condition of "pass" (Pass), and Pass is reduced. By obtaining the time difference of the limit, the dummy information regarding the delay time and the like intervening in the apparent access time of the memory circuit M is acquired. Thereby, the time difference data D1, relating to the two states,
The access time TAA of the memory circuit M is calculated based on D2 (TRAM, TREG).

Therefore, as in the conventional example, the test circuit 11A is commonly provided for the plurality of memory circuits M, and the test clock wiring and the test output wiring are laid long inside the chip. Also, it is possible to eliminate the influence of the delay time and the like related to the test clock wiring and the test output wiring based on the dummy information.

As a result, the non-test / test mode signal A /
It becomes possible to disconnect only the memory circuit M from the internal integrated circuit 11 based on T etc. and accurately measure the access time via the test circuit 11A. Further, it is possible to improve the test accuracy of the device.

Further, according to the test method of the semiconductor integrated circuit device of the present invention, the access time TAA of the memory circuit M is controlled by using the dummy test circuit 12 provided separately from the test circuit 11A of the device under test 16. Value calculation is performed.

For example, if the test output data DOUT is compared with its expected value and they match, the time difference between the test clock signal TCK and the test auxiliary clock RCK is reduced under the condition of path (Pass), and the time difference is reduced. The first time difference data D1 (TR
AM) is acquired and compared with the dummy output signal DTCK and its expected value, and if they match, the path (Pass
), The time difference between the dummy output signal DTCK and the test auxiliary clock RCK is reduced, and the second time difference data D2 (TREG) obtained when the time difference is reduced to the limit of Pass is acquired.

Therefore, in step P3C, the difference between the first and second time difference data D1 and D2 is calculated, so that the test circuit 11A is shared by the plurality of memory circuits M as in the conventional example. Even if the test clock wiring and test output wiring run around the inside of the chip for a long time,
Based on the dummy information, it is possible to remove the influence of the delay time related to the test clock wiring and the test output wiring,
It becomes possible to measure the true access time TAA of the memory circuit M.

As a result, by measuring the highly accurate access time TAA in consideration of these delay times, the true speed of the memory circuit M is further increased as the function and performance of the semiconductor integrated circuit device are improved. It becomes possible to evaluate.

[0042]

Embodiments of the present invention will now be described with reference to the drawings. 3 to 8 are views for explaining a semiconductor integrated circuit device according to an embodiment of the present invention, a test apparatus therefor and a test method therefor, and FIG. 3 is a configuration diagram of the semiconductor integrated circuit device according to the embodiment of the present invention. Is shown. FIG. 4 is an internal block diagram of the RAM macro.

For example, a gate array 26 with a built-in RAM, which is an example of a semiconductor integrated circuit device, is shown in FIG.
AM macros M1 to Mn, gate array 21, register clock input 22A, dummy output buffer 22D, test input buffer 101, test output buffer 102, test clock input buffer 103, test mode input buffer 104, normal input buffer 26A, normal output buffer 26B and various input / output terminals T1 to T5.

That is, n RAM macros M1 to Mn
Is a memory for temporarily storing various logically processed data in the gate array 21 and resultant data. One R
The internal structure of the AM macro M1 will be described in detail with reference to FIG.

The gate array 21 is composed of logical gate circuits such as logical product and logical sum, and is connected to the normal input buffer 26A, the normal output buffer 26B and the normal input port Pin and the normal output port Pout of the n RAM macros M1 to Mn. To be done.

The register clock input 22A is an embodiment of the test auxiliary clock input means 12A and constitutes a part of the dummy test circuit 12. Also, register clock input 22
A is a test input buffer 101, a test clock input buffer
Separately from 103 and the test mode input buffer 104, a register clock which is an example of the test auxiliary clock signal RCK related to the dummy processing of the test clock signal TCK is input. Further, the input portion of the register clock input 22A is connected to the register clock input terminal T1 and the output portion thereof is connected to the register clock wiring Lin2, and n RAMs are connected.
It reaches the dummy register 22B and the data output register 22C of the macros M1 to Mn.

The dummy output buffer 22D is a dummy output means.
This is an example of 12D and constitutes a part of the example of the dummy test circuit 12. The dummy output buffer 22D outputs a dummy output signal DTCK separately from the test output buffer 102. The input part of the dummy output buffer 22D is connected to the output part of the dummy register 22B, and the output part is connected to the test clock output terminal T5.

Test input buffer 101, test output buffer
Reference numeral 102, test clock input buffer 103 and test mode input buffer 104 constitute one embodiment of the test circuit 11A and are circuits for separating the RAM macros M1 to Mn from the gate array 21 and assisting the test. The test input buffer 101 is for inputting the test data DIN, and is connected to the test input terminal T2 and the test input wiring Lin1 and connected to each RA.
The test switching circuit 21B for the M macro Mn is reached.

The test output buffer 102 outputs the test output data DOUT and is connected to the test output terminal T6 and the test output wiring Lout and reaches the data output register 22C of each RAM macro Mn. The test clock input buffer 103 inputs the test clock signal TCK, and is connected to the test clock input terminal T3 and the test clock line Lt.
Test switching circuit 21 for each RAM macro Mn connected to
B and the dummy register 22B.

The test mode input buffer 104 is not tested /
The test mode signal T / A is input, and the test switching circuit 21 of the mode input terminal T4 and each RAM macro Mn is input.
Connected to B. The normal input buffer 26A and the normal output buffer 26B are the gate array 21 and the predetermined input port P.
It is connected to IN and a predetermined output port POUT, and inputs and outputs various data during normal use.

The internal structure of one RAM macro M1 is, as shown in FIG. 4, a RAM 21A and a test switching circuit 21.
B, input register 21C, dummy register 22B and data output register 22C.

That is, the RAM 21A is an embodiment of the memory circuit M, and temporarily stores the test data DIN and the normal data at the time of the test or the normal use. The test switching circuit 21B switches the input source of the input register 21C based on the non-test / test mode signal T / A. For example, the normal input port Pin is connected to the input register 21C during non-test, that is, in normal use, and the test clock line Lt and the test input line Lin1 are connected to the input register 21C during test. The input register 21C holds the test data DIN based on the test clock signal TCK during the test. RAM21A, test switching circuit 21
B and the input register 21C are an embodiment of the internal integrated circuit 11.

The dummy register 22B is a dummy holding means 12B.
This is an embodiment of the present invention and constitutes a dummy test circuit 12.
The dummy register 22B holds the test clock signal TCK based on the register clock RCK. The data output register 22C is an embodiment of the test data holding means 12C and constitutes the dummy test circuit 12. Also,
The data output register 22C holds the test output data DOUT based on the register clock RCK.

The dummy register 22B and the data output register 22C are composed of the same circuit, and the test switching circuit 21
B, input register 21C, RAM 21A, dummy register 22
B and the data output register 22C are arranged close to each other.

This is to suppress the time difference between the register clocks reaching the dummy register 22B and the data output register 22C and the time difference between the test clock signals TCK reaching the input register 21C and the dummy register 22B to a negligible level.

Thus, R according to the embodiment of the present invention
According to the AM-incorporated gate array, as shown in FIGS. 3 and 5, a built-in RAM in which a test circuit 11A such as a test input buffer 101, a test output buffer 102, a test clock input buffer 103, and a test mode input buffer 104 is incorporated. In the gate array, in addition to the test circuit 11A, a register clock input 22A, a dummy register 22B, and a data output register 22 for performing dummy processing of the test clock signal TCK are provided.
A dummy test circuit 12 including C and a dummy output buffer 22D is provided.

Therefore, the RAM macros M1 to Mn are separated from the gate array 21, and the access time TA
When measuring A, a plurality of RAs as in the conventional example
Test output buffer 10 for each of M macros M1 to Mn
2 is provided, the test clock input buffer 103 is provided in common, and even when the test clock wiring Lt and the test data output wiring are laid long inside the chip, dummy information regarding the delay time and the like is provided. The dummy buffer can be provided to an external test device or the like.

That is, when looking at the test clock input buffer 103, the test output buffer 102, etc. from a certain RAM macro Mn, the parasitic input wiring capacitance, the delay time due to the output wiring capacitance and the stray capacitance, the delay of the input / output buffer, etc. Also, dummy information corresponding to the setup time of the input register 21C and the like can be output from the dummy register 22B to the outside.

As a result, the gate array 21 is connected to the RAM.
It is possible to separate the macros M1 to Mn and measure their true access time TAA.
It is possible to improve the reliability of the performance evaluation of.

During normal use, the test switching circuit 21B is supplied with the non-test / test mode signal T / A = "L" level to put the RAM macro M1 in the normal mode. As a result, the test switching circuit 21B causes the test input wiring Lin1
The side is separated and the normal input port Pin is selected. At this time, when the RAM macros M1 to Mn are connected to the gate array 26 and the input data is input to the predetermined input port PIN, the output data processed by the gate array 26 is output from the predetermined output port POUT. .

Next, a semiconductor integrated circuit device testing apparatus according to an embodiment of the present invention will be described, supplementing the operation of the dummy testing circuit of the RAM built-in gate array 26.

FIG. 5 is a block diagram of a test system device for a gate array with built-in RAM according to an embodiment of the present invention. For example, in addition to the test circuit 11A, a dummy test circuit 12 for performing a dummy process of the test clock signal TCK is provided R
RA from the gate array 21 of the gate array 26 with built-in AM
The device for separating the M macros M1 to Mn and measuring the access time TAA thereof comprises a test signal output unit 23, a test signal input unit 24 and a data control device 25 in FIG.

That is, the test signal output section 23 is one embodiment of the test signal output means 13, and the non-test / test mode signal T / A, the test clock signal TCK, the test data DIN and the register clock RCK are contained in the RAM built-in gate array. It outputs to 26. For example, the test signal output unit 23 is R
Register clock input terminal T1, test input terminal T2, test clock input terminal T3 of the gate array 26 with built-in AM
It is connected to the test mode terminal T4.

The test signal input section 24 is the test signal input means 1
4 is an embodiment of the present invention, which is a dummy output signal DTCK and test output data DOU fed back from the RAM built-in gate array 26.
You type T. For example, the test signal input unit 24
Is connected to the dummy output signal output terminal T5 and the test output terminal T6 of the RAM built-in gate array 26.

The data control device 25 is an embodiment of the control means 15, and includes a test signal output section 23 and a test signal input section 2
4 controls the input / output of the signal. For example, the data control device 25 has a signal generator 25 connected to the data bus 25F.
A, expected value comparison unit 25B, memory unit 25C, other processing unit
25D and CPU (Central Processing Unit) 25E.

The signal generator 25A generates the non-test / test mode signal T / A, the test clock signal TCK, the test data DIN and the register clock RCK, and the expected value comparator 25B outputs the dummy output signal DTCK and its expectation. Value, that is, the test data D is compared with the test clock signal TCK.
The test output data DOUT related to IN is compared with the expected value data which is the evaluation standard.

The memory section 25C stores the test output data DOUT, expected value data, etc., and the access time T of the apparent RAM macro Mn including the delay time of the test circuit 11A.
The first and second time difference data D1 relating to the apparent setup time TREG of the RAM and the dummy register 22B.
Memorize D2 and the like.

The other processing unit 25D assists the input / output of the CPU 25E, and the CPU 25E is a signal generating unit 25A,
Expected value comparison unit 25B, memory unit 25C and other processing unit 25
It controls the input / output of D. For example, CPU25E
Is the test output data D returned from the test output buffer 102.
The value of the access time TAA of the RAM macro Mn is controlled based on the first and second time difference data D1 and D2 relating to the two states of the dummy output signal DTCK fed back from the OUT or the dummy test circuit 12.

Thus, R according to the embodiment of the present invention
As shown in FIG. 5, the test apparatus for the AM built-in gate array includes a test signal output section 23, a test signal input section 24, and a data control apparatus 25.
Thus, the access time TAA of the RAM macro Mn is controlled to be a value.

For example, R of the gate array 26 with built-in RAM
When measuring the access time of the AM macro M1, the non-test / test mode signal T / A, the test clock signal TCK, the test data DIN and the register are added to the RAM built-in gate array 26 in which the test circuit 11A is incorporated. The clock RCK is output from the test signal output unit 23 to the test circuit 11A and the dummy test circuit 12.

At this time, as shown in FIG. 4, when the register clock RCK is input to the register clock input 22A of the dummy test circuit 12, the test clock signal TCK is held by the dummy register 22B based on the register clock RCK. The test output data DOUT is held in the data output register 22C based on the test auxiliary clock signal RCK.

Further, the dummy output signal DTCK and the test output data DOUT fed back from the RAM built-in gate array 26 are input to the data control device 25 via the test signal input section 24. At this time, the test clock signal TCK passed through the dummy register 22B, that is, the dummy output signal DTCK and the test output data DOUT passed through the data output register 22C are output from the dummy output buffer 22D and the test output buffer 102.

Further, in the data control device 25, first,
The apparent access time of the RAM macro Mn including the delay time is measured based on the test output data DOUT. Next, the dummy output signal DTCK fed back from the test circuit 12
Based on the above, the dummy information relating to the delay time and the like intervening in the apparent access time of the RAM macro Mn is acquired. As a result, the time differences TRAM, T related to the two states are
Access time T of RAM macro Mn based on REG
AA is calculated.

Therefore, as in the conventional example, the test circuit 11A is commonly provided for the plurality of RAM macros M1 to Mn, and the test input wiring Lin1, the test clock wiring Lt, and the test data output wiring are provided inside the chip. Even if it is routed for a long time, it is possible to remove the influence of the delay time or the like related to the test clock wiring Lt or the like based on the dummy information.

As a result, the non-test / test mode signal A /
From the gate array 26 to the RAM macro M1 based on T etc.
It becomes possible to accurately separate the access time TAA through the test circuit 11A by disconnecting only .about.Mn. Further, it is possible to improve the test accuracy of the device.

Next, a method of testing the semiconductor integrated circuit device according to the embodiment of the present invention will be described, supplementing the operation of the test device. FIG. 6 shows an R according to an embodiment of the present invention.
FIG. 7 is a test flowchart of the AM-incorporated gate array, and FIG. 7 is a limit timing chart supplementing the test flowchart.

For example, the true access time T of the RAM macro M1 of the RAM built-in gate array (hereinafter referred to as the gate array under test) 26 provided with the dummy test circuit 12 is provided.
When measuring AA, first, in FIG.
At 0, the gate array under test 26 and the test system device are connected. At this time, the register clock input terminal T1, the test input terminal T2, the test clock input terminal T3, and the test mode terminal T4 of the gate array under test 26 are connected to the test signal output section 23, and the test clock output terminal T5 and the test output thereof are connected. The terminal T6 is connected to the test signal input section 24.

Next, the apparent access time TRAM of the RAM macro M1 seen from the outside in steps P1 to P4.
To measure. The apparent access time TRAM
Input / output buffer delay time, input register 21B
Setup time, the true access time TAA of the RAM 21A, and the delay time associated with each wiring capacitance. The true access time TAA means the time from the input of the test clock signal TCK to the RAM macro Mn to the output of the read data (test output data DOUT) to the normal output port Pout.

That is, in step P1, the mode signal T /
Select A. At this time, the test circuit 11 of the gate array under test 26 is tested by the test signal output section 23 of the test system device.
Signals T / A, TCK, DI to A and the dummy test circuit 12
N and RCK are output. For example, the non-test / test mode signal T / A is set to the “H” level, and the RAM macros M1 to M are
Put n in test mode. This allows the test switching circuit
21B disconnects the normal input port Pin and selects the test input wiring Lin1 side.

Next, in step P2, the non-test / test mode signal T / A, the test clock signal TCK, the test data DIN and the register clock RCK are supplied to the gate array under test 26.

Then, in step P3, the dummy output signal DTCK and test output data DOUT which are fed back from the gate array under test 26 are acquired. Here, as shown in FIG. 7A, when the test clock signal TCK is based on the input time t10 of the test clock input terminal T1, the input register 21 is input at the time t11 after the delay time TC due to the input wiring capacitance or the like.
Reach B. In synchronization with the rise of this test clock signal TCK, it takes a true access time TAA
21A operates, and the test output data DOUT is read at time t13.

On the other hand, assuming that the register clock RCK is input to the register clock input terminal T1 at time t12, the time t after the delay time TR depends on the input wiring capacity and the like.
At 14, the data output register 22C is reached. Here, the setup time TS is required for the data output register 22C to fetch the test data DOUT.

After that, in step P4, the time difference between the test clock signal TCK and the register clock TCK is reduced, and the test output data DOUT and the expected value data serving as its evaluation reference are calculated by the expected value comparison unit 25B of the data control device 25. When they are compared and the expected value is reached, the time difference reduction is stopped and the limit timing is obtained.

Here, as shown in FIG. 7A, the RAM
The apparent access time TRAM of 21A is the time difference between the test clock signal TCK and the register clock RCK seen at the test clock input terminal T3 and the register clock input terminal T1. Also, the delay time TC,
True access time TAA, setup time TS of data output register 22C, apparent access time T
There is a relationship as shown in equation (1) between the RAM and the delay time TR due to the input wiring capacitance and the like.

TC + TAA + TS = TRAM + TR (1) Note that the apparent access time TRAM of the RAM 21A according to the equation (1) is obtained as the first time difference data D1.

Next, in step P5, the test clock signal T
The storage process of the first time difference data D1 in which the time difference between CK and the register clock RCK is minimized is performed. Where the first
The time difference data D1 of is the TRAM data according to the equation (1), which is, for example, the memory unit 25C of the test system device.
Is temporarily stored in.

After that, the apparent setup time TR of the dummy register 22B seen from the outside in steps P6 to 8 is set.
Measure EG. That is, in step P6, the test clock signal TCK and the register clock RCK are output from the test signal output unit 23 of the test system device to the gate array 2 under test.
6 to the test circuit 11A and the dummy test circuit 12.

Then, in step P7, the dummy output signal DTCK fed back from the gate array under test 26 is acquired. Here, as shown in FIG. 7B, the test clock signal TCK is input at the input time t of the test clock input terminal T1.
If 20 is used as a reference, the delay time TC
The dummy register 22B is reached at a later time t22. on the other hand,
Assuming that the register clock RCK is input to the register clock input terminal T1 at time t21, the dummy register is set at time t23 after the delay time TR due to the input wiring capacity and the like.
Reach 22B. Here, the setup time T5 is required for the dummy register 22BK to take in the test clock signal CK while considering the input data.

Then, in step P8, the time difference between the test clock signal TCK and the register clock RCK is reduced.
At this time, the expected value comparison unit 25B of the data control device 25 compares the test clock signal TCK at the time of output, that is, the dummy output signal DTCK with the test clock signal TCK at the time of input, which is the expected value. When the expected value is reached, the time difference reduction is stopped and the limit timing is obtained.

Here, as shown in FIG. 7B, the apparent setup time TREG of the dummy register 22B is the test clock signal TCK and the register clock R seen at the test clock input terminal T1 and the register clock input terminal T1.
It is the time difference from CK. Also, the delay time TC, the true setup time TS of the dummy register 22B, the apparent setup time TREG of the dummy register 22B, and the delay time TR due to the input wiring capacitance, etc.
There is a relationship as shown in equation (2) between and.

TC + TS = TREG + TR (2) Since the dummy register 22B and the data output register 22C are provided so that their shapes and arrangement conditions are close to each other, their setup times TS are almost the same. Further, the apparent setup time TREG of the dummy register 22B according to the equation (2) is obtained as the second time difference data D2 which is an example of the dummy information.

Next, in step P9, the true access time TAA is calculated based on the first and second time difference data D1 and D2.
Is calculated. At this time, for example, the CPU 25E of the test system device calculates the difference between the equations (1) and (2), and erases the delay times TC and TR and the setup time TS that are unknowns that cannot be measured directly from the outside. , The true access time TAA is calculated as shown in equation (3).

TAA = TRAM-TREG (3) Then, in step P10, the test evaluation of the gate array under test 26 is performed. Thus, the true access time TAA of the RAM macro M1 of the RAM built-in gate array 26 provided with the dummy test circuit 12 can be evaluated.

Thus, R according to the embodiment of the present invention
According to the method of testing the gate array with built-in AM, as shown in FIG. 6, the first and second time difference data D1 and D2 are acquired in steps P4 and P8.

Therefore, in step P9, the difference between the apparent access time TRAM of the RAM 21A and the apparent setup time TREG of the dummy register 22B is calculated based on the first and second time difference data D1 and D2. Thus, a plurality of RAM macros M1 as in the conventional example
Even if the test circuit 11A is commonly provided for Mn to Mn, and the test input line Lin1, the test clock line Lt, and the test data output line are laid around the inside of the chip for a long time, RAM macros M1 to Mn can be removed by eliminating the influence of test input / output wiring, test clock wiring, delay time related to input / output buffer, and the like.
It is possible to measure the true access time TAA of

As a result, even if the delay time becomes much longer than the true access time of the RAM 21A due to the higher integration and higher density of the semiconductor integrated circuit device, the apparent RAM macro Mn access time TR
Since the dummy information TREG such as the delay time of the test clock signal TCK is subtracted from AM, the accurate access time TAA can be measured.

As a result, by measuring the access time TAA with high precision in consideration of these delay times, the RAM macros M1 to Mn are further accelerated as the function and performance of the semiconductor integrated circuit device are improved. It is possible to make a true evaluation of.

In the embodiment of the present invention, the method of measuring the access time TAA with reference to the rising edge of the clock signal has been described, but the same effect can be obtained when the access time TAA is measured with reference to the falling edge. To be Further, in the embodiment of the present invention, the case where the test object 16 is the RAM macro built-in gate array has been described, but it may be a standard cell or a microprocessor, and the macro is a ROM.
The same effect can be obtained with a (read-only memory) or a logic circuit.

[0099]

As described above, according to the semiconductor integrated circuit device of the present invention, the dummy test circuit for performing the dummy processing of the test clock signal is provided separately from the test circuit.

Therefore, as in the conventional example, a test circuit is commonly provided for a plurality of memory circuits, and the test input / output wiring and the test clock wiring are laid long inside the chip. Also, it becomes possible to provide the dummy information regarding the delay time and the like from the dummy test circuit to an external test device or the like.

Further, according to the semiconductor integrated circuit device testing apparatus of the present invention, the test signal output means, the test signal input means and the control means are provided, and the control means allows the apparent access time of the memory circuit (first Data) and the apparent setup time of the dummy holding means (second time difference data) are acquired.

Therefore, it is possible to separate only the memory circuit from the internal integrated circuit of the semiconductor integrated circuit device and obtain the true access time of the memory circuit based on two apparent access times and setup times.
It is possible to improve the test accuracy of the device.

Further, according to the test method of the semiconductor integrated circuit device of the present invention, the first and second time difference data are acquired by using the dummy test circuit provided separately from the test circuit to be tested. Then, the access time of the storage circuit is calculated based on the value.

Therefore, the setup time of the test output register, the input wiring, and the delay element of the input buffer are erased by calculating the difference between the first and second time difference data that can be measured directly from the external terminal. Therefore, the true access time of the memory circuit can be accurately measured. As a result, a highly accurate access time can be measured in consideration of the delay time of the test circuit of the memory circuit built in the semiconductor integrated circuit device, and true RAM evaluation or the like can be performed.

As a result, it becomes possible to improve the reliability of the performance evaluation of the gate array, the standard cell, etc. having the built-in semiconductor memory circuit, which contributes to the provision of a highly reliable semiconductor integrated circuit device and its testing device. However, it is big.

[Brief description of drawings]

FIG. 1 is a principle diagram of a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a principle diagram of a semiconductor integrated circuit device test apparatus and a test method therefor according to the present invention.

FIG. 3 is an overall configuration diagram of a RAM macro built-in gate array according to an embodiment of the present invention.

FIG. 4 is an internal configuration diagram of a RAM macro according to an embodiment of the present invention.

FIG. 5 is a configuration diagram of a test system device for a RAM macro built-in gate array according to an embodiment of the present invention.

FIG. 6 is a test flowchart of a RAM macro built-in gate array according to an embodiment of the present invention.

FIG. 7 is a limit timing chart supplementing the test flow chart according to the embodiment of the present invention.

FIG. 8 is an overall configuration diagram of a RAM macro built-in gate array according to a conventional example.

FIG. 9 is an explanatory diagram of a method of testing a RAM macro according to a conventional example.

[Explanation of symbols]

 11 ... Internal integrated circuit, 11A ... Test circuit, 12 ... Dummy test circuit, 12A ... Test auxiliary clock input means, 12B ... Dummy holding means, 12C ... Test data holding means, 12D ... Dummy output means, 13 ... Test signal Output means, 14 ... Test signal input means, 15 ... Control means, M ... Memory circuit, TCK ... Test clock signal, DTCK ... Dummy output signal, RCK ... Test auxiliary clock signal, DIN ... Test data, DOUT ... Test output data, T / A ... Non-test / test mode signal, TAA ... True access time, D1 ... First time difference data (TRAM), D2 ... Second time difference data (TREG).

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location G11C 29/00 303 H 6741-5L H01L 21/66 W 7377-4M 21/82 8225-4M H01L 21 / 82 T

Claims (6)

[Claims] 1. A semiconductor integrated circuit device incorporating a test circuit (11A) for assisting the test of an internal integrated circuit (11) which operates based on a clock signal, the test being performed separately from the test circuit (11A). A semiconductor integrated circuit device comprising a dummy test circuit (12) for performing dummy processing of a clock signal (TCK). 2. The semiconductor integrated circuit device according to claim 1, wherein the dummy test circuit (12) inputs a test auxiliary clock input means (12A) for inputting a test auxiliary clock signal (RCK), and the test auxiliary clock signal. Dummy holding means (12B) for holding the test clock signal (TCK) based on (RCK) and test data holding means (12C) for holding the test output data (DOUT) based on the test auxiliary clock signal (RCK). And a dummy output means (12D) for outputting the test clock signal (TCK) held by the dummy holding means (12B) as a dummy output signal (DTCK). 3. The semiconductor integrated circuit device according to claim 1, wherein the dummy holding means (12B) and the test data holding means (12C) are made of the same circuit, and the internal integrated circuit (11) and the dummy holding means (12). 12B) is arranged in close proximity to the semiconductor integrated circuit device. 4. A device for testing the semiconductor integrated circuit device according to claim 1, wherein said device under test (16) has a non-test / test mode signal (T / A) and a test clock signal (T).
CK), test data (DIN) and test auxiliary clock signal (RCK), and a dummy output signal (DTCK) and test output data (DOUT).
) Is inputted, and a control means (15) for controlling input / output of the test signal output means (13) and the test signal input means (14) is provided, and the control means (15) ) Controls the delay time of the internal integrated circuit (11) based on the dummy output signal (DTCK) fed back from the dummy test circuit (12) provided in the device under test (16). And a semiconductor integrated circuit device testing device. 5. A method for testing a semiconductor integrated circuit device according to claim 1, wherein said device under test (16) has a non-test / test mode signal (T / A) and a test clock signal (T).
CK), test data (DIN) and test auxiliary clock signal (RCK) are supplied, and the dummy output signal (DTCK) is supplied.
) And test output data (DOUT) are acquired, and a dummy output signal (DTCK) is fed back from a dummy test circuit (12) provided separately from the test circuit (11A) of the device under test (16). A method of testing a semiconductor integrated circuit device, which comprises performing a delay time value calculation process of an internal integrated circuit (11) based on the above. 6. The method for testing a semiconductor integrated circuit device according to claim 5, wherein the delay time value calculation process of the internal integrated circuit (11) is performed by using an expected value and a test output of the device under test (16). Under the condition of comparing the data (DOUT), the test clock signal (TCK) and the test auxiliary clock signal (RC
The time difference from the test output data (DOUT
) Performs the acquisition process of the first time difference data (D1) related to the limit in which the test object (16) matches the expected value, and
The expected value of the device under test (16) and the dummy output signal (D
Under the condition of comparing with TCK), the time difference between the test clock signal (TCK) and the test auxiliary clock signal (RCK) is reduced so that the dummy output signal (DTCK) matches the expected value of the device under test (16). A test of a semiconductor integrated circuit device, characterized by performing a process of obtaining second time difference data (D2) relating to a limit of the operation, and a process of calculating a difference between the first and second time difference data (D1, D2). Method.