JP3264812B2 - Timing synchronization method for IC test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC tester for inspecting electrical characteristics of an IC device (integrated circuit).
In particular, when the cycle of the address differs from the cycle of the read data,
The present invention relates to a timing synchronization method of an IC test apparatus suitable for inspecting a C device.

[0002]

2. Description of the Related Art In order to ship an IC device whose performance and quality are guaranteed as a final product, all or a part of the IC device is extracted in each step of a manufacturing section and an inspection section, and the electrical characteristics are inspected. There is a need. An IC test device is a device for inspecting such electrical characteristics. The IC test apparatus gives predetermined test pattern data to the IC under test, reads the output data of the IC under test, and determines whether there is any problem in the basic operation and function of the IC under test. The failure information is analyzed from the data and the electrical characteristics are inspected.

[0003] DC tests (D
C measurement test) and a function test (FC measurement test). For DC test, D
By applying a predetermined voltage or current from the C measuring means, it is checked whether there is any defect in the basic operation of the IC to be measured. On the other hand, in the function test, predetermined test pattern data is given to the input terminal of the IC under test from the pattern generation means, and the output data of the IC under test is read, and there is no problem in the basic operation and function of the IC under test. It is to check whether or not. That is, the function test is performed by changing input conditions such as an input timing and an amplitude of each input signal of the IC under test such as an address, data, a write enable signal, and a chip select signal, and testing the output timing and the output amplitude thereof. Or something to do.

FIG. 2 is a block diagram showing a schematic configuration of a conventional IC test apparatus. The IC test apparatus is roughly divided into a tester unit 50 and an IC mounting device 70. Tester part 5
0 denotes control means 51, DC measurement means 52, timing generation means 53, pattern generation means 54, pin control means 55,
It comprises a pin electronics 56, a fail memory 57 and an input / output switching means 58. The tester unit 50 has various other components, but only necessary parts are shown in this specification.

The tester unit 50 and the IC mounting device 70 are connected by signal lines including a plurality (m) of coaxial cables or the like corresponding to the total number of input / output terminals (m) of the IC mounting device 70. The connection relationship between the terminal and the coaxial cable is associated with each other by a relay matrix (not shown), and transmission of various signals is performed between a predetermined terminal and the coaxial cable. Note that there are physically as many signal lines as the number m of all input / output terminals of the IC mounting device 70.

The IC mounting device 70 includes a plurality of ICs to be measured.
71 is configured to be mounted on a socket. The input / output terminal of the IC 71 to be measured and the input / output terminal of the IC mounting device 70 are connected in one-to-one correspondence. For example, if the IC 71 to be measured having 28 input / output terminals is 1
In the case of the IC mounting device 70 capable of mounting zero ICs, a total of 28
It has zero input / output terminals.

The control means 51 controls the entire IC test apparatus,
It performs operations and management, and has a microprocessor configuration. Therefore, although not shown, the control means 51 has a ROM for storing a system program, a RAM for storing various data, and the like. The control means 51
DC measuring means 52, timing generating means 53, pattern generating means 54, pin control means 55, and fail memory 5
7 is connected via a tester bus (data bus, address bus, control bus) 69.

[0008] The control means 51 transmits the data for the DC test to D
The C measuring means 52 supplies the timing data for starting the function test to the timing generating means 53, the program and various data necessary for generating the test pattern to the pattern generating means 54, the expected value data and the like to the pin control means 55,
Output each. In addition, the control means 51 outputs various data to each component via the tester bus 69. Further, the control means 51 includes a DC measurement means 52
The data (DC data or fail data) indicating the test result is read from the internal register, the fail memory 57, and the pass / fail (PASS / FAIL) register 65 in the pin control means 55, and the data is analyzed and analyzed.
The quality of C71 is determined.

The DC measuring means 52 receives the DC test data from the control means 51 and performs a DC test on the IC 71 to be measured of the IC mounting device 70 based on the data. DC
The measuring means 52 starts a DC test by inputting a measurement start signal from the control means 51, and writes data indicating the test result into an internal register. When the writing of the test result data is completed, the DC measuring means 52 outputs an end signal to the control means 51. The data written in the internal register is read by the control means 51 via the tester bus 69 and analyzed there. Thus, the DC test is performed. The DC measuring means 52 supplies reference voltages VIH, VIL, VOH, and VOL to the driver 64 of the pin electronics 56 and the analog comparator 65.

The timing generating means 53 includes a control means 51
Is stored in an internal memory, and a high-speed operation clock CLK is output to the pattern generating means 54 and the pin control means 55 based on the timing data, and the timing signal PH for writing and reading data is transmitted to the pin control means 55 and the fail signal. Output to the memory 57. Therefore, the operating speed of the pattern generating means 54 and the pin control means 55 is determined by the high-speed operation clock CLK, and the timing of writing and reading data to and from the IC 71 to be measured is determined by the timing signal PH. In addition, fail memory 5
7 is also determined by the timing signal PH. Accordingly, the output timings of the test signal P2 output from the formatter 60 to the pin electronics 56 and the switching signal P6 output from the I / O formatter 61 to the input / output switching unit 58 are also high-speed operation clocks CLK and CLK from the timing generation unit 53. It is controlled according to the timing signal PH. Further, the timing generation means 53 includes a pattern generation means 54.
The control signal CH for switching the timing is input, and the operation cycle, phase, and the like are appropriately switched based on the control signal CH.

The pattern generating means 54 receives data for pattern creation (microprogram or pattern data) from the control means 51 and outputs pattern data PD based on the data to the data selector 59 of the pin control means 55. That is, the pattern generation means 54 outputs a regular test pattern data by various arithmetic processes according to the microprogram method, and an internal memory (referred to as a pattern memory) which stores the same data as the data to be written in the IC under test. In advance, and read it out at the same address as the IC to be measured to obtain irregular (random) pattern data (expected value data).
It operates in a memory stored format that outputs In the programming method, the measured IC is RAM (Random Accesses)
s Memory) and other volatile memory tests,
The memory stored method is ROM (Read Only M)
memory) is supported. Note that, even in the case of the memory stored system, the generation of the address supplied to the IC to be measured is performed by the program system.

The pin control means 55 includes a data selector 59,
Formatter 60, I / O formatter 61, comparator logic circuit 62, and pass / fail (PASS /
FALI) register 63P. The data selector 59 is composed of a memory storing various test signal creation data (address data / write data) P1, switching signal creation data P5 and expected value data P4, and stores the pattern data from the pattern generation means 54. The test signal generation data P1 and the switching signal generation data P5 corresponding to the address are output to the formatter 60 and the I / O formatter 61, and the expected value data P4 is output to the comparator logic circuit 62.

The formatter 60 has a multi-stage configuration of flip-flop circuits and logic circuits. The formatter 60 processes test signal creation data (address data / write data) P1 from the data selector 59 to create a predetermined applied waveform. And uses it as a test signal P2 in the timing generation means 53
Is output to the driver 64 of the pin electronics 56 at a timing synchronized with the timing signal PH from. I /
Similarly to the formatter 60, the O formatter 61 has a multi-stage configuration of flip-flop circuits and logic circuits, and the switching signal generation data P5 from the data selector 59.
Is processed to create a predetermined applied waveform, which is used as a switching signal P
6 is output to the input / output switching means 58 at a timing synchronized with the timing signal PH from the timing generating means 53.

The comparator logic circuit 62 compares and determines the digital read data P3 from the analog comparator 65 of the pin electronics 56 with the expected value data P4 from the data selector 59, and shows pass / fail data PFD indicating the result of the comparison. Is output to the pass / fail register 63P and the fail memory 57. The pass / fail register 63P is set to fail (FA) by the comparator logic circuit 62 in the function test.
This is a register for storing whether or not it has been determined to be (IL), and is constituted by the number of bits corresponding to the number of ICs 71 to be measured that can be mounted on the IC mounting device 70. That is, when a maximum of 32 ICs to be measured 71 can be mounted on the IC mounting device 70, the pass / fail register 63P has a 32-bit configuration. If the corresponding bit of the pass / fail register 63P is a high-level "1" pass (PASS), the measured IC 71 is determined to be non-defective.
In the case of a low level “0” fail (FAIL), the measured IC 71 has some defect and is determined to be defective. Therefore, when analyzing the defective portion in detail, it is necessary to use the fail memory 57.

The pin electronics 56 comprises a plurality of drivers 64 and an analog comparator 65. The driver 64 and the analog comparator 65 are IC
One is provided for each input / output terminal of the mounting device 70, and one of them is connected via the input / output switching means 58. Input / output switching means 5
8 switches the connection state between one of the driver 64 and the analog comparator 65 and the input / output terminal of the IC mounting device 70 in accordance with the switching signal P6 from the I / O formatter 61. That is, when the number of input / output terminals of the IC mounting device 70 is m, the driver 64,
The analog comparator 65 and the input / output switching means 58 are each composed of m pieces. However, when measuring a memory IC or the like, an analog comparator is not required for an address terminal, a chip select terminal, or the like, and thus the number of analog comparators and input / output switching means may be small.

The driver 64 is connected to input / output terminals of the IC mounting device 70, that is, signal input terminals of the IC under test 71, such as an address terminal, a data input terminal, a chip select terminal, and a write enable terminal, via the input / output switching means 58. ,
The test signal P from the formatter 60 of the pin control means 55
Then, a high-level “H” or low-level “L” signal corresponding to 2 is applied, and a desired test pattern is written to the IC 71 to be measured.

The analog comparator 65 is an IC to be measured.
A signal output from the data output terminal 71 via the input / output switching means 58 is input, and the signal is output to the timing generation means 5.
3 is compared with the reference voltages VOH and VOL at the timing of the strobe signal (not shown), and the result of the comparison is taken as digital read data P3 of high level "PASS" or low level "FAIL" and the comparator logic circuit 6
Output to 2. Normally, the analog comparator 65 is composed of two comparators for the reference voltage VOH and the reference voltage VOL, but is omitted in the figure.

The fail memory 57 stores pass / fail data PF output from the comparator logic circuit 62.
D is stored in an address position corresponding to the address signal AD from the pattern generation means at the input timing of the timing signal PH from the timing generation means 53.
The fail memory 57 is composed of a RAM which has a storage capacity similar to that of the measured IC 71 and can be read and written at any time, and is used when the measured IC 71 is determined to be defective to analyze the defective portion in detail. It is something that can be done. Therefore, the fail memory 57 is not used in the ordinary simple pass / fail judgment.

The fail memory 57 has a data input / output terminal fixedly corresponding to the data output terminal of the IC mounting device 70. For example, if the total number of input / output terminals of the IC mounting device 70 is 280, and 160 of them are data output terminals, the fail memory 57 stores data of the same number or more than this number of data output terminals. It is composed of a memory having an input terminal. The pass / fail data PFD stored in the fail memory 57 is stored in the control unit 51.
, Transferred to a data processing memory (not shown), and analyzed.

[0020]

In the above-described IC test apparatus, the test signal creation data P1 output from the data selector 59 is converted into a predetermined test signal P2 by the formatter 60, and is converted via the driver 64. I
The voltage is applied to the measured IC 71 on the C mounting device 70. On the other hand, the switching signal creation data P5 output from the data selector 59 is converted into a predetermined switching signal P6 by the I / O formatter 61 and applied to the input / output switching means 58. Then, according to the application of the test signal P2, the measured IC 7
The read data output from 1 is input to the comparator logic circuit 62 via the input / output switching means 58 and the analog comparator 65. That is, the data selector 59
The test signal creation data P1 output from the device is output from the formatter 60-driver 64-input / output switching means 58-I
C71-I / O switching means 58-Analog comparator 6
5 through a test data path (first data path), which is finally converted into read data P3 and input to the comparator logic circuit 62.

The data selector 59 includes test signal creation data P1, switching signal creation data P5, and expected value data P4.
To the formatter 60, the I / O formatter 61, and the comparator logic circuit 62 at the same timing. However, since the test signal creation data P1 is input to the comparator logic circuit 62 after passing through the test data path (first data path) as described above, a signal whose timing is significantly delayed from the expected value data P4 is Become. Therefore, in the conventional IC test apparatus, a data path similar to that of the formatter 60 is provided in the comparator logic circuit 62 in order to adjust the timing of the comparison judgment of the comparator logic circuit 62. That is,
The formatter 60 is also provided in the comparator logic circuit 62.
A flip-flop (F / F) circuit and a logic circuit of the same number of stages are provided, and the data path (second data path) through which the expected value data P4 passes is made the same as the test data path (first data path). Value data P4 and read data P3
(Test signal creation data P1) and the timing of comparison and judgment was synchronized.

In recent years, memories such as synchronous DRAMs and synchronous SRAMs having different addresses and read data cycles have appeared. This synchronous DRAM
Has rapidly developed as an image memory capable of high-speed read / write and high-speed data transfer, and operates in synchronization with an external clock. When writing data, the address and write data have the same cycle. However, at the time of reading, the read data is output with a delay of several cycles with respect to the address.

Therefore, the synchronous DRAM is replaced with the conventional I DRAM.
To perform a test using the C test apparatus, as described above, the expected value data P4 and the read data P3 (test signal creation data P1)
It is necessary to adjust the timing of the comparison judgment between. Further, there is a problem in that an IC test apparatus whose timing is once adjusted for a synchronous DRAM cannot test a normal DRAM.

The present invention has been made in view of the above points, and even when the output timing of the read data fluctuates in accordance with the characteristics of the IC to be measured, the timing of the comparison between the read data and the expected value data is determined. It is an object of the present invention to provide an IC test apparatus capable of synchronizing data.

[0025]

[0026]

[0027]

Timing synchronization method of an IC test apparatus according to the present invention According to an aspect of the read data inspecting electrical characteristics of an object to be measured IC as output delayed a predetermined number cycles for the specified address A test signal generating means for generating a test signal such as the specified address, write data to be written to the specified address, and expected value data to be read from the specified address in the timing synchronization method of the IC test apparatus; Read / write control means for inputting the specified address and write data to the IC under test, writing a predetermined test pattern based on the specified address, reading the written test pattern in accordance with the specified address, and outputting the read test data as the read data And the expected value data output from the test signal generating means and the read / write control. Determining means for comparing and determining the read data read by the stage and outputting pass / fail data indicating the result of the determination; and determining the pass / fail data output from the determining means at an address corresponding to the designated address. A first memory for delaying the expected value data by a time corresponding to the predetermined number of cycles, and outputting the specified address to the predetermined number of cycles; Second synchronizing means for outputting to the fail memory delayed by a time corresponding to the time, and control means for inspecting electrical characteristics of the IC under test based on the pass / fail data stored in the fail memory It is equipped with.

Since the fail memory stores the pass / fail data output from the judging means at an address corresponding to the designated address from the test signal generating means, the microprogram of the test signal generating means is stored in a predetermined number of cycles, and The specified address may be output to the fail memory in a form delayed by a time corresponding to the determination processing time. However, there is a problem in that a microprogram must be created for each IC to be measured in accordance with the predetermined number of cycles and the determination processing time of the determination means. Therefore, in the present invention, a second synchronizing unit for delaying the designated address by a predetermined number of cycles and a time corresponding to the judgment processing time of the judging unit and outputting the same to the fail memory is newly provided. As a result, even if the output timing of the read data fluctuates according to the characteristics of the IC under test, the pass / fail data output from the judging unit corresponds to the specified address without rewriting the microprogram of the test signal generating unit Can be written to the specified address.

When the data terminal of the IC to be measured is used for both input and output, the test signal generating means generates switching data in addition to the designated address, write data and expected value data. This switching data controls the connection state of each data terminal according to the data read / write operation.
It is supplied to switching means for connecting each terminal of C to one of the driver means and the comparing means based on the switching data. Therefore, the switching means connects the data terminal to the driver means during the data write operation, and connects the data terminal to the comparison means during the data read operation. Therefore, if the IC under test is such that the read data is output with a predetermined number of cycles delayed from the specified address, the second synchronization means switches the switching data by delaying the same by the predetermined number of cycles. Enter in the means. Thus, the switching means can be switched at a timing synchronized with the switching timing between the writing operation and the reading operation.

[0030]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a diagram showing details of a portion corresponding to the timing synchronization method of the IC test apparatus of the present invention. Flip-flop circuits 11 and 16 are provided between the data selector 59 and the formatter 60. The flip-flop circuit 11 inputs the test signal creation data P1 from the data selector 59 to an input terminal and the high-speed clock CLK from the timing generation means 53 to a clock terminal CK (not shown), and outputs the high-speed clock CLK.
The test signal creation data P1 is output to the flip-flop circuit 16 of the next stage in accordance with the input timing of the test signal P1. The flip-flop circuit 16 outputs the test signal creation data P1 from the flip-flop circuit 11 to the formatter 60 according to the high-speed clock CLK. Therefore, the data selector 59
The test signal creation data P1 output from the flip-flop circuits 11 and 1 in two cycles of the high-speed clock CLK.
6 to the formatter 60.

Between the data selector 59 and the I / O formatter 61, there is provided a synchronization means comprising flip-flop circuits 21 to 26 and multiplexers (MUX) 27 and 28. Flip-flop circuit 21
Changes the switching signal generation data P5 from the data selector 59 into the input terminal of the flip-flop circuit 22 at the next stage and the first terminal T of the multiplexer 28 according to the high-speed clock CLK.
Output to 1. The flip-flop circuit 22 converts the switching signal creation data P5 from the flip-flop circuit 21 into the next-stage flip-flop circuit 23 according to the high-speed clock CLK.
And the third terminal T3 of the multiplexer 27. The flip-flop circuit 23 outputs the switching signal creation data P5 from the flip-flop circuit 22 to the input terminal of the next-stage flip-flop circuit 24 and the second terminal T2 of the multiplexer 27 according to the high-speed clock CLK. The flip-flop circuit 24 outputs the switching signal creation data P5 from the flip-flop circuit 23 to the high-speed clock CL.
In response to K, the signal is output to the input terminal of the next-stage flip-flop circuit 25 and the first terminal T1 of the multiplexer 27. The flip-flop circuit 25 outputs the switching signal creation data P5 from the flip-flop circuit 24 to the 0th terminal T0 of the multiplexer 27 according to the high-speed clock CLK.

The multiplexer 27 inputs a control signal P7 from the pattern generating means 54 to a selection terminal, and in response to the control signal P7, flip-flop circuits 22 to 25 connected from the 0th terminal T0 to the third terminal T3. The switching signal creation data P5 output from any one of the above is output to the multiplexer 28 in the next stage. The multiplexer 28
The control signal P8 from the pattern generating means 54 is input to the selection terminal, and either the multiplexer 27 connected to the zeroth terminal T0 or the flip-flop circuit 21 connected to the first terminal T1 is responsive to the control signal P8. The switching signal generation data P5 output from one of them is output to the flip-flop circuit 26. The flip-flop circuit 26 outputs the switching signal creation data P5 from the multiplexer 26 to the I / O formatter 61 according to the high-speed clock CLK.

The pattern generating means 54 is a multiplexer 2
The control signal P8 for selecting the first terminal T1 as the selection terminal of No. 8
When (T1) is output, the switching signal creation data P5 output from the data selector 59 becomes the high-speed clock CLK 2
The data is input to the I / O formatter 61 via the flip-flop circuits 21 and 26 in a cycle. That is, it is input to the I / O formatter 61 at the same timing as the test signal creation data P1. Therefore, at the time of writing, the pattern generating means 54 outputs a control signal P8 (T1) for selecting the first terminal T1 of the multiplexer 28 to the selection terminal of the multiplexer 28.

On the other hand, at the time of data reading, the pattern generating means 54 supplies the 0th terminal to the selection terminal of the multiplexer 28.
A control signal P8 (T0) for selecting the terminal T0 is output, and the switching signal creation data P output from the data selector 59 is output.
5 is input to the I / O formatter 61 with a delay corresponding to the number of cycles corresponding to the control signal P7 input to the selection terminal of the multiplexer 27. That is, the pattern generating means 54 controls the control signal P8 for selecting the 0th terminal T0.
(T0) is output to the selection terminal of the multiplexer 28, and the control signal P7 corresponding to the number of cycles is output to the selection terminal of the multiplexer 27.

Therefore, when the pattern generation means 54 outputs the control signal P7 (T0) for selecting the 0th terminal T0 to the selection terminal of the multiplexer 27, the switching signal creation data P5 output from the data selector 59 is converted into six flip-flops. I / O formatter 6 via circuits 21-26
1, the test signal creation data P1
4 clocks later than the high-speed clock CLK. Similarly, a control signal P7 (T1) for the pattern generation means 54 to select the first terminal T1 of the multiplexer 27
Is output to the selection terminal of the multiplexer 27, the switching signal creation data P5 is delayed by three cycles by the high-speed clock CLK. Similarly, the pattern generating means 54 controls the control signal P7 (T
When 2) is output to the selection terminal of the multiplexer 27, the switching signal creation data P5 is delayed by two cycles with the high-speed clock CLK, and the control signal P7 for selecting the third terminal T3.
When (T3) is output to the selection terminal of the multiplexer 27, the switching signal creation data P5 becomes 1 by the high-speed clock CLK.
It will be delayed by the number of cycles.

On the other hand, the flip-flop circuit 3 is provided between the data selector 59 and the comparator logic circuit 62.
Synchronization means including a number 1 to 36 and a multiplexer 37 is provided. The flip-flop circuit 31 outputs the expected value data P4 from the data selector 59 to the input terminal of the next-stage flip-flop circuit 32 and the fourth terminal T4 of the multiplexer 37 according to the high-speed clock CLK. The flip-flop circuit 32 outputs the expected value data P4 from the flip-flop circuit 31 to the input terminal of the next-stage flip-flop circuit 33 and the third terminal T3 of the multiplexer 37 according to the high-speed clock CLK. The flip-flop circuit 33 outputs the expected value data P4 from the flip-flop circuit 32 to the input terminal of the next-stage flip-flop circuit 34 and the second terminal T2 of the multiplexer 37 according to the high-speed clock CLK. The flip-flop circuit 34 receives the expected value data P from the flip-flop circuit 33.
4 is output to the input terminal of the next-stage flip-flop circuit 35 and the first terminal T1 of the multiplexer 37 in response to the high-speed clock CLK. The flip-flop circuit 35 converts the expected value data P4 from the flip-flop circuit 34 into a 0-th terminal T0 of the multiplexer 37 according to the high-speed clock CLK.
Output to

The multiplexer 37 inputs a control signal P9 from the pattern generating means 54 to a selection terminal, and in response to the control signal P9, flip-flop circuits 31 to 35 connected from the 0th terminal T0 to the 4th terminal T4. Is output to the flip-flop circuit 36. The flip-flop circuit 36 outputs the expected value data P4 from the multiplexer 37 to the comparator logic circuit 62 according to the high-speed clock CLK.

Pattern generating means 54 and fail memory 5
7 is provided with a synchronizing means composed of flip-flop circuits 41 to 47 and a multiplexer 48. The flip-flop circuit 41 includes the pattern generation unit 5
4 to the input terminal of the flip-flop circuit 42 of the next stage and the fourth terminal T4 of the multiplexer 48 according to the high-speed clock CLK. The flip-flop circuit 42 converts the address signal AD from the flip-flop circuit 41 into the input terminal of the next-stage flip-flop circuit 43 and the multiplexer 4 according to the high-speed clock CLK.
8 to a third terminal T3. Flip-flop circuit 4
3 is an address signal AD from the flip-flop circuit 42.
Is output to the input terminal of the flip-flop circuit 44 of the next stage and the second terminal T2 of the multiplexer 48 according to the high-speed clock CLK. The flip-flop circuit 44 outputs the address signal AD from the flip-flop circuit 43 to the input terminal of the next-stage flip-flop circuit 45 and the first terminal T1 of the multiplexer 48 according to the high-speed clock CLK. The flip-flop circuit 45 outputs the address signal AD from the flip-flop circuit 44 to the 0th terminal T0 of the multiplexer 48 according to the high-speed clock CLK.

The multiplexer 48 inputs the control signal P9 from the pattern generating means 54 to the selection terminal, and in response to the control signal P9, flip-flop circuits 41 to 45 connected from the 0th terminal T0 to the fourth terminal T4. Is output to the flip-flop circuit 46. The flip-flop circuit 46 outputs the address signal AD from the multiplexer 48 to the input terminal of the next-stage flip-flop circuit 47 according to the high-speed clock CLK. The flip-flop circuit 47 outputs the address signal AD from the flip-flop circuit 46 to the fail memory 57 according to the high-speed clock CLK. The flip-flop circuit 47 has a data path for delaying a signal by a time corresponding to the determination processing time of the comparator logic circuit. Therefore, the pattern generating means 54 only needs to output the common control signal P9 to the multiplexers 37 and 48. If the flip-flop circuit 47 does not exist, the pattern generating means 54 outputs a control signal (a signal different from the control signal P9 for the multiplexer 37) considering the time corresponding to the determination processing time of the comparator logic circuit to the multiplexer 4.
8 may be output.

The pattern generating means 54 includes the multiplexer 3
When the control signal P9 (T4) for selecting the fourth terminal T4 is output to the selection terminals 7 and 48, the expected value data P4 output from the data selector 59 is output to the flip-flop circuit 3
1 and 36, the high-speed clock CLK is input to the comparator logic circuit 62 in two cycles, and the address signal AD output from the pattern generating means 54 is output via the flip-flop circuits 41, 46 and 47. The data is input to the fail memory 57 in three cycles of the high-speed clock CLK. Therefore, the measured IC 71
Is a normal DRAM or the like, the pattern generation means 5
4 outputs a control signal P9 (T4) for selecting the fourth terminal T4 of the multiplexers 37 and 48 to the multiplexers 37 and 4.
8 to the selection terminal.

On the other hand, when the IC 71 to be measured is a synchronous DRAM or the like, the pattern generating means 54 transmits the control signal P9 corresponding to the number of data delay cycles at the time of reading data from the synchronous DRAM to the multiplexer 37 and the multiplexer 37. Output to 48 select terminals. That is, the control signal P9 for selecting the 0th terminal T0 by the pattern generation means 54
When (T0) is output to the selection terminals of the multiplexers 37 and 48, the expected value data P4 output from the data selector 59 is delayed by four cycles by the high-speed clock CLK via the six flip-flop circuits 31 to 36,
The address signal AD input to the comparator logic circuit 62 and output from the pattern generating means 54 is supplied to the high-speed clock C via seven flip-flop circuits 41 to 47.
The data is input to the fail memory 57 after being delayed by 5 cycles in LK.

Similarly, the pattern generating means 54 controls the control signal P for selecting the first terminals T1 of the multiplexers 37 and 48.
When 9 (T1) is output to the selection terminals of the multiplexers 37 and 48, the expected value data P4 is delayed by three cycles by the high-speed clock CLK, and the address signal AD is delayed by four cycles by the high-speed clock CLK. When the pattern generating means 54 outputs a control signal P9 (T2) for selecting the second terminal T2 of the multiplexers 37 and 48 to the selection terminals of the multiplexers 37 and 48, the expected value data P4 is delayed by two cycles by the high-speed clock CLK, The address signal AD is delayed by three cycles with the high-speed clock CLK.
When the pattern generation means 54 outputs a control signal P9 (T3) for selecting the third terminal T3 of the multiplexers 37 and 48 to the selection terminals of the multiplexers 37 and 48, the expected value data P4 is delayed by one cycle with the high-speed clock CLK, and The signal AD is delayed by two cycles with the high-speed clock CLK. Therefore, if it is known how much the read data is delayed by the number of cycles with respect to the address of the synchronous DRAM, the control signal P9 for the multiplexers 37 and 48 can be easily changed by simply changing the control signal P9 appropriately. .

Next, an operation for testing a synchronous DRAM in which read data is output with a delay of two cycles with respect to an address will be described. First, Synchronous D
Since the RAM outputs the read data with a delay of two cycles with respect to the read address, the pattern generating means 54 supplies the second terminal T
The control signal P7 (T2) for selecting the input of the second terminal T2 and the control signal P9 (T2) for selecting the input of the second terminal T2 are also output to the selection terminals of the multiplexers 37 and 48, respectively.
As a result, the multiplexer 27 outputs the switching signal generation data P5 from the flip-flop circuit 23 connected to the second terminal T2 to the multiplexer 28, and the multiplexer 37 outputs the flip-flop circuit connected to the second terminal T2. Expected value data P4 from circuit 33
To the flip-flop circuit 36, and the multiplexer 48 outputs the address signal AD from the flip-flop circuit 43 connected to the second terminal T2 to the flip-flop circuit 46.

When writing pattern data to the synchronous DRAM, the pattern generating means 54 outputs to the multiplexer 28 a control signal P8 (T1) for selecting the input of the first terminal T1. Thus, the multiplexer 28 outputs the switching signal creation data P5 from the flip-flop circuit 21 connected to the first terminal T1 to the flip-flop circuit 26. Therefore, the test signal creation data (address and write data) P1 output from the data selector 59 is input to the formatter 60 via the two flip-flop circuits 11 and 16. Further, the switching signal creation data P5 output from the data selector 59 is input to the I / O formatter 61 via the two flip-flop circuits 21 and 26.

The case where the written pattern data is read from the synchronous DRAM will be described. When reading data, the synchronous DRAM (IC under test 7)
From 1), the data is output with a delay of two cycles with respect to the read address, so that the switching signal creation data P5 input to the I / O formatter 61 and the expected value data P4 input to the comparator logic circuit 62 have the same number of cycles ( It is necessary to delay the address signal AD input to the fail memory 57 by three cycles, which is one cycle longer than that.

First, the pattern generating means 54 outputs to the multiplexer 28 a control signal P8 (T0) for selecting the input of the 0th terminal T0. Thereby, the multiplexer 28 outputs the switching signal creation data P5 to the flip-flop circuit 26 via the multiplexer 27 and the flip-flop circuit 23. That is, the switching signal creation data P5 output from the data selector 59 is input to the I / O formatter 61 via the four flip-flop circuits 21, 22, 23 and 26.

On the other hand, the test signal creation data (read address) P 1 output from the data selector 59 is input to the formatter 60 via the two flip-flop circuits 11 and 16. That is, the test signal creation data (read address) P1 is input to the formatter 60 at the same timing as when writing data. Test signal creation data P
1 is processed into a predetermined applied waveform by the formatter 60, and is output as a test signal (read address) P2 to the driver 64 of the pin electronics 56 in synchronization with the timing signal from the timing generation means 53. It is applied to the address terminal of the IC 71). The synchronous DRAM (the IC under test 71) to which the test signal (read address) P2 is input outputs data corresponding to the test signal (read address) P2 at a timing delayed by two cycles.

At this time, since the switching signal creation data P5 output from the data selector 59 is input to the I / O formatter 61 via the four flip-flop circuits 21, 22, 23 and 26, the I / O formatter 61 61
Outputs the switching signal P6 to the input / output switching means 58 at a timing delayed by two cycles from the test signal P2. Also,
The expected value data P4 output from the data selector 59 includes four flip-flop circuits 31, 32, 33 and 36.
, The test signal creation data (read address) P1 is input to the comparator logic circuit 62 at a timing two cycles later than the input timing to the formatter 60. In the comparator logic circuit 62, a data path similar to that of the formatter 60 is provided, and the comparison determination timing between the expected value data P4 and the read data P3 coincides. The address signal AD output from the pattern generation means 54 is supplied to five flip-flop circuits 41, 42, 43, 46 and 4
7, the test signal creation data (read address) P1 is input to the fail memory 57 at a timing about three cycles later than the timing at which the test signal generation data P1 is input to the formatter 60. Since the flip-flop circuit 47 has a data path for delaying the signal by a time corresponding to the determination processing time of the comparator logic circuit, the pass / fail data PF output from the comparator logic circuit 62 is provided.
The timing between D and the address signal AD coincides.

As described above, in the IC test apparatus of the present invention, when testing a measured IC 71 such as a synchronous DRAM which outputs two cycles behind the read address, the expected value data P4 is By delaying the timing of input to the comparator logic circuit 61 by the same amount as that cycle, the synchronization between the read data P3 and the expected value data P4 and the pass / fail data P
The synchronization between the FD and the address signal AD is established.

When the IC 71 to be measured is a normal DRAM or the like, the pattern generator 54 outputs a control signal P8 (T1) for selecting the input of the first terminal T1 to the multiplexer 28, And 48, the control signal P9 for selecting the input of the fourth terminal T4
(T4) is output. Thereby, the data selector 5
9 is input to the I / O formatter 61 via the two flip-flop circuits 21 and 26. Similarly, the expected value data P4 output from the data selector 59 is also input to the two flip-flop circuits. Since the data is input to the comparator logic circuit 62 via the circuits 31 and 36, the timing of the comparison determination between the expected value data P4 and the read data P3 coincides with each other. Further, the address signal AD output from the pattern generating means 54 also has three flip-flop circuits 41, 46 and 47.
Input to the fail memory 57 via
The timing between the pass / fail data PFD output from the comparator logic circuit 62 and the address signal AD coincide.

[0051]

According to the present invention, even if the output timing of the read data fluctuates in accordance with the characteristics of the IC to be measured, the timing for comparing and judging the read data and the expected value data, the pass / fail data, There is an effect that the timing with the write address signal can be easily synchronized.

[Brief description of the drawings]

FIG. 1 is a diagram showing details of a portion corresponding to a timing synchronization method of an IC test apparatus of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a conventional IC test apparatus.

[Explanation of symbols]

11, 16, 21 to 26, 31 to 36, 41 to 47 ... flip-flop circuits, 27, 28, 37 ... multiplexers, 50 ... tester units, 51 ... control means, 52 ... DC measurement means, 53 ... timing generation means, 54: pattern generating means, 55: pin control means, 56: pin electronics, 57: fail memory, 58: input / output switching means, 5
9 Data selector, 60 Formatter, 61 I /
O formatter, 62 ... Comparator logic circuit, 6
3P: pass / fail register, 64: driver, 65
... Analog comparator, 69 ... Tester bus, 70 ... I
C mounting device, 71: IC to be measured, P1: test signal creation data, P2: test signal, P3: read data, P4: expected value data, P5: switching signal creation data, P6: switching signal, P7, P8, P9 ... Control signal, AD ... address signal, PFD ... pass / fail data, CLK ... high-speed clock

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G01R 31/28-31/3193 G11C 29/00 651

Claims (2)

(57) [Claims] 1. A timing synchronization method for an IC test apparatus for inspecting electrical characteristics of an IC under test, in which read data is output after a predetermined number of cycles with respect to a specified address, wherein: Test signal generating means for generating a test signal such as write data to be written and expected value data to be read from the specified address; and inputting the specified address and the write data to the IC under test; A predetermined test pattern based thereon is written, the written test pattern is read in accordance with the specified address, and read / write control means for outputting as the read data; the expected value data output from the test signal generating means; and The read data read by the read / write control means are compared and determined, and the determination result is obtained. Determining means for outputting pass / fail data indicative of: a fail memory storing the pass / fail data output from the determining means at an address corresponding to the designated address; and setting the expected value data to the predetermined cycle number. A first synchronizing unit that outputs the specified address to the determination unit with a delay corresponding to the predetermined time, and a second synchronization unit that outputs the designated address to the fail memory with a delay corresponding to the predetermined number of cycles and the determination time of the determination unit. A timing synchronization method for an IC test apparatus, comprising: synchronization means; and control means for inspecting electrical characteristics of the IC under test based on the pass / fail data stored in the fail memory. 2. The switching circuit according to claim 2, wherein said test signal generation means controls a connection state of each terminal of said IC under test according to a data read / write operation in addition to said designated address, said write data and said expected value data. A plurality of driver means for applying a signal based on the specified address and the write data to each terminal of the IC under test, and reading and writing of the IC under test based on the specified address. A plurality of comparing means for comparing the signal output from each terminal with a predetermined reference voltage and outputting the read data; and switching each terminal of the IC under test and one of the driver means and the comparing means. A plurality of switching means connected on the basis of data; and a third switching means for delaying the switching data by the same number as the predetermined number of cycles and inputting the switching data to the switching means. Timing synchronization method of an IC test apparatus according to claim 1, characterized in that a synchronization means.