JPH08315597A - Ic test equipment - Google Patents

Abstract

PURPOSE: To shorten the test time significantly even when the tests are carried out a plurality of times under different conditions by executing the file switching from a pattern generating means. CONSTITUTION: When an IC 71 is tested under a plurality of conditions, a control means 51 outputs data related to the plurality of conditions to a timing generation means 53 and a pattern generation means 54. Subsequently, the control means 51 outputs a start pulse to the timing generation means 53 in order to start a test under first conditions and the results are stored in the first file of a register file 63. The pattern generation means 54 then outputs a file switching signal FCH to the register file 63 in order to select a second file. Upon finishing the test under second conditions, the results are stored in the second file. The tests are carried out sequentially and the results are stored. Upon completion of tests, the control means 51 can read out the results from each file and judge easily.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC tester for inspecting the electrical characteristics of an IC (integrated circuit), and in particular, even if the test conditions are different, the test is performed by a series of processes,
The present invention relates to an IC test device that can significantly reduce the test time.

[0002]

2. Description of the Related Art In order to ship an IC whose performance and quality are guaranteed as a final product, it is necessary to extract all or part of the IC product in each process of the manufacturing department and inspection department and inspect its electrical characteristics. There is. The IC test device is a device for inspecting such electrical characteristics. The IC tester gives a predetermined test pattern data to the IC to be measured, reads the output data of the IC to be measured thereby, and outputs whether the basic operation and function of the IC to be measured have no problem. We analyze failure information from the data and inspect electrical characteristics.

The test in the IC test apparatus is a direct current test (D
It is roughly divided into a C measurement test) and a function test (FC measurement test). For the DC test, D is connected to the input / output terminal of the IC to be measured.
By applying a predetermined voltage or current from the C measuring means, it is inspected whether the basic operation of the IC to be measured is defective. On the other hand, in the function test, given pattern data for test from the pattern generating means to the input terminal of the IC to be measured, the output data of the IC to be measured is read, and there is no problem in the basic operation and function of the IC to be measured. It is something to inspect. That is, in the function test, the input timing of each input signal of the IC to be measured such as address, data, write enable signal, and chip select signal, and input conditions such as amplitude are changed to test the output timing and output amplitude. It is something to do.

FIG. 2 is a block diagram showing a schematic configuration of a conventional IC test apparatus. The IC test device is roughly divided into a tester unit 50 and an IC mounting device 70. Tester part 5
0 is a control means 51, a DC measurement means 52, a timing generation means 53, a pattern generation means 54, a pin control means 55,
It is composed of a pin electronics 56, a fail memory 57 and an input / output switching means 58. Although the tester unit 50 has various other components, only the necessary parts are shown in the present specification.

The tester section 50 and the IC mounting device 70 are connected by a signal line composed of a plurality (m) of coaxial cables or the like corresponding to the total number of input / output terminals (m) of the IC mounting device 70. The connection relationship between the terminals and the coaxial cable is associated with each other by a relay matrix (not shown), and various signals are transmitted between the predetermined terminals and the coaxial cable. The number of signal lines is physically the same as the total number m of input / output terminals of the IC mounting apparatus 70.

The IC mounting device 70 includes a plurality of ICs to be measured.
71 is configured to be mounted in a socket. The input / output terminals of the IC to be measured 71 and the input / output terminals of the IC attachment device 70 are connected in one-to-one correspondence with each other. For example, the measured IC 71 with 28 input / output terminals is
In the case of the IC mounting device 70 that can mount zero, 28 in total
It will have 0 input / output terminals.

The control means 51 controls the entire IC test apparatus,
It is used for operation and management, and has a microprocessor configuration. Therefore, although not shown, the control means 51 has a ROM for storing a system program, a RAM for storing various data, and the like. The control means 51
DC measuring means 52, timing generating means 53, pattern generating means 54, pin control means 55 and fail memory 5
7 via a tester bus (data bus, address bus, control bus) 69.

The control means 51 sends the data for DC test to D
The C measuring means 52, the timing data for starting the function test, the timing generating means 53, the programs and various data necessary for the test pattern generation, the pattern generating means 54, the expected value data and the like, the pin control means 55,
Output each. In addition to this, the control means 51 outputs various data to the respective constituent parts via the tester bus 69. Further, the control means 51 uses the DC measuring means 52.
The data (DC data or fail data) indicating the test result is read from the internal register in the internal memory, the fail memory 57 and the pass / fail register 65 in the pin control means 55, and these are analyzed and measured I
The quality of C71 is judged.

The DC measuring means 52 receives the DC test data from the control means 51 and performs a DC test on the IC 71 to be measured of the IC mounting apparatus 70 based on the DC test data. DC
The measuring means 52 starts the DC test by inputting the measurement start signal from the control means 51, and writes the data showing the test result in the internal register. When the DC measurement means 52 finishes writing the test result data, it outputs an end signal to the control means 51. The data written in the internal register is read by the control means 51 via the tester bus 69 and analyzed there. In this way, the DC test is performed. Further, the DC measuring means 52 supplies the reference voltages VIH, VIL, VOH, and VOL to the driver 64 of the pin electronics 56 and the analog comparator 65.

The timing generating means 53 is a control means 71.
The timing data from the memory is stored in the internal memory, and the high-speed operation clock φ is output to the pattern generation means 54 and the pin control means 55 based on it, and the timing signal PH for writing and reading the data is supplied to the pin control means 55 and fail. Output to the memory 57. Therefore, the operation speeds of the pattern generation means 54 and the pin control means 55 are determined by this high-speed operation clock φ, and the timing of data writing and reading with respect to the IC to be measured 71 is the timing signal P.
Determined by H. The timing of writing pass / fail data to the fail memory 57 is also determined by the timing signal PH. Therefore, the output timings of the test signal S2 output from the formatter 60 to the pin electronics 56 and the switching signal S6 output from the I / O formatter 61 to the input / output switching means 58 are also high-speed operation clock φ from the timing generating means 53 and It is controlled according to the timing signal PH. Further, the timing generating means 53 inputs the timing switching control signal CH from the pattern generating means 54, and switches the operation cycle, the phase and the like as appropriate based on the input.

The pattern generating means 54 inputs the data (microprogram or pattern data) for pattern generation from the control means 51 and outputs the pattern data PD based on the data to the data selector 59 of the pin control means 55. That is, the pattern generating means 54 uses a program method that outputs regular test pattern data by various arithmetic processing according to the microprogram method, and an internal memory (referred to as a pattern memory) that has the same data as the data written in the IC to be measured. Is written in advance and is read at the same address as the IC to be measured, so that irregular (random) pattern data (expected value data)
It operates by the memory stored method that outputs. In the program method, the IC to be measured is a RAM (Random Acces).
Corresponding to the test of volatile memory such as s Memory),
The memory stored method is ROM (Random Acce
It corresponds to the test of non-volatile memory such as ss Memory). Even in the case of the memory stored method, the address supplied to the IC to be measured is generated by the program method.

The pin control means 55 is a data selector 59,
Formatter 60, I / O formatter 61, comparator logic circuit 62 and pass / fail (PASS /
FALI) register 63P. The data selector 59 is composed of a memory that stores various test signal creation data (address data / write data) S1, switching signal creation data S5, and expected value data S4. The test signal creation data S1 and the switching signal creation data S5 corresponding to the address are input to the formatter 60 and the I / O formatter 61, and the expected value data S4 is output to the comparator logic circuit 62.

The formatter 60 is composed of flip-flop circuits and logic circuits in multiple stages, and processes the test signal creation data (address data / write data) S1 from the data selector 59 to create a predetermined applied waveform. Then, it is used as the test signal S2 and the timing generation means 53
The signal is output to the driver 64 of the pin electronics 56 at the timing synchronized with the timing signal PH from. I /
Like the formatter 60, the O formatter 61 also has a multi-stage configuration of flip-flop circuits and logic circuits, and the switching signal creation data S5 from the data selector 59.
Is processed to create a predetermined applied waveform, which is used as a switching signal S
The signal is output to the timing input / output switching means 58 synchronized with the timing signal PH from the timing generation means 53.

The comparator logic circuit 62 compares the digital signal S3 from the analog comparator 65 of the pin electronics 56 and the expected value data S4 from the data selector 59 and makes a pass / path indicating the determination result.
The fail data PASS / FAIL is output to the pass / fail register 63P and the fail memory 57. The pass / fail register 63P is a register that stores whether or not the comparator logic circuit 62 determines that it is FAIL in the function test, and the IC to be measured 71 that can be mounted on the IC attachment device 70.
The number of bits corresponds to the number of bits. That is, when up to 32 ICs to be measured 71 can be mounted on the IC mounting device 70, the pass / fail register 63P has 3 pins.
It has a 2-bit configuration. This pass / fail register 63
Path (PAS) in which the corresponding bit of P is high level "1"
In the case of S), the measured IC 71 is determined to be a good product, and in the case of a low level “0” fail (FAIL), the measured IC 71 has some defect and is determined to be a defective product. It Therefore, it is necessary to use the fail memory 57 when analyzing the defective portion in detail.

The pin electronics 56 is composed of a plurality of drivers 64 and an analog comparator 65. The driver 64 and the analog comparator 65 are ICs
One is provided for each input / output terminal of the mounting device 70, and either one of them is connected via the input / output switching means 58. Input / output switching means 5
Reference numeral 8 switches the connection state between one of the driver 64 and the analog comparator 65 and the input / output terminal of the IC attachment device 70 according to the switching signal S6 from the I / O formatter 61. That is, when the number of input / output terminals of the IC mounting device 70 is m, the driver 64,
Each of the analog comparator 65 and the input / output switching means 58 is composed of m pieces. However, when measuring a memory IC or the like, an analog comparator is not required for an address terminal, a chip select terminal, or the like, so the number of analog comparators and input / output switching means may be small.

The driver 64 is connected to the input / output terminals of the IC mounting device 70, that is, the signal input terminals such as the address terminal, the data input terminal, the chip select terminal, and the write enable terminal of the IC to be measured 71 through the input / output switching means 58. ,
Test signal S from the formatter 60 of the pin control means 55
A high level “H” or low level “L” signal corresponding to 2 is applied to write a desired test pattern in the IC 71 to be measured.

The analog comparator 65 is an IC to be measured.
The signal output from the data output terminal 71 is input through the input / output switching means 58, and is input to the timing generating means 5
3 is compared with the reference voltages VOH and VOL at the timing of a strobe signal (not shown) from 3 and the comparison result is output to the comparator logic circuit 62 as a high level "PASS" or low level "FAIL" digital signal S3. Normally, the analog comparator 65 has a reference voltage VO.
Although it is composed of two comparators for H and reference voltage VOL, they are omitted in FIG.

The fail memory 57 is a pass / fail data PA output from the comparator logic circuit 62.
The timing generator 5 is provided with SS / FAIL at the address position corresponding to the address signal ADD from the pattern generator.
It is stored at the input timing of the timing signal PH from the No. 3. The fail memory 57 is composed of a RAM that has a storage capacity similar to that of the IC 71 to be measured and can be read from and written to at any time. When the IC 71 to be measured is determined to be defective, the fail memory 57 is used for detailed analysis. It is what is done. Therefore, the fail memory 57 is not used in the normal simple pass / fail judgment.

Further, the fail memory 57 has a data input / output terminal that fixedly corresponds to the data output terminal of the IC mounting apparatus 70. For example, when the total number of input / output terminals of the IC attachment device 70 is 280 and 160 of them are data output terminals, the fail memory 57 has the same or more data as the number of data output terminals. It is composed of a memory having an input terminal. The fail data FD stored in the fail memory 57 is read by the control means 51, transferred to a memory for data processing (not shown), and analyzed.

[0020]

In the IC test apparatus as described above, since one bit of the pass / fail register corresponds to one IC 71 to be measured, the function test is performed under the first condition. In this case, the test result cannot be determined unless the pass / fail register is read after the test under the first condition is performed. Therefore, when the test condition is changed from the first condition to the second condition and set, the test result is read from the pass / fail register at the time when the test under the first condition is completed, and at the time when the read is completed. Next, after rewriting various data corresponding to the second condition, the test under the second condition was performed. That is, when a test is performed for one IC to be measured under different conditions, it is necessary to rewrite various data each time the condition is changed.
Therefore, in addition to the actual test time, the time required to rewrite various data for changing the test conditions (condition setting time) becomes long, and the total test time also significantly increases. Was. When the memory area of the IC to be measured is divided into predetermined areas (for example, mat units) for testing, the test result is read from the pass / fail register every time the test for the predetermined area is completed, and the determination is performed. Since the test for the next area was performed, there is a problem that the accumulation of the time (start processing time) required from the end of the test of the predetermined area to the start of the test of the next area increases the total test time. there were.

The present invention has been made in view of the above-mentioned points, and the condition can be satisfied regardless of whether a test under different conditions is performed a plurality of times as described above or the same test is performed a plurality of times on different regions. It is an object of the present invention to provide an IC test apparatus capable of shortening the set time and the start-up processing time and greatly reducing the total test time.

[0022]

According to a first aspect of the present invention, there is provided an IC test apparatus, which is address data for designating an address of an IC memory under test, data to be written at the designated address, and a clock which is a reference for operation. Test signal generating means for generating a test signal composed of signals and the like according to a predetermined condition, and data corresponding to the test signal is written to the IC memory under test, and the written data is written according to the address data. IC read / write control means for reading,
The data read by the IC read / write control means is compared with the reference data to make a judgment, and the path / path indicating the judgment result is displayed.
Judgment means for outputting fail data and the IC to be measured
When a plurality of tests according to different conditions are performed on the memory as a series of test operations or the IC to be measured
The pass / fail data output from the determination unit when a plurality of tests according to predetermined conditions are performed as a series of test operations on different areas of the memory can be stored for each of the conditions or for each of the areas. And a control means for reading the pass / fail data stored in the register file and inspecting the electrical characteristics of the IC to be measured.

The IC test apparatus according to the second invention comprises address data for designating an address of the IC memory under test, data to be written at this designated address, and a clock signal as a reference for operation. Test signal generating means for generating a test signal according to a predetermined condition, and IC read / write control means for writing data according to the test signal to the IC memory under test and reading the written data according to the address data. Determination means for comparing and determining the data read by the IC read / write control means with reference data and outputting pass / fail data indicating the determination result, and the pass / fail data for the address designated by the address data. Memory which is taken in and stored in the IC memory and is different from the IC memory under test. The determination means in the case where a plurality of tests according to the conditions are performed as a series of test operations or when the plurality of tests according to a predetermined condition are performed as a series of test operations in different areas of the IC memory under test. A fail memory that stores the pass / fail data output from the memory for each condition or each area, and the pass / fail data stored in the fail memory is read to determine the electrical characteristics of the IC to be measured. It is provided with a control means for inspecting.

[0024]

In the IC test apparatus according to the first aspect of the present invention, the test signal generating means changes the test signals such as the address, data, write enable signal and chip select signal according to predetermined conditions such as input timing and amplitude. Output. The IC read / write means writes data corresponding to the test signal in the IC to be measured or reads the written data. Therefore, there are some ICs to be measured in which data is not accurately written and some in which data is not accurately read out due to changes in input timing and amplitude. The determination means compares the data read by the IC read / write means with the reference data, and if the two match, the pass data indicating that the data read / write processing of the IC to be measured for the condition is normal. If they do not match, fail data indicating an abnormality is output. The register file is
When a test according to a certain condition is performed, the pass / fail data output from the judging means is stored in a predetermined file. Therefore, when a plurality of tests under different conditions are performed on the IC memory under test as a series of test operations, pass / fail data is output from the judging means for each test under different conditions. Therefore, the register file stores pass / fail data output for each test in a plurality of files. Alternatively, when a plurality of tests under different conditions of the IC memory under test are performed as a series of test operations,
Since the pass / fail data is output from the judging means for each test for each area, the register file stores the pass / fail data output for each test in a plurality of files. The control means reads the pass / fail data stored in each file of the register file and inspects the electrical characteristics of the IC to be measured. The IC test apparatus according to the second invention uses a conventionally used fail memory in the same way as the register file of the first invention. This allows pass / fail data obtained for each test to be stored separately in the register file (fail memory), even if tests under different conditions are performed multiple times or the same test is performed multiple times for different areas. The test result can be easily recognized by reading pass / fail data from this register file (fail memory), the condition setting time and start-up processing time can be shortened, and the total test time can be significantly increased. Can be reduced to.

[0025]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 is a diagram showing a schematic configuration of an IC test apparatus according to the present invention. In FIG. 1, the same components as those in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted. The present invention is different from the conventional technique of FIG. 2 in that the IC attaching device 7 is replaced with the conventional pass / fail register 63P.
Registers each having a number of bits corresponding to the number of ICs under test 71 that can be mounted on 0 are defined as one file, and a register file 63 having a plurality of files is provided, and switching of the files of the register file 63 is performed by pattern generation. The point is that the file switching signal FCH from the means 54 is used. For example, when the number of ICs to be measured 71 that can be mounted on the IC attachment device 70 is 32, the register file 63 includes 16 32-bit files. That is, the register file 63 is composed of 512 bits in total.

Next, an operation example of this IC test apparatus will be described. Here, a case will be described in which the register file 63 is composed of 16 files of 32 bits, and the test is performed on the IC to be measured 71 under the eight conditions from the first to the eighth. In such a case, first, the control means 51
Outputs timing data relating to the first to eighth conditions (up to 16 conditions) to the timing generating means 53, and also to the pattern generating means 54, data for pattern generation relating to the eight conditions (microprogram or pattern). Data) is output. The data for creating the pattern is the file switching signal FC from the pattern generating means 54 to the register file 63 at the time when the conditions are switched.
H is output.

After that, the control means 51 outputs a start pulse to the timing generation means 53. Then, the function test according to the first condition is performed. At this point,
Since the file switching signal FCH for the first file is input to the register file 63, all the test results under the first condition are stored in the first file of the register file 63. Next, the pattern generating means 54
The file switching signal FCH is output to the register file 63 and the second file is selected before the function test according to the condition of 1 is activated. Then, when the function test according to the second condition ends, the test result under the second condition is stored in the second file of the register file 63. In this way, the function test according to the third to eighth conditions is performed, and the test results corresponding thereto are stored in the third to eighth files of the register file 63.

In this way, when the first to eighth function tests are completed, the control means 51 reads the pass / fail data from each file of the register file 63 to determine which of the first to eighth functions. In the condition test, it is possible to easily recognize which IC to be measured has failed, and it is not necessary to rewrite various data each time the test condition is changed unlike the conventional method. It is possible to significantly reduce the time. Further, even when the memory area of the IC to be measured is divided into predetermined areas (for example, mat units) and tested, the start-up processing time is similarly shortened by associating the test result of each area with each file of the register file 63. The total test time can be significantly reduced.

In the above embodiment, the case where the register file 63 is used has been described, but the fail memory 57 may be used instead. That is, the internal address generator of the fail memory 57 is operated as shown in FIG.
The address is advanced according to the file switching signal FCH from the pattern generating means 54, and the comparator logic circuit 62
Alternatively, the pass / fail data may be written into the fail memory 57 every time the condition is changed or the area is changed. In addition, the fail switching signal FCH is sent to the fail memory 5
Alternatively, the address signal ADD supplied to 7 may be interrupted on the pattern generating means 54 side.

[0030]

According to the present invention, the condition setting time and the start-up processing time can be shortened even if the test under different conditions is performed a plurality of times or the same test is performed a plurality of times for different areas. There is an effect that the test time of can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of an IC test apparatus of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a conventional IC test apparatus.

[Explanation of symbols]

50 ... Tester section, 51 ... Control means, 52 ... DC measuring means, 53 ... Timing generating means, 54 ... Pattern generating means, 55 ... Pin control means, 56 ... Pin electronics, 57 ... Fail memory, 58 ... Input / output switching means 5,
9 ... Data selector, 60 ... Formatter, 61 ... I /
O formatter, 62 ... Comparator logic circuit, 6
3 ... Register file, 64 ... Driver, 65 ... Analog comparator, 69 ... Bus, 70 ... IC mounting device, 7
1 ... IC to be measured, S1 ... Test signal creation data, S2 ... Test signal, S3 ... Read data, S4 ... Expected value data, S5
... switching signal creation data, S6 ... switching signal, PH ... timing signal, PD ... pattern data, CH ... timing switching control signal, φ ... high speed operation clock, FCH ... file switching signal, ADD ... address signal, PASS / FAI
L ... Pass / Fail data

Claims (2)

[Claims] 1. A test signal composed of address data for designating an address of an IC memory under test, data to be written to the designated address, a clock signal as a reference of operation, etc. is generated in accordance with a predetermined condition. Test signal generating means, IC read / write control means for writing data according to the test signal to the IC memory under test and reading the written data according to the address data, and read by the IC read / write control means. Path / shows the judgment result by comparing the selected data with the reference data
When a plurality of tests are performed on the IC memory under test according to different conditions as a series of test operations or a predetermined condition for different areas of the IC memory under test. A register file composed of a plurality of files capable of storing the pass / fail data output from the determining means for each condition or each area when a plurality of tests according to And an control unit for reading the pass / fail data stored in the register file and inspecting the electrical characteristics of the IC to be measured. 2. A test signal composed of address data for designating an address of an IC memory under test, data to be written at the designated address, a clock signal as an operation reference, etc. is generated in accordance with a predetermined condition. Test signal generating means, IC read / write control means for writing data according to the test signal to the IC memory under test and reading the written data according to the address data, and read by the IC read / write control means. Path / shows the judgment result by comparing the selected data with the reference data
A determination unit for outputting fail data, and a memory for fetching and storing the pass / fail data at an address designated by the address data, wherein a plurality of tests according to different conditions are performed on the IC memory under test. The pass / fail output from the determining means when a series of test operations is performed or when a plurality of tests according to a predetermined condition are performed as a series of test operations on different areas of the IC memory under test A fail memory that stores data for each condition or each area, and a control unit that reads the pass / fail data stored in the fail memory and inspects the electrical characteristics of the IC to be measured are provided. An IC test apparatus characterized in that