JP3215600B2 - IC test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC test apparatus for inspecting the electrical characteristics of an IC (integrated circuit), and more particularly to an IC test for easily checking test pattern data generated by a pattern generating means. Related to the device.

[0002]

2. Description of the Related Art In order to ship an IC whose performance and quality are guaranteed as a final product, it is necessary to extract all or a part of the IC product in each process of a manufacturing department and an inspection department and to inspect its electrical characteristics. There is. An IC test device is a device for inspecting such electrical characteristics. The IC test apparatus gives predetermined test pattern data to the IC under test, reads the output data of the IC under test, and determines whether there is any problem in the basic operation and function of the IC under test. The failure information is analyzed from the data and the electrical characteristics are inspected.

[0003] DC tests (D
C measurement test) and a function test (FC measurement test). For DC test, D
By applying a predetermined voltage or current from the C measuring means, it is checked whether there is any defect in the basic operation of the IC to be measured. On the other hand, in the function test, predetermined test pattern data is given to the input terminal of the IC under test from the pattern generating means, and the output data of the IC under test is read. It is to check whether or not.

FIG. 4 is a block diagram showing a schematic configuration of a conventional IC test apparatus. The IC test apparatus is roughly divided into a tester section 50 and an IC mounting apparatus 70. The tester unit 50 includes a control unit 51, a DC measurement unit 52, a timing generation unit 5
3. It comprises a pattern generating means 54, a pin control means 55, a pin electronics 56, a fail memory 57 and an input / output switching means 58. In the actual tester section 50,
There are various other constituent means, but only necessary parts are shown in this specification.

The tester unit 50 and the IC mounting device 70 are connected by signal lines including a plurality (m) of coaxial cables or the like corresponding to the total number of input / output terminals (m) of the IC mounting device 70. The connection relationship between the terminal and the coaxial cable is associated with each other by a relay matrix (not shown), and transmission of various signals is performed between a predetermined terminal and the coaxial cable. Note that there are physically as many signal lines as the number m of all input / output terminals of the IC mounting device 70.

The IC mounting device 70 includes a plurality of ICs to be measured.
71 is configured to be mounted on a socket. The input / output terminal of the IC 71 to be measured and the input / output terminal of the IC mounting device 70 are connected in one-to-one correspondence. For example, if the IC 71 to be measured having 28 input / output terminals is 1
In the case of the IC mounting device 70 capable of mounting zero ICs, a total of 28
It has zero input / output terminals.

The control means 51 controls the entire IC test apparatus,
It performs operations and management, and has a microprocessor configuration. Therefore, although not shown, it has a ROM for storing a system program, a RAM for storing various data, and the like. The control unit 51 includes a DC measurement unit 52, a timing generation unit 53, a pattern generation unit 5
4. It is connected to the pin control means 55 and the fail memory 57 via a bus (data bus, address bus, control bus) 65.

[0008] The control means 51 transmits the data for the DC test to D
A timing signal for starting a function test is output to the timing generation means 53, a pattern creation program is output to the pattern generation means 54, and expected value data and the like are output to the pin control means 55 to the C measurement means 52. In addition, the control means 51 outputs various data to respective components via a bus. Further, the control means 51 reads the test results (pass / fail data and DC data) from the fail memory 57 and the DC measurement means 52, performs various data processing and the like, analyzes the test data, and
71 is determined.

The DC measuring means 52 receives the DC test data from the control means 51 and performs a DC test on the IC 71 to be measured of the IC mounting device 70 based on the data. DC
The measuring means 52 starts a DC test by inputting a measurement start signal from the control means 51, and writes data indicating the test result into an internal register. When the writing of the test result data is completed, the DC measuring means 52 outputs an end signal to the control means 51. The data indicating the test result written in the internal register of the DC measuring means 52 is read by the control means 51 via the bus 65 and analyzed there. Thus, the DC test is performed. DC measurement means 5
2 designates reference voltages VIH and VI for the driver 63 of the pin electronics 56 and the analog comparator 64.
L, VOH, and VOL are output.

The timing generating means 53 outputs a predetermined clock to the pin control means 55, and outputs data from the data selector 59,
It controls the operation speed and the like of the formatter 60, the I / O formatter 61, and the comparator logic circuit 62. Therefore, the test signal S2 output from the formatter 60 to the pin electronics 56 and the I / O formatter 61
The output timing of the switching signal S6 output from the input / output switching unit 58 to the input / output switching unit 58 is also controlled according to the high-speed clock from the timing generation unit 53.

The pattern generating means 54 is provided with a pattern creating program (micro program) from the control means 51.
And outputs the pattern data PD based on the data to the data selector 59 of the pin control means 55. That is, the pattern generating means 54 outputs regular test pattern data PD by various arithmetic processes according to the pattern creation program. Such a method is called a program method. In addition to the program method, the same data as the data to be written to the IC to be measured is previously written in the internal memory (referred to as a pattern memory) in the pattern generating means 54, and is read out at the same address as the IC to be measured. There is a memory stored type which outputs irregular (random) pattern data (expected value data). However, even in this memory stored system, the generation of the address to be supplied to the IC to be measured is performed by a program system.

The pin control means 55 includes a data selector 59,
It comprises a formatter 60, an I / O formatter 61 and a comparator logic circuit 62. The data selector 59 is composed of a memory that stores various test signal creation data (address data / write data) S1, switching signal creation data S5, and expected value data S4, and stores the pattern data from the pattern generator 54. Input as an address, and test signal creation data S corresponding to the address.
1 and the switching signal creation data S5 are output to the formatter 60 and the I / O formatter 61, and the expected value data S4 is output to the comparator logic circuit 62.

The formatter 60 has a multi-stage configuration of flip-flop circuits and logic circuits. The formatter 60 processes test signal creation data (address data / write data) S1 from the data selector 59 to create a predetermined applied waveform. Then, it is used as a test signal S2 in the timing generator 53.
Is output to the driver 63 of the pin electronics 56 in synchronization with the timing signal from I / O formatter 6
1 also has a multi-stage configuration of a flip-flop circuit and a logic circuit, like the formatter 60, and processes the switching signal creation data S5 from the data selector 59 to create a predetermined applied waveform, which is used as the switching signal S6. The signal is output to the input / output switching means 58 in synchronization with the timing signal from the timing generation means 53. Comparator logic circuit 6
2 is a digital signal S3 from the analog comparator 64 of the pin electronics 56 and the data selector 59.
And the pass / fail data FD indicating the result of the comparison is compared with the expected value data S4 from the fail memory 57.
Output to

The pin electronics 56 comprises a plurality of drivers 63 and an analog comparator 64. The driver 63 and the analog comparator 64 are IC
One input terminal is provided for each input / output terminal of the mounting device 70, and one of them is connected via the input / output switching means 58. Input / output switching means 5
Numeral 8 switches the connection state between one of the driver 63 and the analog comparator 64 and the input / output terminal of the IC mounting device 70 in accordance with the switching signal S6 from the I / O formatter 61. That is, when the number of input / output terminals of the IC mounting device 70 is m, the driver 63,
The analog comparator 64 and the input / output switching means 58 are each composed of m pieces. However, when measuring a memory IC or the like, an analog comparator is not required for an address terminal, a chip select terminal, or the like, and thus the number of analog comparators and input / output switching means may be small.

The driver 63 is connected to input / output terminals of the IC mounting device 70, that is, signal input terminals such as an address terminal, a data input terminal, a chip select terminal, and a write enable terminal of the IC 71 to be measured via the input / output switching means 58. ,
The test signal S from the formatter 60 of the pin control means 55
Then, a high-level “H” or low-level “L” signal corresponding to 2 is applied, and a desired test pattern is written to the IC 71 to be measured. The analog comparator 64 is connected to the measured IC 7
1, a signal output from the data output terminal via the input / output switching means 58 is input and compared with the reference voltages VOH and VOL at the timing of the strobe signal from the control means 51, and the comparison result is set to a high level. It outputs to the comparator logic circuit 62 as a digital signal S3 of “PASS” or low level “FAIL”. Usually, the analog comparator 64 is composed of two comparators for the reference voltage VOH and the reference voltage VOL, but is omitted here.

The fail memory 57 stores pass / fail data FD output from the comparator logic circuit 62.
, And is configured by a RAM which has a storage capacity similar to that of the IC 71 to be measured and which can be read and written at any time. The fail memory 57 has a data input / output terminal fixedly corresponding to the data output terminal of the IC mounting device 70. For example, if the total number of input / output terminals of the IC mounting device 70 is 28
If the number is 0 and 160 of them are data output terminals, the fail memory 57 is constituted by a memory having the same or more data input terminals as the number of data output terminals. The pass / fail data FD stored in the fail memory 57 is read out by the control means 51, transferred to a data processing memory (not shown), and analyzed.

[0017]

In the above-described IC test apparatus, the pattern generating means 54 is controlled by the control means 51.
Since the pattern data is generated by a program method based on the pattern generating program from, the pattern generating means 54 reads the pattern data generated to confirm whether the pattern generating program is correctly described. it can. However,
Since the number of execution steps of the pattern creation program is very large, conventionally, the pattern creation program is reduced (the number of execution steps is reduced), and the pattern data generated by the pattern generation means 54 is accordingly controlled by the control means. By reading at 51 or directly using synchro, the contents of the program for pattern creation were checked to see if it was correctly described.

As described above, the pattern data can be easily read by reducing the actual pattern creation program. However, the number of execution steps of the reduced pattern creation program depends on the pattern creation used in the actual test. Is extremely small compared to the number of execution steps of the pattern creation program, and the relationship with various operation timings that occur during the execution of the actual pattern creation program differs from that during the actual operation. Has a problem that pattern data different from the case of operating is output, and accurate reading of the pattern data cannot be performed.

Therefore, conventionally, the pattern generating means 54 is operated based on an actual pattern creating program,
A trigger is generated in accordance with a specific step value or a register value, and the pattern data at a specific point is read by extracting the pattern data at the time when the trigger is generated. However, according to the method using the trigger, it is possible to easily confirm what pattern data is output at a specific step value or register value. However, the address position of the IC 71 to be measured and the position before and after the address position are determined. There is a problem that pattern data generated in several steps, that is, the relationship of pattern data generation order cannot be confirmed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and provides an IC test apparatus capable of easily confirming the occurrence state of pattern data in a predetermined address range without reducing the pattern data. The purpose is to:

[0021]

An IC test apparatus according to the present invention provides a test pattern data such as a designated address, write data to be written to the designated address, and expected value data to be read from the designated address. a pattern generating means for generating, if said pattern generating means
The test pattern data generated from the test
Input the test pattern data according to the input of the test pattern data.
Receiving data output from the test IC, and
From the pin control means for evaluating the
Enter generated by said test pattern data, the pattern check means for said specified address therein for temporarily storing said test pattern data in the case where there is a pre-set address range, the pattern check means in which reading the test pattern data stored equipped with a control means for displaying.

[0022]

The pattern confirmation means inputs test pattern data output from the pattern generation means. The test pattern data always includes the specified address. Therefore,
The pattern checking means determines whether or not the designated address included in the test pattern data is within a preset address range, and temporarily stores the test pattern data when the specified address is within the address range. I do. That is, by simply setting the address range in advance, the test pattern data output together with the designated address existing in the address range from the long test pattern data is taken into the pattern checking means, and temporarily stored. Is stored. The control means reads out the stored test pattern data and displays it, so that the test pattern data can be easily confirmed.

[0023]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a schematic configuration of an IC test apparatus according to the present invention. In FIG. 1, the same components as those in FIG. 4 are denoted by the same reference numerals, and the description thereof will be omitted. The difference between the IC test apparatus according to the present invention and the prior art shown in FIG. 4 is that the pattern data PD generated by the pattern generating means 54 is input, and only the pattern data PD in a predetermined address range is controlled from among them. This is the point that a pattern confirmation unit 66 that can output the data to the printer is newly provided.

The pattern checking means 66 is provided by the pattern selector 54 to the data selector 59 of the pin controller 55.
Is input in parallel, and it is determined whether or not the address signals (X address and Y address) in the pattern data PD are within a predetermined address range. Is output to the control means 51 via the bus 65.

FIG. 2 is a diagram showing the detailed configuration of the pattern confirmation means 66. The pattern confirmation means 66 includes an X mask register 20, an X address maximum value designation register 21,
X address minimum value designation register 22, X address comparator 23, Y mask register 24, Y address maximum value designation register 25, Y address minimum value designation register 26, Y address comparator 27, AND circuit 28, and history memory 29
Consists of The pattern confirmation means 66 captures the captured pattern data PD (address, expected value / applied data, R / W operation control signal, etc.) to the input terminal of the history memory 29, and stores the X address in the pattern data PD in the X mask register. At 20, the Y address is taken into the Y mask register 24 in parallel.

The X mask register 20 is a mask register for specifying an address which is not output to the X address comparator 23 among the X addresses. The bit corresponding to the address is set in advance by the control means 51. When the X address corresponding to the set bit is input, the operation is performed so that the X address is not output to the comparator 26. The Y mask register 24 performs the same operation for the Y address. The X address maximum value designation register 21 stores the maximum value of the X address, and the X address minimum value designation register 22 stores the minimum value of the X address.
When the X address passed through the X mask register 20 is equal to or less than the value stored in the X address maximum value designation register 21 and equal to or greater than the value stored in the X address minimum value designation register 22, the comparator 23 determines the high level as a determination result. A signal of "1" is output to the AND circuit 28. If the X address is out of this range, a signal of low level "0" is output to the AND circuit 28. That is, the X address maximum value designation register 2
1 and the comparator 23 limit the maximum value of the address, and the X address minimum value designation register 22 and the comparator 23 function to limit the minimum value of the address. Therefore, in the figure, the X address maximum value designation register 21 is displayed as XH limit,
The address minimum value designation register 22 is indicated as XL limit.

The Y address maximum value designation register (YH limit) 25 stores the maximum value of the Y address, and the Y address minimum value designation register (YL limit) 26 stores the minimum value of the Y address. The comparator 27 is a Y mask register 2
When the Y address that passed through No. 4 is equal to or less than the value stored in the Y address maximum value specifying register 25 and equal to or greater than the value stored in the Y address minimum value specifying register 26, a high level “1” signal is output as a determination result to the AND circuit When the Y address is out of this range, a low-level “0” signal is output to the AND circuit 28.

The AND circuit 28 includes the comparator 23 and the comparator 2
The logical product of both outputs of 7 is obtained and output to the history memory 29. That is, the AND circuit 28 outputs the X address and the Y address.
An active signal is output to the history memory 29 only when both the addresses pass through the X mask register 20 and the Y mask register 24 and both are within a predetermined address range. The history memory 29 stores the pattern data PD in 256
It is composed of a FIFO memory capable of storing data for each step. Therefore, the history memory 29 stores the pattern data PD in synchronization with the active signal from the AND circuit 28 only when the address is within a predetermined address range, and sequentially transfers the pattern data PD to the output terminal side. The pattern data PD output from the output terminal of the history memory 29 is taken into the control means 51 via the bus 65. The control means 51 displays the pattern data PD output from the history memory 29 on a display means or the like. At this time, the display means plots and displays the address data and the positional relationship on the screen, thereby facilitating visual data confirmation.

FIG. 3 is a diagram showing an operation example of how the pattern checking means of FIG. 2 determines an address range. In this example, the address of the IC 71 to be measured is 1
The case of megabit will be described. The X address is "0" to "1023", and the Y address is also "0" to "102".
3 ". At this time, the address “XH” is stored in the X address maximum value specification register 21, the address “XL” is stored in the X address minimum value specification register 22, the address “YH” is stored in the Y address maximum value specification register 25, and the Y address The minimum value designation register 26 stores an address “YL”. On the other hand, the X mask register 20 stores an address “X” larger than the address “XL” as shown in the figure.
A mask bit is set to mask an address in the range between "1" and "X2". When the above-described addresses are set in the respective registers of the pattern confirmation unit 66, the pattern generation unit 54 outputs the pattern data PD corresponding to the address of 1 megabit. Then, only the pattern data PD corresponding to the address of the portion corresponding to the hatched portion in FIG. The written pattern data PD is read by the control means 51 and displayed on the display means. Thus, the contents of the pattern data PD can be easily confirmed.

As described above, the pattern checking means 66 is newly provided as in the IC test apparatus of the present embodiment, and when the address in the pattern data is within a predetermined range, the pattern data is temporarily stored in the history memory 29. Since the data is stored and output to the control means 51, the pattern data PD in an arbitrary specified address range can be easily confirmed using a long pattern having a large number of execution steps as it is. . Also, by sampling and storing the pattern data in the history memory, the required time can be reduced. In the above-described embodiment, the case where the history memory 29 is configured by the FIFO memory has been described. However, if the operation speed is satisfied,
It goes without saying that the memory may be constituted by other memory.

[0031]

According to the present invention, there is an effect that the state of occurrence of pattern data in a predetermined address range can be easily confirmed without reducing the pattern data.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an IC test apparatus according to the present invention.

FIG. 2 is a diagram illustrating a detailed configuration of a pattern checking unit in FIG. 1;

FIG. 3 is a diagram showing an operation example of how the pattern checking means of FIG. 2 determines an address range.

FIG. 4 is a block diagram showing a schematic configuration of a conventional IC test apparatus.

[Explanation of symbols]

Reference numeral 50: tester unit, 51: control means, 52: DC measurement means, 53: timing generation means, 54: pattern generation means, 55: pin control means, 56: pin electronics, 57: fail memory, 58: input / output switching means , 5
9 Data selector, 60 Formatter, 61 I /
O formatter, 62 ... Comparator logic circuit, 6
3 ... Driver, 64 ... Analog comparator, 65 ... Bus, 66 ... Pattern checking means, 70 ... IC mounting device, 7
1: IC to be measured

Claims (2)

(57) [Claims] 1. A specified address, a pattern generating means for generating a test pattern data, such as expected value data would be read out from the write data and the specified address to be written to the designated address from the pattern generating means The generated test putter
Input the test pattern data to the IC under test.
The data output from the IC under test in response to
Receiving and evaluating the IC under test, and inputting the test pattern data generated by the pattern generating means, and setting the designated address in the test address data within a predetermined address range. An IC test apparatus comprising: a pattern confirmation unit that temporarily stores test pattern data; and a control unit that reads and displays the test pattern data stored in the pattern confirmation unit. 2. The pattern confirming means comprising: means for outputting an active signal when the designated address is within the address range; and a history memory for storing the test pattern data at the time of input of the active signal. 2. The IC test apparatus according to claim 1, wherein the IC test apparatus comprises: