JP2010002315A - Semiconductor testing device and method for testing dc characteristic thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor testing device capable of reducing the number of times of DC characteristic testing of a device to be tested and a time period for the testing. <P>SOLUTION: This semiconductor testing device is adapted to perform testing of a DC characteristic in such a manner that a plurality of parameter measurement units 31 are connected to a plurality of devices 2 to be tested via a relay switching circuit 10 in a pin electronics 1. In the semiconductor testing device, a CPU 4 chooses a measurement sequence of which the number of times of DC characteristic testing is minimized from measurement sequences obtained on the basis of pin structure data of a data storage device 5, the number of pins of each device 2 to be tested to which the parameter measurement units 31 are simultaneously connectable and the number of pins of devices 2 to be tested to which each of the parameter measurement units 31 is simultaneously connectable, and controls the relay switching circuit 10 on the basis of the chosen result. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor test apparatus that shortens a test time in a DC characteristic test.

In order to ship semiconductor integrated circuits such as LSIs and ICs as final products with guaranteed performance and quality, it is necessary to extract all or part of the semiconductor integrated circuits during the manufacturing and inspection processes and inspect their electrical characteristics. There is. The semiconductor test apparatus is an apparatus for inspecting the electrical characteristics of such a semiconductor integrated circuit.

  The semiconductor test equipment gives predetermined test pattern data to the device under test, analyzes defect information about the basic operation and function of the device under test from the output data of the device under test, and inspects the electrical characteristics. ing.

The DC characteristic test in the semiconductor test apparatus is performed in the basic operation of the device under test by applying a predetermined voltage or current from the DC measuring means to the input / output terminal of the device under test and measuring the voltage of the output terminal of the device under test. This is to inspect for defects.

FIG. 7 is a schematic configuration diagram showing a connection relationship among a device under test of a conventional semiconductor test apparatus, a DC unit, and a driver.

The DC unit 3 includes a plurality of parameter measurement units (also referred to as PMU (Parametric Measurement Unit)) 31 for performing voltage measurement, voltage application current measurement, current application voltage measurement, voltage application, current application, and the like for the device under test 2. A plurality of devices under test 2 are switched and connected via a plurality of pin electronics 1. A plurality of (usually several) parameter measurement units 31 are connected to each pin electronics 1.

In the pin electronics 1, the driver 11 gives a test signal to a predetermined pin of the device under test 2 connected via the output relay 13. Each driver comparator 12 includes a driver for supplying a test signal to the device under test 2 and a comparator for measuring the state of the signal output from the device under test 2 to determine pass / fail, and via the output relay 13 the device under test 2. Connected to a predetermined pin. The force terminal of each parameter measurement unit 31 and each pin of the device under test 2 are connected via a first force relay 14 for parameter measurement unit selection and a second force relay 15 for pin selection. Similarly, the sense terminal of each parameter measurement unit 31 and each pin of the device under test 2 are connected via a first sense relay 16 for parameter measurement unit selection and a second sense relay 17 for pin selection. The CPU 4 controls the overall operation of these relays 13-17.

In the above description, the output relay 13, the force relays 14 and 15, and the sense relays 16 and 17 constitute the relay switching circuit 10 that switches and connects the plurality of parameter measurement units 31 to the plurality of devices under test 2.

Next, the operation of the apparatus of FIG. 7 in the DC characteristic test will be described. In the case of voltage measurement, a command is sent from the CPU 4 to each relay corresponding to the measurement target pin, the output relay 13 and the force relays 14 and 15 are turned off, and the sense relays 16 and 17 are turned on. Measurement is performed. Similarly, in the case of voltage application current measurement, current application voltage measurement, voltage application, and current application, the output relay 13 is turned off, the force relays 14 and 15 and the sense relays 16 and 17 are turned on. Each application and measurement is performed.

  FIG. 8 is a specific example of the apparatus shown in FIG. 7 and is a block diagram illustrating the control operation of the measurement pin. The device under test 2 is composed of four devices under test DUTa to DUTd each having 8 pins, while the pin electronics 1 is composed of 8 cards P1 to P8, which are connected to 4 pins per card. , Connect in total (4 pins x 8 =) 32 pins.

  FIG. 9 is a pin configuration table associating the cards P1 to P8 of the pin electronics 1 with the pins of the device under test 2. P1 is 1 pin of DUTa, b (represented as 1a and 1b in FIG. 9, respectively) and 2 pins, P2 is 3 pins and 4 pins of DUTa, b, P3 is 5 pins and 6 pins of DUTa, b , P4 is on pins 7 and 8 of DUTa, b, P5 is on pins 1 and 2 of DUTc and d, P6 is on pins 3 and 4 of DUTc and d, P7 is on pins 5 and 6 of DUTc and d, P8 Are connected to pins 7 and 8 of DUTc and d, respectively.

  When the 16 parameter measuring units 31 are called PMU1 to PMU16, PMU1 is 1 pin of DUTa and DUTb, PMU2 is 2 pins of DUTa and DUTb, PMU3 is 3 pins of DUTa and DUTb, and PMU4 is DUTa. And PUT5 are connected to DUTa and DUTb 5 pins, PMU9 is connected to DUTc and DUTd 1 pin, and PMU16 is connected to DUTc and DUTd 8 pins.

  An example of operation when voltage applied current measurement is performed using the pin electronics 1 having the pin configuration as described above will be described below. However, voltage application current measurement and current application voltage measurement are usually performed one pin at a time because if two pins are measured simultaneously in the same device under test, the measured value may be affected.

  When measuring the voltage application current from pin 1 to pin 8, as shown in FIG. 10, in the first test T1, the P1 DUTa pin 1 is measured by PMU1, and the P5 DUTc pin 1 is measured by PMU9, and in the second T2 test. P1 DUTb 1 pin is measured by PMU1, P5 DUTd 1 pin is measured by PMU9 ... In the 16th T16, P4 DUTb 8 pin is measured by PMU8, P8 DUTd 8 pin is measured by PMU16. In this way, if measurement is performed in order from the 1st pin to the 8th pin, a total of 16 measurements are required.

  In the case where measurement is possible simultaneously, such as voltage measurement, current application, voltage application, etc., two or more pins can be measured or applied simultaneously in the same device under test.

  Prior art documents related to a semiconductor test apparatus designed to increase the speed of the DC test include the following.

Japanese Patent Laid-Open No. 08-043480

  However, in the conventional apparatus, since measurement is performed in order from the smallest pin, the number of measurements is large, and the test time of the DUT is long.

  An object of the present invention is to provide a semiconductor test apparatus capable of reducing the number of DC characteristic tests of a device under test and shortening a test time.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In a semiconductor test apparatus in which a plurality of parameter measurement units are connected to a plurality of devices under test via a relay switching circuit in pin electronics to test DC characteristics.
A data storage device for storing pin configuration data for associating the plurality of parameter measurement units with the pins of the plurality of devices under test;
Based on the pin configuration data from the data storage device, the number of pins of each device under test to which the parameter measurement unit can be connected simultaneously, and the number of pins of the device under test to which the parameter measurement units can be connected simultaneously And a first CPU that controls the relay switching circuit based on a measurement sequence that minimizes the number of DC characteristic tests.

The invention according to claim 2
The semiconductor test apparatus according to claim 1,
The number of pins of each device under test to which the parameter measurement unit can be connected simultaneously and the number of pins of the device under test to which the parameter measurement unit can be connected simultaneously are set to 1, respectively.

The invention described in claim 3
The semiconductor test apparatus according to claim 1 or 2,
The pin electronics include the parameter measurement unit, the first CPU, and the data storage device.

The invention according to claim 4
The semiconductor test apparatus according to claim 3,
Pin configuration data from each data storage device of the plurality of pin electronics, the number of pins of each device under test to which the parameter measurement unit can be connected simultaneously, and the device under test to which the parameter measurement unit can be connected simultaneously A second CPU for obtaining a minimum of the number of DC characteristic tests among the measurement sequences obtained based on the number of pins;
Based on the measurement sequence obtained by the second CPU, the first CPU controls the relay switching circuit in each pin electronics.

The invention according to claim 5
In a DC characteristic test method of a semiconductor test apparatus in which a plurality of parameter measurement units are connected to a plurality of devices under test via a relay switching circuit in pin electronics to test a DC characteristic.
Pin configuration data for associating the plurality of parameter measurement units with the pins of the plurality of devices under test, the number of pins of each device under test to which the parameter measurement units can be connected simultaneously, and the parameter measurement units simultaneously connected Selecting a measurement sequence obtained based on the number of possible pins of the device under test that minimizes the number of DC characteristic tests;
And a step of controlling the relay switching circuit based on the selection result.

The invention described in claim 6
In the DC characteristic test method of the semiconductor test apparatus according to claim 5,
The number of pins of each device under test to which the parameter measurement unit can be connected simultaneously and the number of pins of the device under test to which the parameter measurement unit can be connected simultaneously are set to 1, respectively.
.

The invention described in claim 7
In the DC characteristic test method of the semiconductor test apparatus according to claim 5,
Pin configuration data from each data storage device of the plurality of pin electronics, the number of pins of each device under test to which the parameter measurement unit can be connected simultaneously, and the device under test to which the parameter measurement unit can be connected simultaneously Obtaining a minimum of the number of DC characteristic tests among the measurement sequences obtained based on the number of pins of
Each of the pin electronics controls the relay switching circuit based on the measurement sequence.

  As is apparent from the above description, according to the present invention, a semiconductor test apparatus in which a plurality of parameter measurement units are connected to a plurality of devices under test via a relay switching circuit in pin electronics to test DC characteristics. , A data storage device for storing pin configuration data for associating the plurality of parameter measurement units with the pins of the plurality of devices under test, pin configuration data from the data storage device, and the parameter measurement unit can be connected simultaneously. Among the measurement sequences obtained based on the number of pins of each device under test and the number of pins of the device under test to which the respective parameter measurement units can be connected simultaneously, the number of times of the DC characteristic test is minimized. And a first CPU for controlling the relay switching circuit based on Reducing the number of DC characteristic test of the device, it is possible to shorten the test time.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a configuration block diagram showing an example of a semiconductor test apparatus according to an embodiment of the present invention. 7 that are the same as those in FIG. The difference from FIG. 7 is that a data storage device 5 is added.

The data storage device 5 includes pin configuration data for associating a plurality of parameter measurement units 31 with pins of a plurality of devices under test 2, and each of the devices under test to which the parameter measurement unit 31 of the DC characteristic test target pins can be connected simultaneously. The number of pins of the device 2 and the number of pins of the device under test 2 to which the parameter measuring units 31 can be connected simultaneously are stored.

  The CPU 4 constitutes a first CPU and controls the relay switching circuit 10 based on the pin configuration data of the data storage device 5 so that the number of DC characteristic tests is minimized.

The operation of the apparatus shown in FIG. 1 will be described below. The basic operation of the relay during the DC characteristic test is the same as in the prior art.

The pin configuration of each card of the pin electronics 1 and the number of pins of each device under test 2 to which the parameter measurement unit 31 can be simultaneously connected and the parameter measurement unit 31 are simultaneously stored in the data storage device 5 in advance. The number of pins of the device under test 2 that can be connected is written. When the DC characteristic test mode is started, the CPU 4 accesses the data storage device 5 and reads out each data. The CPU 4 reads the pin configuration data read from the data storage device 5 and the number of pins of each device under test 2 to which the parameter measurement unit 31 of the DC characteristic test target pin can be connected at the same time and the parameter measurement unit 31 at the same time. Of the connection combinations obtained based on the possible number of pins of the device under test 2, the connection combination that minimizes the number of DC characteristic tests is selected, and the selection result is written in the data storage device 5 as a measurement sequence. When the DC characteristic test is started, the CPU 4 accesses the data storage device 5, controls the relay switching circuit 10 based on the above-described measurement sequence, and performs a DC characteristic test on the measurement target pins of each device under test 2.

Next, measurement pin control will be described using a specific example.

FIG. 2 is a specific example of the apparatus shown in FIG. 1, and is a block diagram showing a configuration in which the pin configuration of the pin electronics 1 is the same as that of the conventional example shown in FIGS. When the voltage application current measurement from pin 1 to pin 8 is performed, the CPU 4 determines the number of pins of each device under test 2 to which the parameter measurement unit 31 can be connected simultaneously and the device under test 2 to which each parameter measurement unit 31 can be connected simultaneously. The connection combination that minimizes the number of DC characteristic tests is selected under the connection condition where the number of pins is 1, and the result is written in the data storage device 5 as a measurement sequence shown in FIG.

Based on the measurement sequence read from the data storage device 5, the CPU 4 performs a DC characteristic test with the smallest number of measurements. That is, in the first test T1, the P1 DUTa pin 1 is measured by the PMU1, the P2 DUTb pin 3 is the PMU3, the P5 DUTc pin 1 is the PMU9, and the P6 DUTd pin 3 is the PMU11. Then, P1 DUTb 1 pin is PMU1, P2 DUTa 3 pin is PMU3, P5 DUTd 1 pin is PMU9, P6 DUTc 3 pin is PMU11 ... 8th time T8, P3 DUTb PUT3 6 pins are measured by PMU6, 8 pins of P4 DUTa are measured by PMU8, 6 pins of DUTd of P7 are measured by PMU14, 8 pins of DUTc of P8 are measured by PMU16, and a total of 8 measurements are completed.

In the above specific example, as shown in FIG. 9, the case where the card of the pin electronics 31 and the pins of the device under test 2 are regularly associated with each other has been shown. In order to avoid cross wiring in pattern wiring between connectors on a board (not shown), there is a case where it is not possible to make regular correspondence.

FIG. 4 is a diagram for illustrating a pin configuration of the second specific example showing a case where pins are allocated so that there is no regularity in this way. However, the connection with the parameter measurement unit 31 is the same as in the case of FIG. Even in such a connection condition, by obtaining the measurement sequence in the same manner as described above, the test can be performed with the minimum number of measurements as shown in the measurement sequence of FIG. That is, in the first test T1, the P3 DUTa 2 pin is measured by the PMU5, the P4 DUTc 2 pin is measured by the PMU8, the P7 DUTd 4 pin is measured by the PMU13, and the P8 DUTb 1 pin is measured by the PMU15. Then, the P1 DUTb 4 pin is PMU1, the P2 DUTa 3 pin is PMU3, the P5 DUTc 1 pin is PMU9, the P6 DUTd 2 pin is PMU12, and the 8th T8 is P1 DUTb. Pin 5 is measured by PMU1, P2 DUTa 8 pin is PMU4, P5 DUTc 8 pin is measured by PMU10, P6 DUTd 8 pin is measured by PMU11, and a total of 8 measurements are completed.

As is clear from the above, according to the semiconductor test apparatus having the above-described configuration, the number of measurements can be reduced as compared with the prior art in any pin configuration, and the test time can be greatly shortened.

Note that the pin configuration of the pin electronics 1, the configuration of the DC unit 3, and the measurement order of the DC characteristic test described here are examples, and of course, if the pin configuration of the pin electronics 1 and the configuration of the DC unit 3 change. The measurement order also changes.

In the above specific example, the CPU 4 determines the number of pins of each device under test 2 to which the parameter measurement unit 31 can be connected simultaneously and the device under test 2 to which each parameter measurement unit 31 can be connected simultaneously. The connection combination that minimizes the number of DC characteristic tests is selected under the condition that the number of pins of each is 1, but the pin of each device under test 2 to which the parameter measurement unit 31 can be connected simultaneously is selected. The number and the number of pins of the device under test 2 to which each parameter measurement unit 31 can be connected simultaneously can be any number depending on the pin configuration of the pin electronics 1 and the configuration of the DC unit 3. For example, in the case of voltage measurement that allows simultaneous measurement, several pins can be measured simultaneously within the same DUT as long as the hardware configuration is within the limit. Even in these cases, the CPU 4 can select a connection combination that minimizes the number of DC characteristic tests.

In the above embodiment, the number of pins of each device under test 2 to which the parameter measurement unit 31 can be connected simultaneously and the number of pins of the device under test 2 to which each parameter measurement unit 31 can be connected simultaneously. The number may be stored in a memory or register other than the data storage device 5, or may be input from the outside.

FIG. 6 is a configuration block diagram showing a second example of the semiconductor test apparatus according to the embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same symbols, and redundant description is omitted.

Unlike FIG. 1, the parameter measurement unit 31a, the CPU 4a constituting the first CPU, and the data storage device 5a are built in the pin electronics 1a. Also, the pin configuration information provided from each data storage device 5a of the plurality of pin electronics 1a and the parameter measurement unit 31 can be simultaneously connected by an external main CPU (not shown) that constitutes the second CPU in advance. Based on the number of pins of each device under test 2 and the number of pins of the device under test 2 to which each parameter measurement unit 31 can be connected simultaneously, a DC characteristic test sequence that minimizes the number of DC characteristic test measurements is obtained. The contents corresponding to each pin electronics 1a are written in each data storage device 5a. When the measurement is started, the CPU 4a in each pin electronics 1a accesses the data storage device 5a in its own pin electronics 1a and sends a command to each parameter measurement unit 31a and the relay switching circuit 10 in order according to the measurement sequence. Perform the test. Other operations are the same as those in FIG.

According to the semiconductor test apparatus configured as described above, the effect of the case of FIG. 1 is produced, and the wiring to the parameter measurement unit 31a and the relay switching circuit 10 is performed in the pin electronics 1a, thereby reducing the wiring cost. be able to.

It is a block diagram of the configuration of a semiconductor test apparatus showing an embodiment of the present invention. 1 is a configuration block diagram of a semiconductor test apparatus showing a specific example of the apparatus. It is operation | movement explanatory drawing which shows the example of a measurement sequence in the apparatus of FIG. It is a figure for showing the pin structure of the 2nd example in the apparatus of FIG. It is operation | movement explanatory drawing which shows the example of a measurement sequence of the 2nd specific example in the apparatus of FIG. It is a block diagram of the configuration of a semiconductor test apparatus showing a second embodiment of the present invention. It is a block diagram which shows the example of the conventional semiconductor test apparatus. 7 is a configuration block diagram showing a specific example of the apparatus. 8 is a diagram for showing the pin configuration of the device. It is operation | movement explanatory drawing which shows the example of a measurement sequence of the apparatus of FIG.

Explanation of symbols

1,1a pin electronics 2 device under test 4,4a CPU
5, 5a Data storage device 10 Relay switching circuit 31, 31a Parameter measurement unit

Claims (7)

In a semiconductor test apparatus in which a plurality of parameter measurement units are connected to a plurality of devices under test via a relay switching circuit in pin electronics to test DC characteristics.
A data storage device for storing pin configuration data for associating the plurality of parameter measurement units with the pins of the plurality of devices under test;
Based on the pin configuration data from the data storage device, the number of pins of each device under test to which the parameter measurement unit can be connected simultaneously, and the number of pins of the device under test to which the parameter measurement units can be connected simultaneously And a first CPU for controlling the relay switching circuit based on the measurement sequence obtained by the minimum number of DC characteristic tests. 2. The number of pins of each device under test to which the parameter measurement unit can be connected simultaneously and the number of pins of the device under test to which each parameter measurement unit can be connected simultaneously are set to 1, respectively. The semiconductor test apparatus described.   3. The semiconductor test apparatus according to claim 4, wherein the parameter measurement unit, the first CPU, and the data storage device are built in the pin electronics. Pin configuration data from each data storage device of the plurality of pin electronics, the number of pins of each device under test to which the parameter measurement unit can be connected simultaneously, and the device under test to which the parameter measurement unit can be connected simultaneously A second CPU for obtaining a minimum of the number of DC characteristic tests among the measurement sequences obtained based on the number of pins;
4. The semiconductor test apparatus according to claim 3, wherein the first CPU controls the relay switching circuit in each pin electronics based on a measurement sequence obtained by the second CPU. In a DC characteristic test method for a semiconductor test apparatus in which a plurality of parameter measurement units are connected to a plurality of devices under test via a relay switching circuit in pin electronics to test DC characteristics.
Pin configuration data for associating the plurality of parameter measurement units with the pins of the plurality of devices under test, the number of pins of each device under test to which the parameter measurement units can be connected simultaneously, and the parameter measurement units simultaneously connected Selecting a measurement sequence obtained based on the number of possible pins of the device under test that minimizes the number of DC characteristic tests;
And a step of controlling the relay switching circuit based on the selected measurement sequence. 6. The number of pins of each device under test to which the parameter measurement unit can be connected simultaneously and the number of pins of the device under test to which the parameter measurement unit can be connected simultaneously are set to 1, respectively. A method for testing a DC characteristic of the semiconductor test apparatus described. Pin configuration data from each data storage device of the plurality of pin electronics, the number of pins of each device under test to which the parameter measurement unit can be connected simultaneously, and the device under test to which the parameter measurement unit can be connected simultaneously Obtaining a minimum of the number of DC characteristic tests among the measurement sequences obtained based on the number of pins of
7. The method for testing a DC characteristic of a semiconductor test apparatus according to claim 5, further comprising the step of controlling each of the pin electronics based on the measurement sequence.

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