JPH05126914A - Ic testing device - Google Patents

Abstract

PURPOSE:To easily generate pattern data for testing even to an IC having a gigantic gate scale without increasing the capacity of a pattern memory itself constituted of an expensive SRAM from which data can be read out at a high speed. CONSTITUTION:A pattern generating means 14 generates desired pattern data by successively reading out data from a pattern memory 14c which temporarily stores pattern data to be used as a reference for generating the testing signal of an IC 25 to be measured. An auxiliary pattern data storing means 15 stores a larger number of kinds of pattern data than the pattern memory 14c does. Therefore, even when the IC 25 to be measured is changed and the pattern data corresponding to the IC 25 do not exist in the generating means 14, the means 14 can generate the pattern data corresponding to the IC 25, because a transfer control means 11b selects the pattern data corresponding to the IC 25 out of the pattern data stored in the auxiliary storing means 15 and transfers the selected data to the memory 14c.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC tester for inspecting the electrical characteristics of an IC (integrated circuit), and more particularly to a device under test I.
The pattern generating means for generating the test pattern data as a reference for creating the C test signal is improved by I
C test equipment.

[0002]

2. Description of the Related Art In order to ship an IC whose performance and quality are guaranteed as a final product, it is necessary to extract all or part of the IC product in each process of the manufacturing department and the inspection department and inspect its electrical characteristics. There is. The IC test device is a device for inspecting such electrical characteristics. The IC tester gives a predetermined test pattern data to the IC to be measured, reads the output data of the IC to be measured thereby, and outputs whether the basic operation or function of the IC to be measured has no problem. The failure information is analyzed from the data and the electrical characteristics are inspected.

The test in the IC test equipment is a direct current test (D
It is roughly divided into a C measurement test) and a function test (FC measurement test). For the DC test, use the D
By applying a predetermined voltage or current from the C measuring means, it is inspected whether or not the basic operation of the IC to be measured is defective. On the other hand, in the function test, given pattern data for the test is given to the input terminal of the IC to be measured from the pattern generating means, and the output data of the IC to be measured is read to check whether the basic operation and function of the IC to be measured are satisfactory. It is something to inspect.

[0004]

The pattern generating means of the conventional IC test apparatus must generate test pattern data corresponding to each type and type of IC to be measured. It has a built-in pattern memory that stores dozens of types of test pattern data corresponding to the type and format of the measurement IC. Then, the pattern generating means selectively reads out the desired test pattern data from the plurality of test pattern data stored in the pattern memory according to the type and format of the IC to be measured. It has occurred. Further, since the pattern memory needs to read the test pattern data under the test condition of the IC to be measured and send it directly to the IC to be measured, it is configured by an SRAM capable of high-speed reading.

However, since the scale of the gate of the IC has expanded recently, the capacity of the test pattern data also becomes enormous, and for example, the number of gates is 10K.
About 200K words, and about 20K about 250K
In the case of 25K words, about 300K words of test pattern data are required. For an IC having 100K gates, about 1M words of test pattern data are required. Therefore, in the conventional IC test apparatus, there is a gate-scale IC that cannot be tested due to the hardware limitation of the pattern memory.

In order to test an IC having a large gate scale as described above, the capacity of the pattern memory itself of the pattern generating means may be simply increased. However, as described above, the pattern memory is expensive and can be read at high speed. Since it is composed of the SRAM, the increase in the capacity directly reflects the increase in the cost, so that there is a problem in simply increasing the capacity of the pattern memory.

The present invention has been made in view of the above points, and can be applied to an IC having an enormous gate scale without increasing the capacity of the pattern memory itself which is composed of an expensive and high-speed readable SRAM. It is an object of the present invention to provide an IC test device equipped with a pattern generating means capable of easily generating test pattern data.

[0008]

According to the present invention, desired pattern data is obtained by sequentially reading data from a pattern memory in which pattern data serving as a reference for creating a test signal of an IC to be measured is temporarily stored. Pattern generating means for generating a pattern data, pattern data auxiliary storage means for storing pattern data of more kinds than the pattern memory can store, and the pattern data stored in the pattern data auxiliary storage means. And a transfer control means for transferring the pattern data corresponding to the IC to be measured to the pattern memory.

[0009]

The pattern generating means is for generating pattern data as a reference for creating the test signal of the IC to be measured. The pattern data is temporarily stored in the pattern memory in the pattern generating means. Therefore, the pattern generating means generates desired pattern data by sequentially reading the data from the pattern memory. The pattern data auxiliary storage means stores more kinds of pattern data than the pattern memory can store.
Specifically, when the storage capacity of the pattern memory is 1 M words, the pattern data auxiliary storage unit stores the pattern data for about 1 G words. Therefore, even if the IC to be measured is changed and the pattern data corresponding to the IC to be measured does not exist inside the pattern generating means, the transfer control means selects the pattern data from the pattern data stored in the pattern data auxiliary storage means. Since the pattern data corresponding to the IC to be measured is transferred to the pattern memory, the pattern generating means can generate the pattern data corresponding to the IC to be measured.

[0010]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing a schematic configuration of the entire IC test apparatus of the present invention. The IC testing device is roughly divided into a tester unit 10 and an IC mounting device 24. The tester unit 10 is composed of a control means 11, a DC measurement means 12, a timing generation means 13, a pattern generation means 14, a pattern data auxiliary storage means 15, a pin control means 16, a pin electronics 17, and a fail memory 18. The actual tester unit 10 has various other components, but only the necessary parts are shown in this specification.

The tester section 10 and the IC mounting device 24 are connected by signal lines composed of a plurality (m) of coaxial cables corresponding to the total number m of input / output terminals of the IC mounting device 24, and each terminal is connected. The connection relationships between the two are associated by a relay matrix (not shown), and various signals are transmitted between predetermined terminals. Note that this signal line is physically the IC mounting device 24.
There are the same number as the total number m of input / output terminals.

The IC mounting device 24 includes a plurality of ICs to be measured.
25 is configured so that it can be mounted in a socket. The input / output terminals of the IC to be measured 25 and the input / output terminals of the IC attachment device 24 are connected in a one-to-one correspondence with each other. For example, in the case of the IC mounting device 24 capable of mounting 10 ICs to be measured 25 having 28 input / output terminals, the total is 2
It will have 80 input / output terminals.

The control means 11 controls the entire IC testing apparatus,
It is used for operation and management and has a microprocessor configuration. Therefore, although not shown, it has a ROM for storing a system program, a RAM for storing various data, a data buffer for transferring data between the tester bus 23 and the internal CPU bus, and the like.

The control means 11 includes a DC measurement means 12, a timing generation means 13, a pattern generation means 14, a pattern data auxiliary storage means 15, a pin control means 16 and a fail memory 18, and a tester bus (data bus, address bus, control bus). It is connected via 23. The control means 11 sends data for DC test to the DC measuring means 12 and sends a signal for starting the function test to the timing generating means 1.
3, the pattern command data and the like for generating the test pattern data are output to the pattern generating means 14, and the expected value data and the like are output to the pin control means 16.

The control means 11 has a transfer control circuit for transferring to the pattern generation means 14 the pattern data required for the test among the pattern data in the pattern data auxiliary storage means 15. Details of this transfer control circuit are shown in FIG. In addition to this, the control means 11 outputs various data to the respective constituent elements via the tester bus. Further, the control means 11 reads the test results (fail data and DC data) from the fail memory 18 and the DC measurement means 12, performs various data processing, and analyzes the test data.

The DC measuring means 12 receives the DC test data from the control means 11 and performs a DC test on the IC 25 to be measured of the IC mounting device 24 based on the data. D
The C measuring means 12 starts the DC test by inputting the measurement start signal from the control means 11 and writes the test result data in the register. When the DC measurement means 12 finishes writing the test result data, the end signal is controlled by the control means 11
Output to. The test result data written in the register in the DC measuring means 12 is read by the control means 11 via the tester bus 23 and analyzed there. In this way, the DC test is performed. Further, the DC measuring means 12 applies the reference voltages VIH, VIL, VOH, and VOL to the driver 21 and the comparator 22 of the pin electronics 17.
Is output.

The timing generation means 13 outputs a predetermined clock to the pin control means 16 to control the operating speed of the formatter 19 and the comparator logic circuit 20. Therefore, the output timing of the test signal output from the formatter 19 to the pin electronics 17 is also controlled according to the high speed clock from the timing generating means 13.

The pattern generating means 14 is composed of a pattern memory which stores various test signal creation data P1 and expected value data P4, and the pattern command data from the control means 11 is inputted as an address, and based on it. The pattern data (test signal creation data P1 and expected value data P4) are output to the formatter 19 and the comparator logic circuit 20 of the pin control means 16.

The pattern data auxiliary storage means 15 is composed of a DRAM having a storage capacity about 1000 times that of the pattern memory of the pattern generation means 14, and stores test pattern data of various ICs. For example, when the capacity of the pattern memory is 1 M words, the capacity of the pattern data auxiliary storage unit 15 is 1 G words.
The transfer of the test pattern data from the pattern data auxiliary storage means 15 to the pattern memory in the pattern generation means 14 is performed by a dedicated transfer control circuit in the control means 11.

The pin control means 16 comprises a formatter 19 and a comparator logic circuit 20. The formatter 19 is composed of multi-stage flip-flop circuits and logic circuits, and variously processes the test signal generation data P1 from the pattern generating means 14 to synchronize a predetermined applied waveform with the timing signal from the timing generating means 13. And outputs it to the driver 21 of the pin electronics 17. The comparator logic circuit 20 includes the measured data P3 from the comparator 22 of the pin electronics 17 and the expected value data P4 from the pattern generating means 14.
Is compared and determined, and the determination result is output to the fail memory 18 as fail data.

The pin electronics 17 is composed of a plurality of drivers 21 and a comparator 22. One driver 21 and one comparator 22 are provided for each input / output terminal of the IC attachment device 24, and are connected via a signal line. That is, when the number of input / output terminals of the IC attachment device 24 is m, each of the driver 21 and the comparator 22 is composed of m. However, when measuring a memory IC or the like, since a comparator is not required for the address terminal, the number of comparators may be small.

The driver 21 responds to the test signal creation data P1 from the formatter 19 of the pin control means 16 in accordance with
The input / output terminal of the IC mounting device 24, that is, the measured IC 2
5, a test signal is applied to signal input terminals such as an address terminal, a data input terminal, a chip select terminal, and a write enable terminal, and a desired test pattern is written in the IC to be measured 25.

The comparator 22 inputs the measured data P3 output from a signal output terminal such as a data output terminal of the measured IC 25, and compares it with the reference voltages VOH and VOL at the timing of the strobe signal from the control means 11. ,
The comparison result (high level “1” or low level “0”) is output to the comparator logic circuit 20.

The fail memory 18 stores fail data output from the comparator logic circuit 20, and is composed of a RAM capable of reading and writing at any time having a storage capacity similar to that of the IC 25 to be measured. The fail memory 18 has a data input / output terminal that fixedly corresponds to the data output terminal of the IC attachment device 24. For example,
The total number of input / output terminals of the IC mounting device 24 is 280,
When 170 of them are data output terminals, the fail memory 18 is composed of a memory having data input terminals equal to or more than the number of data output terminals. The fail data stored in the fail memory 18 is read by the control means 11, transferred to a memory for data processing (not shown), and analyzed.

FIG. 2 is a diagram showing the detailed construction of the pattern generation means 14, the pattern data auxiliary storage means 15 and the transfer control circuit 11b for controlling the transfer of the pattern data between them in FIG. The control means 11 controls the data buffer 11 between the internal bus (not shown) and the tester bus 23.
a and a transfer control circuit 11b for controlling transfer of pattern data between the pattern memory 14c and the pattern auxiliary memory 15c.

The transfer control circuit 11b is a counter circuit 11
c, an oscillator 11d, and a shift register 11e. The counter circuit 11c is a CPU in the control means 11.
By inputting the transfer start signal TS from, the high speed clock of the oscillator 11d is counted and converted into a clock of a predetermined speed. Therefore, the clock speed can be freely changed by appropriately changing and setting the count value of the counter circuit 11c.

The shift register 11e is a counter circuit 11
3) Input a clock of a predetermined speed of c, sequentially shift it, and perform a predetermined logical operation on the shifted clock.
One transfer control signal is output. These three control signals are
A buffer control signal BC for controlling the operations of the data buffer 14a of the pattern generation means 14 and the data buffer 15a of the pattern data auxiliary storage means 15, the address counter circuit 14b of the pattern generation means 14, and the address counter circuit of the pattern data auxiliary storage means 15 Address count-up signal AU for counting up 15b
And a pattern write signal WE for writing pattern data in the pattern memory 14c of the pattern generating means 14.
Is.

The pattern generating means 14 has a data buffer 14a, an address counter circuit 14b and a pattern memory 14c. The data buffer 14a is a buffer for aligning the pattern data on the data bus of the tester bus 23 with the data input terminal of the pattern memory 14c, and is controlled by the buffer control signal BC of the transfer control circuit 11b. The address counter circuit 14b receives the address count-up signal AU of the transfer control circuit 11b, and counts up the address count-up signal AU to generate sequentially changing addresses of the pattern memory 14c. The address counter circuit 14b is connected to the address bus on the tester bus 23, and the initial address is set by the control means 11. Pattern memory 14
c inputs the count value of the address count circuit 14b to the address terminal and the pattern data on the data bus of the tester bus 23 to the data input terminal, and writes the pattern data according to the pattern write signal WE from the transfer control circuit 11b. To be crowded.

The pattern data auxiliary storage means 15 has a structure corresponding to the pattern generation means 14 and has a data buffer 15a, an address counter circuit 15b and a pattern auxiliary storage memory 14c. Data buffer 15a
Is a buffer for arranging the pattern data in the pattern auxiliary memory 15c on the data bus of the tester bus 23, and like the data buffer 14a, the transfer control circuit 1
It is controlled by the buffer control signal BC of 1b. The address counter circuit 15b receives the address count-up signal AU of the transfer control circuit 11b, and counts up the address count-up signal AU to generate sequentially changing addresses of the pattern auxiliary memory 15c.

The address counter circuit 15b is connected to the address bus on the tester bus 23, and the control means 11
By this, the initial address at which the pattern data to be transferred is located is set. Therefore, both the address counter circuits 14b and 15b change the address at the same timing. Pattern auxiliary memory 15c
Inputs the count value of the address count circuit 15b to the address terminal and outputs the pattern data corresponding to the address onto the data bus of the tester bus 23 via the data buffer 15a.

Next, the operation of this embodiment will be described. First,
The control means 11 sets an initial address in the address counter circuit 14b of the transfer destination pattern generation means 14 and the address counter circuit 15b of the transfer source pattern data auxiliary storage means 15, respectively.

When the setting of the initial address is completed, the CPU in the control means 11 outputs the transfer start signal TS to the counter circuit 11c. The counter circuit 11c counts the high speed clock of the oscillator 11d, converts it into a clock of a predetermined speed, and outputs it to the shift register 11e. The shift register 11e outputs three transfer control signals in the order of the address count-up signal AU, the buffer control signal BC, and the pattern write signal WE.

In response to the output of the address count-up signal AU, the address counter circuit 14b outputs the initial address to the pattern memory 14c, and at the same time, the address counter circuit 15b outputs the initial address to the pattern auxiliary memory 15.
output to c. At this time, the pattern auxiliary memory 15c is in the read mode and the pattern memory 14c is in the write mode.

In response to the output of the buffer control signal BC, the pattern data is read from the pattern auxiliary memory 15c and output on the data bus of the tester bus 23 via the data buffer 15a. Then, the pattern data on the data bus of the tester bus 23 is taken into the pattern memory 14c via the data buffer 14a. In response to the output of the pattern write signal WE, the pattern memory 14
Predetermined pattern data is written in c.

In this way, the pattern generating means stores desired pattern data from the pattern data auxiliary storage means in which a large number of pattern data are stored in advance in order to generate pattern data according to the type and format of the IC to be measured. , The pattern data can be generated during the IC test.

[0036]

According to the present invention, the test pattern data can be easily obtained even for an IC having a huge gate scale without increasing the capacity of the pattern memory itself which is composed of an expensive and high-speed readable SRAM. The effect is that it can occur.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of an entire IC test apparatus of the present invention.

FIG. 2 is a diagram showing a detailed configuration of a pattern generation unit, a pattern data auxiliary storage unit, and a control unit in FIG.

[Explanation of symbols]

10 ... Tester section, 11 ... Control means, 11a ... Data buffer, 11b ... Transfer control circuit, 11c ... Counter circuit,
11d ... Oscillator, 11e ... Shift register, 12 ... DC
Measuring means, 13 ... Timing generating means, 14 ... Pattern generating means, 14a ... Data buffer, 14b ... Address counter circuit, 14c ... Pattern memory, 15 ... Pattern data auxiliary storage means, 15a ... Data buffer, 15
b ... Address counter circuit, 15c ... Pattern auxiliary memory, 16 ... Pin control means, 17 ... Pin electronics, 18 ... Fail memory, 19 ... Data selector, 1
9 ... Formatter, 20 ... Comparator logic circuit,
21 ... Driver, 22 ... Comparator, 23 ... Tester bus, 24 ... IC mounting device, 25 ... IC to be measured

Claims (2)

[Claims] 1. A pattern generating means for generating desired pattern data by sequentially reading data from a pattern memory in which pattern data serving as a reference for creating a test signal of an IC to be measured is temporarily stored, Pattern data auxiliary storage means for storing pattern data of a number larger than the number that can be stored in the pattern memory, and to the IC to be measured from the pattern data stored in the pattern data auxiliary storage means. An IC test apparatus comprising: transfer control means for transferring corresponding pattern data to the pattern memory. 2. The IC test apparatus according to claim 1, wherein the pattern memory is an SRAM, and the pattern auxiliary storage unit is a DRAM.