JPH05273308A - Timing generating device for ic testing device - Google Patents

Abstract

PURPOSE:To adjust the outputting timing of data in a programmable state by generating a discriminating signal by delaying a period signal in a timing generating means. CONSTITUTION:A test period signal generator 1 generates a data preset signal PRE and outputs the signal PRE to a predelay circuit 3. The circuit 3 is provided with a plurality of FF circuits 11, 12-1n, and 40, a multiplexer 20, and a register 30. After a predetermined delay, the circuit 11 outputs the signal PRE to the next circuit 12 and multiplexer 20. The FF circuits 12-1n and 40 successively perform the same operation. The multiplexer 20 selects one out of the inputs from the circuit 11-1n in accordance with a select signal SD preset in the register 30 and outputs the selected input to a discriminating signal generator 4 through the FF circuit 40. Therefore, when the signal SD of the register 30 is changed, the delay time of the signal PRE inputted to the generator 4 can be adjusted. The generator 4 is actuated by the input and outputs a discriminating signal STRB generated at prescribed phase timing to a comparator logic circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC tester for inspecting the electrical characteristics of an IC (integrated circuit), and more particularly to synchronizing output timing between data output in the device in synchronization with a high speed clock. The present invention relates to a timing generation device for an IC test device.

[0002]

2. Description of the Related Art In order to ship an IC whose performance and quality are guaranteed as a final product, it is necessary to extract all or part of the IC product in each process of the manufacturing department and the inspection department and inspect its electrical characteristics. There is. The IC test device is a device for inspecting such electrical characteristics. The IC tester gives a predetermined test pattern data to the IC to be measured, reads the output data of the IC to be measured thereby, and outputs whether the basic operation or function of the IC to be measured has no problem. The failure information is analyzed from the data and the electrical characteristics are inspected.

The test in the IC test equipment is a direct current test (D
It is roughly divided into a C measurement test) and a function test (FC measurement test). For the DC test, use the D
By applying a predetermined voltage or current from the C measuring means, it is inspected whether or not the basic operation of the IC to be measured is defective. On the other hand, in the function test, given pattern data for the test is given to the input terminal of the IC to be measured from the pattern generating means, and the output data of the IC to be measured is read to check whether the basic operation and function of the IC to be measured are satisfactory. It is something to inspect.

FIG. 3 is a block diagram showing a schematic configuration of a conventional IC test apparatus. The IC test device is roughly divided into a tester section 50 and an IC mounting device 65. The tester unit 50 includes a control unit 51, a DC measurement unit 52, a timing generation unit 5
3, pattern generation means 54, pin control means 55, pin electronics 56 and fail memory 57. In the actual tester unit 50, various other components exist, but only necessary parts are shown in the present specification.

The tester section 50 and the IC mounting device 65 are connected by signal lines composed of a plurality (m) of coaxial cables corresponding to the total number m of input / output terminals of the IC mounting device 65, and each terminal is connected. The connection relationships between the two are associated by a relay matrix (not shown), and various signals are transmitted between predetermined terminals. Note that this signal line is physically the IC mounting device 65.
There are the same number as the total number m of input / output terminals.

The IC mounting device 65 includes a plurality of ICs to be measured.
66 is configured to be mounted in the socket. The input / output terminals of the IC 66 to be measured and the input / output terminals of the IC attachment device 65 are connected in one-to-one correspondence with each other. For example, in the case of the IC mounting device 65 capable of mounting 10 ICs to be measured 66 having 28 input / output terminals, the total is 2
It will have 80 input / output terminals.

The control means 51 controls the entire IC test apparatus,
It is used for operation and management and has a microprocessor configuration. Therefore, although not shown, the control means 51 is configured to have a ROM for storing a system program, a RAM for storing various data, and the like.

The control means 51 includes a DC measuring means 52, a timing generating means 53, a pattern generating means 54, a pin controlling means 55 and a fail memory 57, which are buses (data bus, data bus,
They are connected via an address bus and a control bus) 64. The control means 51 sends the DC test data to the DC measuring means 52, the function test start signal to the timing generating means 53, the test pattern generating data to the pattern generating means 54, and the expected value data to the pin. It outputs to each of the control means 55. In addition to this, the control means 51
Outputs various data to the respective constituent means via the bus 64. In addition, the control unit 51 reads the test results (fail data and DC data) from the fail memory 57 and the DC measurement unit 52, performs various data processing, and analyzes the test data.

The DC measuring means 52 receives the DC test data from the control means 51 and performs a DC test on the IC 66 to be measured of the IC mounting device 65 based on the DC test data. The DC measuring means 52 starts a DC test by inputting a measurement start signal from the control means 51, and writes the test result data into a register (not shown) in the DC measuring means 52. When the writing of the test result data is completed, the DC measuring means 52 outputs an end signal to the control means 51 this time.
The test result data written in the register in the DC measuring means 52 is read by the control means 51 via the bus 64,
It is analyzed there. In this way, the DC test is performed. Further, the DC measuring means 52 outputs the reference voltages VIH, VIL, VOH, and VOL to the driver 60 and the comparator 61 of the pin electronics 56.

The timing generating means 53 is an IC 6 to be measured.
The test cycle signal RATE which is the reference of the test cycle of No. 6 is output to the pattern generating means 54, and the test cycle signal RA
The waveform switching timing signal PHASE obtained by delaying TE by a predetermined timing phase difference is output to the pin control means 55. The pattern generation means 54 stores the pattern data from the control means 51 in advance, and outputs the pattern data PD to the data selector 58 of the pin control means 55 in synchronization with the test cycle signal RATE from the timing generation means 53. To do.

The pin control means 55 is a data selector 58,
It is composed of a formatter 59 and a comparator logic circuit 63. The data selector 58 is composed of a memory or the like that stores various test signal creation data P1 and expected value data P4. The pattern data PD from the pattern generating means 54 is input as an address, and the data is sent according to the address. Format tester 5 with test signal creation data P1
Output to 9.

The formatter 59 is composed of flip-flop circuits and logic circuits in multiple stages, and has a waveform switching timing signal PH from the timing generating means 53.
The test signal generation data P1 output from the data selector 58 is subjected to various processes in synchronization with ASE, and is output as a test signal P2 finally applied to the driver 60 of the pin electronics 56.

The pin electronics 56 is composed of a plurality of drivers 60 and a comparator 61. One driver 60 and one comparator 61 are provided for each input / output terminal of the IC mounting device 65, and are connected via a signal line. That is, when the number of input / output terminals of the IC attachment device 65 is m, each of the driver 60 and the comparator 61 is composed of m. However, when measuring a memory IC or the like, since a comparator is not required for the address terminal, the number of comparators may be small.

The driver 60 responds to the applied waveform P2 output from the formatter 59 of the pin control means 55 according to I
The input terminal of the C attachment device 65, that is, the address terminal of the IC to be measured 66, the data input terminal, the chip select terminal,
Test signal P2 is applied to the signal input terminals such as the write enable terminal
Is applied to write a desired test pattern to the IC 66 to be measured.

The comparator 61 receives the output data output from the signal output terminal such as the data output terminal of the IC 66 to be measured, and inputs it to the reference voltage VO from the DC measuring means 52.
H and VOL, and the comparison result (high level “1”
Alternatively, the low level “0”) is output to the comparator logic circuit 63 as the measured data P3.

The delay circuit 62 outputs the waveform switching timing signal PHASE from the timing generation means 53 to the time corresponding to the system timing (the test signal P2 processed by the formatter 59 according to the input of the waveform switching timing signal PHASE is the driver 60, IC 66 to be measured
And a time required for passing through the comparator 61) to delay the judgment signal (strobe signal) STR.
B is output to the comparator logic circuit 63, and is composed of a flip-flop circuit and a logic circuit that are configured in multiple stages.

The comparator logic circuit 63 outputs the measured data P3 (high level "1" or low level "0") output from the comparator 61 of the pin electronics 56 to the determination signal (strobe signal) STRB from the delay circuit 62. The fail memory 5 is latched at a timing and compared with the expected value data P4 from the data selector 58 to make a decision.
Output to 7. In addition, the comparator logic circuit 63
Is a fail stop signal FS corresponding to the result of the comparison judgment.
Is output to the pattern generating means 54.

The fail memory 57 stores the fail data FD output from the comparator logic circuit 63, and is composed of a RAM that has a storage capacity similar to that of the IC 66 to be measured and is readable and writable at any time. The fail memory 57 has a data input / output terminal that fixedly corresponds to the data output terminal of the IC attachment device 65. For example, when the total number of input / output terminals of the IC attachment device 65 is 280 and 163 of them are data output terminals, the fail memory 57 has the same or more data as the number of data output terminals. It is composed of a memory having an input terminal. The fail data FD stored in the fail memory 57 is read by the control means 51, transferred to a data processing memory (not shown), and analyzed. In this way, the function test is performed.

[0019]

In the IC tester as described above, the test signal generation data P1 output from the data selector 58 is converted by the formatter 59 into a predetermined test signal P2 at the timing of the waveform switching timing signal PHASE. It is processed and applied to the IC 66 to be measured on the IC attachment device 65 via the driver 60.
Then, the measured data P3 output from the data output terminal or the like of the measured IC 66 by the application of the test signal P2 is transmitted through the comparator 61 to the comparator logic circuit 63.
Entered in. That is, the test signal creation data P1 output from the data selector 58 is the formatter 59,
It passes through a test data path consisting of the driver 60, the IC to be measured 66, and the comparator 61, and is finally input to the comparator logic circuit 63 as the data to be measured P3.

The data selector 58 outputs the test signal creation data P1 and the expected value data P4 to the formatter 59 and the comparator logic circuit 63 at the same timing, but the test signal creation data P1 passes through the test data path as described above. Since the measured data P3 is input to the comparator logic circuit 63 after that, the measured data P3
Is a signal whose timing is significantly delayed with respect to the waveform switching timing signal PHASE. Therefore, the comparator logic circuit 63 cannot obtain accurate data even if the measured data P3 is latched at the same timing as the waveform switching timing signal PHASE. Therefore, in the conventional IC test apparatus, a delay circuit 62 is provided between the timing generation means 53 and the comparator logic circuit 63,
In the delay circuit 62, the waveform switching timing signal PHA
SE is delayed by the same amount as the test data path described above, and it is applied to the strobe signal ST of the comparator logic circuit 63.
Input as RB.

However, since the formatter 59 has passed through about 25 logic circuits from the input of the waveform switching timing signal PHASE to the output of the test signal P2, the formatter 59 also passes through the delay circuit 62.
There is a problem that the same number of logic circuits and flip-flop circuits as the logic circuit 9 and flip-flop circuits of 9 must be provided.

Further, since the delay time of the delay circuit 62 is determined by the number of stages of the logic circuit and the flip-flop circuit forming the delay circuit 62, the propagation delay time (round trip delay) of the test data path is changed by changing the system configuration of the IC test apparatus. There is a problem that the circuit configuration itself of the delay circuit 62 must be changed when the time) changes.

The present invention has been made in view of the above-mentioned points, and the timing generator of the IC test apparatus capable of adjusting the data output timing in a programmable manner without providing an external dedicated timing adjusting means. The purpose is to provide.

[0024]

SUMMARY OF THE INVENTION A timing generator for an IC test apparatus according to the present invention comprises a periodic signal generating means for generating a signal of a predetermined period based on a clock signal, and the periodic signal inputted to the timing generator. Also includes first timing signal generating means for generating a timing signal delayed by a predetermined timing phase difference, delay means for delaying the periodic signal by a time corresponding to an integral multiple of the cycle of the clock signal, and this delay means. Second timing signal generating means for inputting the delayed periodic signal and generating a timing signal delayed by a predetermined timing phase difference from the input timing.

[0025]

The periodic signal generating means generates a signal having a predetermined period based on the clock signal. The first timing signal generating means inputs the periodic signal and generates a timing signal delayed from the input timing by a predetermined timing phase difference. The conventional timing generator is composed of the periodic signal generating means and the first timing signal generating means. The first timing generating means can delay the periodic signal by a predetermined timing phase difference, but cannot delay the time required for passing through the test data path including the formatter, the driver, the IC to be measured and the comparator. ..

Therefore, in the present invention, delay means for delaying the periodic signal by a time corresponding to an integral multiple of the period of the clock signal, and the periodic signal delayed by the delay means are input,
Second timing signal generating means for generating a timing signal delayed by a predetermined timing phase difference from the input timing is newly provided. Therefore, the delay means delays the data by the time required to pass through the test data path, and the second timing signal generating means further delays the delayed signal by a predetermined timing phase difference and outputs the delayed signal. This allows the timing generator to adjust the data output timing in a programmable manner.

[0027]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. FIG. 2 is a block diagram showing a schematic configuration of an IC test apparatus that employs the timing generator according to the present invention. In FIG. 2, the same components as those in FIG. 3 are designated by the same reference numerals, and the description thereof will be omitted. The embodiment of FIG. 2 is different from the conventional one in that the timing generation means 5 is used.
The delay circuit 6 that delays the waveform switching timing signal PHASE of No. 3 by a predetermined time and outputs it as the strobe signal STRB to the comparator logic circuit 63.
2 is omitted, and the timing generating means 53a directly outputs the strobe signal STRB to the comparator logic circuit 63 in addition to the waveform switching timing signal PHASE.

FIG. 1 is a diagram showing a detailed structure of the timing generating means 53a of FIG. In the figure, the test period signal generator 1 and the waveform switching timing signal generator 2 are
It also exists in the conventional timing signal generating means 53.

The test cycle signal generator 1 operates in response to the input of the clock signal CLOCK having a predetermined frequency, and the test cycle signal RATE serving as a reference of the test cycle of the IC 66 to be measured preset by the control means 51 and this test. Data preset signal PR synchronized with periodic signal RATE
Generate E. The test cycle signal RATE is fetched by the pattern generating means 54 as in the conventional case, and the data preset signal PRE is used as the first stage flip-flop circuit 11 of the waveform switching timing signal generator 2 and the pre-delay circuit 3.
It is taken into the D terminal of.

The waveform switching timing signal generator 2 is
It outputs a plurality of waveform switching timing signals PHASE having different phase timings, and operates in response to the input of a clock signal CLOCK having a predetermined frequency.
Data preset signal PRE from test cycle generator 1
Is input to output a waveform switching timing signal PHASE having a predetermined phase timing to the flip-flop circuit 59.

Conventionally, two to four signals are selected from a plurality of waveform switching timing signals PHASE output from the waveform switching timing signal generator 2, and the selected waveform switching timing signal PHASE is used as a dedicated delay circuit. In 62, the signal is delayed by the time corresponding to the system timing of the IC test apparatus (the test data path consisting of the formatter 59, the driver 60, the IC 66 to be measured, and the comparator 61) and output to the comparator logic circuit 63.

In this embodiment, a pre-delay circuit 3 and a decision signal generator 4 are newly provided in the timing signal generating means 53a, and the data preset signal PRE of the test period signal generator 1 is also provided in the timing signal generating means 53a. I tried to output it.

The pre-delay circuit 3 is composed of a plurality (n) of flip-flop circuits 11, 12, 13 to 1n, 40, a multiplexer 20 and a register 30, and a data preset signal PRE from the test cycle signal generator 1.
Is delayed by a predetermined time and is output to the determination signal generator 4.

The flip-flop circuit 11 inputs the data preset signal PRE from the test cycle signal generator 1 to the D terminal and the high speed clock CLOCK to the clock terminal CK, and outputs the data preset signal PRE according to the input timing of the high speed clock CLK. The signal is output to the flip-flop circuit 12 of the next stage and the first input terminal M1 of the multiplexer 20. The flip-flop circuit 12 inputs the data preset signal PRE from the flip-flop circuit 11 of the previous stage to the D terminal, and in accordance with the input timing of the high-speed clock CLK, the flip-flop circuit 13 and the second stage of the multiplexer 20 of the next stage. Output to the input terminal M2. Thereafter, the flip-flop circuits 13 to 1n similarly output the data preset signal PRE to the flip-flop circuit of the next stage and the input terminals M3 to Mn of the multiplexer 20.

The register 30 outputs the selection signal SD previously written by the control means 51 to the selection terminal SEL of the multiplexer 20. The multiplexer 20 inputs the output Q from each of the flip-flop circuits 11 to 1n, and selectively outputs one of them from the Z terminal to the flip-flop circuit 40 according to the selection signal SD input to the selection terminal SEL. To do. The flip-flop circuit 40 inputs the data preset signal selectively output from the multiplexer 20 to the D terminal and outputs it to the determination signal generator 4 in accordance with the input timing of the high speed clock CLOCK.

Therefore, by appropriately changing the selection signal SEL written in the register 30, the multiplexer 20 is made to operate in the plurality of flip-flop circuits 11.
1n of which output Q of the flip-flop circuit is finally output to the flip-flop circuit 40 as the data preset signal PRE, that is, of the flip-flop circuit through which the data preset signal PRE from the test cycle signal generator 1 passes. Since the number of stages can be appropriately selected, the flip-flop circuit 40 outputs the data preset signal PRE delayed by the time corresponding to the number of passage stages of the flip-flop circuit (number of stages × high-speed clock CLOCK cycle) to the determination signal generator 4. Come to do.

The determination signal generator 4 has a clock signal C of a predetermined frequency, like the waveform switching timing signal generator 2.
Strobe ST which operates in response to LOCK input and is activated by input of delay data preset signal PRE from pre-delay circuit 3 and is generated at a predetermined phase timing
The RB is output to the comparator logic circuit 63.

As described above, the timing generating means 53
a delays the strobe signal STRB by the time required for the test signal P2 to pass through the driver 60, the IC under test 66, and the comparator 61, and measures the measured data P3 from the comparator 61 and the expected value data P4 from the data selector 58. It becomes possible to synchronize the timing between them.

In the above embodiment, the timing generating means 53a causes the strobe signal STRB and the measured data P to be measured.
3 has been described, but the present invention is not limited to this, and the present invention can also be applied to the case of synchronizing other data paths.
Further, the skew between the waveform switching timing signals PHASE may be corrected among the plurality of waveform switching timing signal generators 2 in the timing generating means 53a.

[0040]

According to the present invention, there is an effect that the output timing of the timing generating means can be programmatically changed and set without providing an external dedicated timing adjusting means.

[Brief description of drawings]

FIG. 1 is a diagram showing a detailed configuration of an embodiment of a timing generation device of the present invention.

FIG. 2 is a block diagram showing an overall configuration of an IC test apparatus having a timing generator of the present invention.

FIG. 3 is a block diagram showing the overall configuration of a conventional IC test apparatus.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Test period signal generator, 2 ... Waveform switching timing signal generator, 3 ... Pre-delay circuit, 11-1n, 4
0 ... Flip-flop circuit, 20 ... Multiplexer, 3
0 ... Register, 51 ... Control means, 52 ... DC measuring means,
53 ... Timing generating means, 54 ... Pattern generating means,
55 ... Pin control means, 56 ... Pin electronics, 5
7 ... Fail memory, 58 ... Data selector, 59 ... Formatter, 63 ... Comparator logic circuit, 60 ...
Driver, 60 ... Comparator, 64 ... Bus, 65 ... I
C mounting device, 66 ... IC to be measured

Claims (2)

[Claims] 1. A periodic signal generating means for generating a signal having a predetermined period based on a clock signal, and a first signal for inputting this periodic signal and generating a timing signal delayed by a predetermined timing phase difference from the input timing. Timing signal generating means, delay means for delaying the periodic signal by a time corresponding to an integral multiple of the cycle of the clock signal, and the periodic signal delayed by the delay means is input, and a predetermined time is used rather than the input timing. A timing generator for an IC test apparatus, comprising: a second timing signal generator for generating a timing signal delayed by a timing phase difference. 2. The delay means delays the periodic signal so that the timing signal output from the first timing signal generating means is equivalent to the time required for passing through the data path in the IC test apparatus. The timing generator of the IC test apparatus according to claim 1, wherein