JPH11101852A - Variable delay element inspection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable delay element inspection circuit which can simply and easily detect a failure when a wiring route in a variable delay element generates 0 degenerate failure or 1 degenerate failure. SOLUTION: This variable delay element inspection circuit is provided with a first delay element 3 connected with the output end of a first multiplexer 1, a second delay element 4 connected with the output end of a second multiplexer 2, an OR circuit 5 connected with the output ends of the first and the second delay elements 3, 4, and a control circuit 6 controlling the first and the second multiplexers 1, 2. A test mode signal TEST, a first and a second logic forced set signals D0, D1, and a selection signal S are inputted in the control circuit 6. By variously changing the logic of the signals, the 0 degenerate failure and the 1 degenerate failure in the wiring routes in the variable delay elements are detected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for judging pass / fail of various measuring instruments such as a pulse generator and a timing generator of an LSI tester and a variable delay element used in a timing adjustment circuit in an LSI.

[0002]

2. Description of the Related Art A pulse generator or the like is provided with a variable delay element capable of varying a delay amount according to an external control signal. This type of variable delay element is generally configured to select a delay time of the square of the number of bits of the control signal, and as the number of bits of the control signal increases, the selection path of the delay time also increases. The performance test of the device also takes time.

Several techniques have been proposed as techniques for testing the performance of variable delay elements. The first method is to detect an edge of delay data output from a variable delay element to be measured by an LSI tester or various measuring instruments. In the second method, a ring oscillator is configured using a variable delay element to be measured, and a delay amount is detected based on a change in oscillation frequency when a delay setting of the variable delay element is changed. This technique is a technique that is widely and generally used for evaluating AC characteristics of LSIs.

A third technique utilizes a technique relating to phase difference-voltage conversion, and integrates a pulse signal corresponding to a phase difference between a signal under measurement and a reference signal, converts the signal into a voltage, and converts the voltage into a voltage. Is A / D converted to detect the delay amount.

However, the above-described first to third techniques have the following problems. For example, the first method requires a high-performance LSI tester or an individual measuring device capable of generating a small delay amount, and it takes time to inspect the delay elements one by one in order, and the inspection cost is low. Get higher. Furthermore, control by the CPU of the control system is indispensable for searching for an edge position, which complicates processing and takes time.

In the second method, due to circuit limitations of the ring oscillator, the duty ratio must be measured in an inspection focusing on either rising or falling, and a special circuit or measuring device is required. Further, data exchange occurs between the measurement system and the control system, and an enormous amount of time is required for inspection.

The third method requires a settling time for A / D conversion of the integrated voltage, and takes a long time to process as in the first and second methods. Also, the integrated voltage must be within the range of the A / D converter,
It is necessary to adjust the timing of the reference signal according to the delay amount of the delay element.

[0008]

The variable delay element is configured to select a wiring path according to a control signal from a plurality of wiring paths. A fault that is fixed at "0" (0 stuck-at fault)
Also, when a failure (fixed stuck-at 1) occurs that is fixed at "1", the same path is always selected regardless of the logic of the control signal.

However, in the above-described first to third methods, since a performance test is performed based on the output of the variable delay element, some of the wiring paths in the variable delay element have 0 stuck-at faults or 1
Even if a stuck-at fault occurs, the fault may not be detected.

[0010] The present invention has been made in view of such a point, and an object of the present invention is to provide a method in which each of the wiring paths inside the variable delay element causes a 0 stuck-at fault or a 1 stuck-at fault.
An object of the present invention is to provide a variable delay element test circuit that can easily and reliably detect the failure.

[0011]

In order to solve the above-mentioned problem, the invention according to claim 1 selects one of a plurality of delay elements having different delay amounts based on a selection signal. A variable delay element test circuit that delays an input data signal by a delay element selected by the selection circuit and outputs the delayed data signal, and further includes a control circuit that controls a selection operation of the selection circuit. A test mode signal for setting a test mode, a plurality of logic forced setting signals for forcibly setting the logic of the input terminals of the plurality of delay elements in the test mode, and the selection signal. By changing the logic of each signal input to the control circuit and the logic of the input data signal in various ways, the selection circuit, the control circuit and the plurality of The selection circuit and the control circuit are configured so that a stuck-at-0 fault whose logic is fixed at "0" and a stuck-at-1 fault whose logic is fixed at "1" are detected for each of the wiring paths of the extension elements. .

For example, each of the selection circuit and the control circuit includes a plurality of gates.

According to a second aspect of the present invention, in the variable delay element test circuit according to the first aspect, the selection circuit includes a first multiplexer having an output terminal connected to a first delay element;
A second multiplexer having a second delay element connected to an output end thereof, wherein in the test mode, the first and second logic forcible setting signals of the first and second logic forced setting signals are independent of the logic of the input data signal. The signal corresponding to the logic is transmitted to the first and second signals.
And the logic of the input data signal and the first and second signals except when in the test mode.
A signal corresponding to the logic of the logic compulsory setting signal of
And output from the second multiplexer.

According to a third aspect of the present invention, in the variable delay element test circuit according to the first or second aspect, a plurality of variable delay elements comprising the selection circuit, the control circuit, and the plurality of delay elements are connected in cascade. Each of the selection circuits provided inside these variable delay elements individually selects the delay element.

According to a fourth aspect of the present invention, in the variable delay element test circuit according to any one of the first to third aspects, the control circuit comprises: a first register for outputting the first logical forced setting signal; A second logic for outputting the second logic forced setting signal;
And a register.

According to a fifth aspect of the present invention, in the variable delay element test circuit according to any one of the first to third aspects, the first and second forced logic setting signals input to the control circuit are pulse signals. And the control circuit supplies the input first and second logic forced setting signals to the selection circuit without latching the signals inside the circuit.

For example, each circuit element constituting the variable delay element test circuit according to the first to fifth aspects is integrally formed on a semiconductor substrate.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a variable delay element test circuit to which the present invention is applied will be specifically described with reference to the drawings.

[First Embodiment] FIG. 1 is a circuit diagram of a first embodiment showing the internal configuration of a variable delay element test circuit according to the present invention. The variable delay element test circuit shown in FIG. 1 can detect a stuck-at-0 fault fixed to “0” and a stuck-at-1 fault fixed to “1” for all wiring paths inside the variable delay element. Features. The variable delay element test circuit of FIG. 1 is formed integrally with a variable delay element on a semiconductor substrate, and can be used as a normal variable delay element.

The variable delay element test circuit shown in FIG. 1 includes first and second multiplexers 1 and 2, a first delay element 3 connected to an output terminal of the first multiplexer 1, and a second multiplexer 2. Control the second delay element 4 connected to the output terminal of the first and second delay elements 3 and 4, the OR circuit 5 connected to the output terminals of the first and second delay elements 3 and 4, and the first and second multiplexers 1 and 2. And a control circuit 6 for performing the operation.

The delay amount of the first delay element 3 and the delay amount of the second delay element 4 are different from each other, and the signals output from the first and second multiplexers 1 and 2 The signals are delayed by the delay amounts of 3, 4 and input to the OR circuit 5.

The control circuit 6 has a test mode signal TEST for setting a test mode and first and second signals for forcibly setting the logic of the input terminals of the first and second delay elements 3 and 4 in the test mode. 2 and a selection signal S for selecting one of the first and second multiplexers 1 and 2 except during the test mode. The control circuit 6 has OR circuits 7 and 8, and these OR circuits 7 and 8 output signals corresponding to the logic of the test mode signal TEST and the selection signal S.

When the variable delay element test circuit shown in FIG. 1 is used as a variable delay element, the test mode signal TEST
, The first and second logical compulsory setting signals D0 and D1 are both set to “0”. At this time, if the selection signal S is “1”, the first delay element 3 is selected, and if the selection signal S is “0”, the second delay element 4 is selected. The input data signals input to the first and second multiplexers 1 and 2 are the delay elements 3 and 4 selected by the selection signal S.
, And is input to the OR circuit 5.

On the other hand, when the performance test of the variable delay element is performed, the test mode signal TEST, the selection signal S, the first and second logic forced setting signals D0 and D1, and the input data signal are transmitted as shown in FIG. The logics are set to the following 9 types, and outputs of the variable delay elements are detected, and it is determined whether or not each output matches the output logic shown in FIG.

For example, if each input signal of the variable delay element test circuit is set to the logic shown in FIG. 1, the output of the variable delay element test circuit should normally be "0". Is "1", it can be determined that a stuck-at-1 fault has occurred in any of the routes B to N in FIG. Also,
When a stuck-at-0 fault occurs in any of the paths K, L, and P in FIG. 1, the output of the variable delay element changes according to the logic of the input data signal. Can be detected.

As described above, in the variable delay element test circuit shown in FIG. 1, only the logic of the input signal is changed as shown in FIG. A failure can be detected, and a performance test of the variable delay element can be performed simply, quickly, and reliably.

When the variable delay element test circuit of FIG. 1 is used as a normal variable delay element, it may be used alone. However, as shown in FIG. 3, a plurality of variable delay element test circuits are connected in cascade. May be. FIG. 3 shows an example in which variable delay element test circuits having the same configuration as in FIG. 1 are cascaded in three stages. Since the variable delay element test circuits at each stage have their respective delay amounts set individually, a total of eight delay settings can be made. Generally, if the number of stages of the cascade-connected variable delay element test circuit of FIG. 1 is n, the set number of delay amounts is 2n.

FIG. 4A shows the timing waveform of the input data signal, and FIG. 3A shows the timing waveform when each of the variable delay element test circuits at each stage selects the minimum delay amount. FIG. 3 shows a timing waveform when each of the variable delay element test circuits at each stage selects the maximum delay amount.
Assuming (b), Tp which is the difference between the maximum delay amount and the minimum delay amount
Delay data with a resolution of 1/8 of dmax can be output.

[Second Embodiment] In the second embodiment, the first and second logical forcing setting signals D0 and D1 can be set to any fixed levels.

FIG. 5 is a circuit diagram of a second embodiment showing the internal configuration of the variable delay element test circuit according to the present invention. FIG.
Is different from FIG. 1 only in the configuration of the control circuit 6. The control circuit 6 of FIG. 5 includes a register 11 that outputs a first logical compulsory setting signal, and a register 12 that outputs a second logical compulsory setting signal.

Registers 11 and 12 store first and second logical forcible setting signals D0 and D0 synchronized with an internal clock (not shown).
D1 is output, and these signals D0 and D1 are supplied to the selection circuits 1 and 2. The first and second logic forced setting signals D0 and D1 are:
Since the level is maintained at a constant level until the registers 11 and 12 output other data, each time a test pattern is input, the first and second logical forcing setting signals D0 and D0,
You do not need to enter D1.

On the other hand, when it is desired to inspect the AC characteristics of the variable delay element, the control circuit 6 is constructed as shown in FIG. 1 and the first and second logical compulsory setting signals D0, D0,
Just enter D1.

The logic of the input signal of the variable delay element test circuit is not limited to that shown in FIG. The selection circuits 6 and 6 'in FIGS. 1 and 5 select one of the two delay elements 3 and 4, but select one of the three or more selection circuits 6. Is also good.

[0034]

As described above in detail, according to the present invention, the logics of the selection signal, the test mode signal, the logic forced setting signal, and the input data signal are variously changed, so that the inside of the variable delay element is changed. A stuck-at-0 fault and a stuck-at-1 fault can be detected for each of the wiring paths.
In particular, according to the present invention, even if the number of logic patterns of each input signal is small, a stuck-at-0 fault and a stuck-at-1 fault can be detected, and a performance test of a variable delay element can be performed simply, quickly, and reliably. Further, by using a pulse signal as the logic compulsory setting signal, the AC operation of the variable delay element can be inspected.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment showing an internal configuration of a variable delay element test circuit.

FIG. 2 is a diagram showing the logic of each input / output signal of the variable delay element test circuit.

FIG. 3 is a diagram showing an example in which the variable delay element test circuits of FIG. 1 are cascaded in three stages.

FIG. 4A is a timing waveform diagram of an input data signal,
(B), (c) is a timing waveform diagram showing the output of the variable delay element.

FIG. 5 is a circuit diagram of a second embodiment showing an internal configuration of a variable delay element test circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st multiplexer 2 2nd multiplexer 3 1st delay element 4 2nd delay element 5,7,8 OR circuit 6 delay circuit 11,12 register

Claims (5)

[Claims] A selecting circuit for selecting any one of a plurality of delay elements having different delay amounts based on a selection signal, wherein an input data signal is selected by the delay element selected by the selecting circuit. A variable delay element test circuit for delaying and outputting the control circuit, comprising: a control circuit for controlling a selection operation of the selection circuit, wherein the control circuit includes a test mode signal for setting a test mode, and the plurality of test modes during the test mode. A plurality of logic forced setting signals for forcibly setting the logic of the input terminal of each of the delay elements, and the selection signal, and the logic of each of the signals input to the control circuit and the logic of the input data signal Are variously changed so that the logic of each of the selection circuit, the control circuit, and the wiring path of the plurality of delay elements is fixed to “0”. A variable delay element test circuit comprising: the selection circuit and the control circuit configured to detect a stuck-at fault and a stuck-at-one fault whose logic is fixed to “1”. 2. The selection circuit has a first multiplexer having an output terminal connected to a first delay element, and a second multiplexer having an output terminal connected to a second delay element. In the test mode, a signal corresponding to the logic of the first and second logic compulsory setting signals is output from the first and second multiplexers independently of the logic of the input data signal; And outputting a signal corresponding to the logic of the input data signal and the logic of the first and second logic compulsory setting signals from the first and second multiplexers. 2. The variable delay element test circuit according to 1. 3. A variable delay element comprising said selection circuit, said control circuit and said plurality of delay elements are connected in cascade, and said selection circuits provided inside said variable delay elements are individually connected to said selection circuits. 3. The variable delay element test circuit according to claim 1, wherein a delay element is selected. 4. The control circuit according to claim 1, further comprising a first register for outputting the first logical forcing setting signal, and a second register for outputting the second logical forcing setting signal. The variable delay element test circuit according to claim 1. 5. The first and second logical forcing setting signals input to the control circuit are pulse signals, and the control circuit outputs the first and second logical forcing setting signals input thereto. 4. The variable delay element test circuit according to claim 1, wherein the variable delay element test circuit is supplied to the selection circuit without latching inside the circuit.